diff options
Diffstat (limited to 'arch/arm/plat-samsung')
| -rw-r--r-- | arch/arm/plat-samsung/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/gpiolib.c | 206 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/cpu.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/debug-macro.S | 2 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/devs.h | 6 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/irq-vic-timer.h | 2 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-serial.h | 2 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/uncompress.h | 4 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/irq-uart.c | 83 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/irq-vic-timer.c | 69 |
12 files changed, 44 insertions, 334 deletions
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index be72100b81b4..4d79519d19a4 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -8,6 +8,7 @@ config PLAT_SAMSUNG bool depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P select NO_IOPORT + select GENERIC_IRQ_CHIP default y help Base platform code for all Samsung SoC based systems diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index e9de58a2e294..53eb15b0a07d 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -19,7 +19,6 @@ obj-y += gpio.o obj-y += gpio-config.o obj-y += dev-asocdma.o -obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c deleted file mode 100644 index ea37c0461788..000000000000 --- a/arch/arm/plat-samsung/gpiolib.c +++ /dev/null @@ -1,206 +0,0 @@ -/* arch/arm/plat-samsung/gpiolib.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * SAMSUNG - GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -#ifndef DEBUG_GPIO -#define gpio_dbg(x...) do { } while (0) -#else -#define gpio_dbg(x...) printk(KERN_DEBUG x) -#endif - -/* The samsung_gpiolib_4bit routines are to control the gpio banks where - * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the - * following example: - * - * base + 0x00: Control register, 4 bits per gpio - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n - * - * Note, since the data register is one bit per gpio and is at base + 0x4 - * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of - * the output. -*/ - -static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - - con = __raw_readl(base + GPIOCON_OFF); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + GPIOCON_OFF); - - gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); - - return 0; -} - -static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - unsigned long dat; - - con = __raw_readl(base + GPIOCON_OFF); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + GPIODAT_OFF); - - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, base + GPIOCON_OFF); - __raw_writel(dat, base + GPIODAT_OFF); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -/* The next set of routines are for the case where the GPIO configuration - * registers are 4 bits per GPIO but there is more than one register (the - * bank has more than 8 GPIOs. - * - * This case is the similar to the 4 bit case, but the registers are as - * follows: - * - * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x08: Data register, 1 bit per gpio - * bit n: data bit n - * - * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we - * store the 'base + 0x4' address so that these routines see the data - * register at ourchip->base + 0x04. - */ - -static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); - - gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); - - return 0; -} - -static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long dat; - unsigned con_offset = offset; - - if (con_offset > 7) - con_offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(con_offset)); - con |= 0x1 << con_4bit_shift(con_offset); - - dat = __raw_readl(base + GPIODAT_OFF); - - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, regcon); - __raw_writel(dat, base + GPIODAT_OFF); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = samsung_gpiolib_4bit_input; - chip->chip.direction_output = samsung_gpiolib_4bit_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = samsung_gpiolib_4bit2_input; - chip->chip.direction_output = samsung_gpiolib_4bit2_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - samsung_gpiolib_add_4bit(chip); - s3c_gpiolib_add(chip); - } -} - -void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - samsung_gpiolib_add_4bit2(chip); - s3c_gpiolib_add(chip); - } -} - -void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) - s3c_gpiolib_add(chip); -} diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 3aedac0034ba..c0a5741b23e6 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -86,7 +86,6 @@ extern struct sysdev_class s3c2443_sysclass; extern struct sysdev_class s3c6410_sysclass; extern struct sysdev_class s3c64xx_sysclass; extern struct sysdev_class s5p64x0_sysclass; -extern struct sysdev_class s5p6442_sysclass; extern struct sysdev_class s5pv210_sysclass; extern struct sysdev_class exynos4_sysclass; diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S index dc6efd90e8ff..207e275362a8 100644 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ b/arch/arm/plat-samsung/include/plat/debug-macro.S @@ -11,7 +11,7 @@ #include <plat/regs-serial.h> -/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */ +/* The S5PV210/S5PC110 implementations are as belows. */ .macro fifo_level_s5pv210 rd, rx ldr \rd, [ \rx, # S3C2410_UFSTAT ] diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 39818d8da420..b61b8ee7cc52 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -111,12 +111,6 @@ extern struct platform_device exynos4_device_spdif; extern struct platform_device exynos4_device_pd[]; extern struct platform_device exynos4_device_ahci; -extern struct platform_device s5p6442_device_pcm0; -extern struct platform_device s5p6442_device_pcm1; -extern struct platform_device s5p6442_device_iis0; -extern struct platform_device s5p6442_device_iis1; -extern struct platform_device s5p6442_device_spi; - extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6440_device_iis; diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h index a90b53431b5b..5b9c42fd32d7 100644 --- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h @@ -10,4 +10,4 @@ * published by the Free Software Foundation. */ -extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); +extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq); diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 788837e99cb3..c151c5f94a87 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -194,7 +194,7 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 -/* Following are specific to S5PV210 and S5P6442 */ +/* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) #define S5PV210_UCON_PCLK (0<<10) #define S5PV210_UCON_UCLK (1<<10) diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index ff1a561b326e..0ffe34a21554 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -69,6 +69,5 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); -extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); #endif /* __S3C64XX_PLAT_SPI_H */ diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 7d6ed7263d57..ee48e12a1e72 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -18,8 +18,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ /* uart setup */ -static unsigned int fifo_mask; -static unsigned int fifo_max; +unsigned int fifo_mask; +unsigned int fifo_max; /* forward declerations */ diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4d4e571af553..32582c0958e3 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -27,60 +27,6 @@ /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. */ - -static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) -{ - struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -static void s3c_irq_uart_mask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) { struct s3c_uart_irq *uirq = desc->irq_data.handler_data; @@ -97,30 +43,25 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) generic_handle_irq(base + 3); } -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .irq_mask = s3c_irq_uart_mask, - .irq_unmask = s3c_irq_uart_unmask, - .irq_mask_ack = s3c_irq_uart_maskack, - .irq_ack = s3c_irq_uart_ack, -}; - static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) { void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; /* mask all interrupts at the start. */ __raw_writel(0xf, reg_base + S3C64XX_UINTM); - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq); - irq_set_chip_data(irq, uirq); - set_irq_flags(irq, IRQF_VALID); - } + gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->regs.ack = S3C64XX_UINTP; + ct->regs.mask = S3C64XX_UINTM; + irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); irq_set_handler_data(uirq->parent_irq, uirq); irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index d6ad66ab9290..a607546ddbd0 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -28,60 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) } /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(struct irq_data *data) +static void s3c_irq_timer_ack(struct irq_data *d) { - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 mask = (1 << 5) << (d->irq - gc->irq_base); - reg &= 0x1f; /* mask out pending interrupts */ - reg |= mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); + irq_reg_writel(mask | gc->mask_cache, gc->reg_base); } -static void s3c_irq_timer_ack(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; - reg |= mask << 5; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .irq_mask = s3c_irq_timer_mask, - .irq_unmask = s3c_irq_timer_unmask, - .irq_ack = s3c_irq_timer_ack, -}; - /** * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ - * @parent_irq: The parent IRQ on the VIC for the timer. - * @timer_irq: The IRQ to be used for the timer. + * @num: Number of timers to initialize + * @timer_irq: Base IRQ number to be used for the timers. * * Register the necessary IRQ chaining and support for the timer IRQs * chained of the VIC. */ -void __init s3c_init_vic_timer_irq(unsigned int parent_irq, - unsigned int timer_irq) +void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) { + unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; + struct irq_chip_generic *s3c_tgc; + struct irq_chip_type *ct; + unsigned int i; - irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer); - irq_set_handler_data(parent_irq, (void *)timer_irq); + s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, + S3C64XX_TINT_CSTAT, handle_level_irq); + ct = s3c_tgc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_ack = s3c_irq_timer_ack; + irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + /* Clear the upper bits of the mask_cache*/ + s3c_tgc->mask_cache &= 0x1f; - irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq); - irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); - set_irq_flags(timer_irq, IRQF_VALID); + for (i = 0; i < num; i++, timer_irq++) { + irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); + irq_set_handler_data(pirq[i], (void *)timer_irq); + } } |