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Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32v234.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/s32v234.dtsi254
1 files changed, 254 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
new file mode 100644
index 000000000000..47db198b36ad
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/s32v234-clock.h>
+#include <dt-bindings/pinctrl/s32v234-pinctrl.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,s32v234";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ firc {
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+ fxosc {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80000000>;
+ next-level-cache = <&cluster0_l2_cache>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80000000>;
+ next-level-cache = <&cluster0_l2_cache>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80000000>;
+ next-level-cache = <&cluster1_l2_cache>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80000000>;
+ next-level-cache = <&cluster1_l2_cache>;
+ };
+
+ cluster0_l2_cache: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2_cache: l2-cache1 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ /* clock-frequency might be modified by u-boot, depending on the
+ * chip version.
+ */
+ clock-frequency = <10000000>;
+ };
+
+ gic: interrupt-controller@7d001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x7d001000 0 0x1000>,
+ <0 0x7d002000 0 0x2000>,
+ <0 0x7d004000 0 0x2000>,
+ <0 0x7d006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ aips0: aips-bus@40000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ reg = <0x0 0x40000000 0x0 0x7d000>;
+ ranges;
+
+ fec: ethernet@40032000 {
+ compatible = "fsl,s32v234-fec";
+ reg = <0x0 0x40032000 0x0 0x1000>;
+ interrupt-names = "int0", "int1", "int2", "pps";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks S32V234_CLK_SYS6>,
+ <&clks S32V234_CLK_SYS3>,
+ <&clks S32V234_CLK_ENET_TIME>,
+ <&clks S32V234_CLK_ENET>,
+ <&clks S32V234_CLK_ENET_TIME>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref",
+ "enet_out";
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
+ status = "disabled";
+ };
+
+ clks: mc_cgm0@4003c000 {
+ compatible = "fsl,s32v234-mc_cgm0";
+ reg = <0x0 0x4003C000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mc_cgm1: mc_cgm1@4003F000 {
+ compatible = "fsl,s32v234-mc_cgm1";
+ reg = <0x0 0x4003F000 0x0 0x1000>;
+ };
+
+ mc_cgm2: mc_cgm2@40042000 {
+ compatible = "fsl,s32v234-mc_cgm2";
+ reg = <0x0 0x40042000 0x0 0x1000>;
+ };
+
+ mc_cgm3: mc_cgm3@40045000 {
+ compatible = "fsl,s32v234-mc_cgm3";
+ reg = <0x0 0x40045000 0x0 0x1000>;
+ };
+
+ mc_me: mc_me@4004a000 {
+ compatible = "fsl,s32v234-mc_me";
+ reg = <0x0 0x4004A000 0x0 0x1000>;
+ };
+
+ uart0: serial@40053000 {
+ compatible = "fsl,s32v234-linflexuart";
+ reg = <0x0 0x40053000 0x0 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clks S32V234_CLK_LIN>;
+ clock-names = "lin";
+ status = "disabled";
+ };
+
+ can0: flexcan@40055000 {
+ compatible = "fsl,s32v234-flexcan";
+ reg = <0x0 0x40055000 0x0 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks S32V234_CLK_CAN>,
+ <&clks S32V234_CLK_CAN>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ usdhc0: usdhc@4005d000 {
+ compatible = "fsl,s32v234-usdhc";
+ reg = <0x0 0x4005D000 0x0 0x1000>;
+ interrupts = <0 28 4>;
+ clocks = <&clks S32V234_CLK_SDHC>,
+ <&clks S32V234_CLK_SDHC>,
+ <&clks S32V234_CLK_SDHC>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <8>;
+ status = "disabled";
+ };
+
+ siul2: siul@4006c000 {
+ compatible = "fsl,s32v234-siul2";
+ reg = <0x0 0x4006C000 0x0 0x1794>;
+ status = "disabled";
+ };
+
+ src: src@4007c000 {
+ compatible = "fsl,s32v234-src";
+ reg = <0x0 0x4007C000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+ };
+
+ aips1: aips-bus@40080000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ reg = <0x0 0x40080000 0x0 0x70000>;
+ ranges;
+
+ uart1: serial@400bc000 {
+ compatible = "fsl,s32v234-linflexuart";
+ reg = <0x0 0x400bc000 0x0 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clks S32V234_CLK_LIN>;
+ clock-names = "lin";
+ status = "disabled";
+ };
+
+ can1: flexcan@400be000 {
+ compatible = "fsl,s32v234-flexcan";
+ reg = <0x0 0x400be000 0x0 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks S32V234_CLK_CAN>,
+ <&clks S32V234_CLK_CAN>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+ };
+};
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-10 14:02:48 +0000