diff options
Diffstat (limited to 'arch/arm64/boot')
65 files changed, 8861 insertions, 120 deletions
diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile index 1f012c506434..cd3414898d10 100644 --- a/arch/arm64/boot/Makefile +++ b/arch/arm64/boot/Makefile @@ -16,7 +16,7 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S -targets := Image Image.gz +targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index 2beef9e6cb88..aa0b3844ad63 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -126,9 +126,9 @@ ®_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; ®_dcdc2 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index 338e786155b1..2ef779b02757 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -120,10 +120,14 @@ /* DCDC3 is polyphased with DCDC2 */ +/* + * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal + * 1.35V that the PMIC can drive. + */ ®_dcdc5 { regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; regulator-name = "vcc-ddr3"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8c8db1b057df..788a6f8c5994 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -274,7 +274,8 @@ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu 58>; + clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index e79f3defe002..c2ad4f97cef0 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -56,10 +56,10 @@ pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <0 120 8>, - <0 121 8>, - <0 122 8>, - <0 123 8>; + interrupts = <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi index 125f4deb52fe..b664e7af74eb 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -107,7 +107,7 @@ clock-names = "uartclk", "apb_pclk"; }; - spi0: ssp@e1020000 { + spi0: spi@e1020000 { status = "disabled"; compatible = "arm,pl022", "arm,primecell"; reg = <0 0xe1020000 0 0x1000>; @@ -117,7 +117,7 @@ clock-names = "apb_pclk"; }; - spi1: ssp@e1030000 { + spi1: spi@e1030000 { status = "disabled"; compatible = "arm,pl022", "arm,primecell"; reg = <0 0xe1030000 0 0x1000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 4b17a76959b2..c83c028e95af 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -178,7 +178,7 @@ pinctrl-names = "default"; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", "VCCK En", "CON1 Header Pin31", "I2S Header Pin6", "IR In", "I2S Header Pin7", @@ -186,7 +186,7 @@ "I2S Header Pin5", "HDMI CEC", "SYS LED"; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index c3c65b06ba76..5da604e5cf28 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -189,7 +189,7 @@ pinctrl-names = "default"; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", "USB HUB nRESET", "USB OTG Power En", "J7 Header Pin2", "IR In", "J7 Header Pin4", @@ -197,7 +197,7 @@ "HDMI CEC", "SYS LED"; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", @@ -295,7 +295,7 @@ }; &usb0_phy { - status = "okay"; + status = "disabled"; phy-supply = <&usb_otg_pwr>; }; @@ -305,7 +305,7 @@ }; &usb0 { - status = "okay"; + status = "disabled"; }; &usb1 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index af834cdbba79..250b5c11c0e2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -413,7 +413,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index edc512ad0bac..ce4a116382bf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -33,11 +33,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + power-button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; @@ -112,7 +110,7 @@ linux,rc-map-name = "rc-geekbox"; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "Power Key In", @@ -125,7 +123,7 @@ "SYS LED"; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index d71cbf596d1f..407d32f4fe73 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -14,7 +14,7 @@ / { compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Libre Technology CC"; + model = "Libre Computer Board AML-S905X-CC"; aliases { serial0 = &uart_AO; @@ -139,7 +139,7 @@ }; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "Blue LED", @@ -152,7 +152,7 @@ "7J1 Header Pin13"; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -226,7 +226,6 @@ cap-mmc-highspeed; mmc-ddr-3_3v; max-frequency = <50000000>; - non-removable; disable-wp; mmc-pwrseq = <&emmc_pwrseq>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index fb8d76a17bc5..3c3057944960 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -310,7 +310,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index f165f04db0c9..13ee8ffa9bbf 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -5,7 +5,6 @@ /* * Devices shared by all Juno boards */ - dma-ranges = <0 0 0 0 0x100 0>; memtimer: timer@2a810000 { compatible = "arm,armv7-timer-mem"; diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi index e5e265dfa902..2870b5eeb198 100644 --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi +++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi @@ -8,10 +8,10 @@ */ / { /* SoC fixed clocks */ - soc_uartclk: refclk7273800hz { + soc_uartclk: refclk7372800hz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <7273800>; + clock-frequency = <7372800>; clock-output-names = "juno:uartclk"; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi index 15214d05fec1..8c20d4a0cb4e 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -42,13 +42,14 @@ pinmux: pinmux@0014029c { compatible = "pinctrl-single"; - reg = <0x0014029c 0x250>; + reg = <0x0014029c 0x26c>; #address-cells = <1>; #size-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xf>; pinctrl-single,gpio-range = < - &range 0 154 MODE_GPIO + &range 0 91 MODE_GPIO + &range 95 60 MODE_GPIO >; range: gpio-range { #pinctrl-single,gpio-range-cells = <3>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 2b76293b51c8..3d2921ef2935 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -444,8 +444,7 @@ <&pinmux 108 16 27>, <&pinmux 135 77 6>, <&pinmux 141 67 4>, - <&pinmux 145 149 6>, - <&pinmux 151 91 4>; + <&pinmux 145 149 6>; }; i2c1: i2c@000e0000 { diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c205e89bcab6..77f08d0f55a2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -57,7 +57,10 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-lpddr4-arm2-hsic.dtb \ fsl-imx8dm-lpddr4-arm2.dtb \ fsl-imx8qp-lpddr4-arm2.dtb \ - fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb + fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb \ + fsl-imx8qm-apalis-eval.dtb \ + fsl-imx8qm-apalis-v1.1-eval.dtb \ + fsl-imx8qm-apalis-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-mek.dtb \ fsl-imx8qxp-mek-rpmsg.dtb \ @@ -103,7 +106,13 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8dx-mek-it6263-lvds1-dual-channel.dtb \ fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \ fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \ - fsl-imx8dxp-lpddr4-arm2.dtb + fsl-imx8dxp-lpddr4-arm2.dtb \ + fsl-imx8qxp-apalis-eval.dtb \ + fsl-imx8qxp-colibri-aster.dtb \ + fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb \ + fsl-imx8qxp-colibri-eval-v3.dtb \ + fsl-imx8qxp-colibri-lvds-dual-eval-v3.dtb \ + fsl-imx8qxp-colibri-lvds-single-eval-v3.dtb dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ fsl-imx8mq-ddr4-arm2.dtb \ fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \ @@ -143,7 +152,11 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \ fsl-imx8mm-evk-revb.dtb \ fsl-imx8mm-evk-revb-rm67191.dtb \ fsl-imx8mm-ddr4-evk-rm67191.dtb \ - fsl-imx8mm-ddr4-qca9377-evk.dtb + fsl-imx8mm-ddr4-qca9377-evk.dtb \ + fsl-imx8mm-verdin-nonwifi-dahlia.dtb \ + fsl-imx8mm-verdin-nonwifi-dev.dtb \ + fsl-imx8mm-verdin-wifi-dahlia.dtb \ + fsl-imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_FSL_IMX8MN) += fsl-imx8mn-ddr4-evk.dtb \ fsl-imx8mn-evk.dtb \ fsl-imx8mn-evk-rpmsg.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 72040461e67a..3aebf64eaa2b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1814,9 +1814,7 @@ assigned-clocks = <&clk IMX8QXP_LCD_SEL>, <&clk IMX8QXP_LCD_PXL_SEL>, <&clk IMX8QXP_ELCDIF_PLL_DIV>; - assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>, - <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; - assigned-clock-rates = <0>, <24000000>, <804000000>; + assigned-clock-rates = <0>, <0>, <804000000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_dma_lcd0>; status = "disabled"; @@ -2388,6 +2386,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2705,6 +2704,118 @@ power-domains = <&pd_mipi_csi>; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; + status = "disabled"; + }; + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; + status = "disabled"; + }; + gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dahlia.dtsi new file mode 100755 index 000000000000..b71a67683fab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dahlia.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +#include "fsl-imx8mm-verdin-dev.dtsi" + +&gpio_expander_21 { + status = "disabled"; +}; + +&sound_card { + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dev.dtsi new file mode 100755 index 000000000000..66a8d6c49a19 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dev.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&csi1_bridge { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + status = "okay"; + + spidev20: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +&gpio_expander_21 { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&lvds_bridge { + status = "disabled"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +/* MIPI-DSI to HDMI adapter */ +&mipi_dsi_hdmi { + status = "okay"; +}; + +&ov5640_mipi { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* VERDIN I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Audio Codec */ +&wm8904_1a { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi-dahlia.dts new file mode 100755 index 000000000000..547852506884 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi-dahlia.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8mm-verdin-nonwifi.dtsi" +#include "fsl-imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dahlia", + "toradex,verdin-imx8mm-nonwifi", "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi-dev.dts new file mode 100755 index 000000000000..3cb6c9e30686 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi-dev.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8mm-verdin-nonwifi.dtsi" +#include "fsl-imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dev", + "toradex,verdin-imx8mm-nonwifi", "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi.dtsi new file mode 100755 index 000000000000..0acf988c8b44 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-nonwifi.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +#include "fsl-imx8mm-verdin.dtsi" + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_162", + "SODIMM_164", + "SODIMM_166", + "SODIMM_168", + "SODIMM_66", + "SODIMM_17", + "", + "SODIMM_156", + "SODIMM_160", + "SODIMM_244", + "SODIMM_250", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "SODIMM_148", + "SODIMM_152", + "SODIMM_154", + "SODIMM_174", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_150", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; + +&usdhc3 { + bus-width = <4>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +}; + +&iomuxc { + pinctrl_tsp: tspgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* SODIMM 148 */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* SODIMM 152 */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140 /* SODIMM 154 */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 /* SODIMM 179 */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 /* SODIMM 150 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi-dahlia.dts new file mode 100755 index 000000000000..3ce172f5f183 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi-dahlia.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8mm-verdin-wifi.dtsi" +#include "fsl-imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-wifi-dahlia", + "toradex,verdin-imx8mm-wifi", "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi-dev.dts new file mode 100755 index 000000000000..335f4a22e6de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi-dev.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8mm-verdin-wifi.dtsi" +#include "fsl-imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-wifi-dev", + "toradex,verdin-imx8mm-wifi", "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi.dtsi new file mode 100755 index 000000000000..8f96832677b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-wifi.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +#include "fsl-imx8mm-verdin.dtsi" + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-name = "V3.3_WI-FI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + wifi-host; + status = "okay"; +}; + +&iomuxc { + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ + >; + }; + + pinctrl_wifi_i2s: bti2sgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 /* WIFI_TX_BCLK */ + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 /* WIFI_TX_DATA0 */ + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 /* WIFI_TX_SYNC */ + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 /* WIFI_RX_DATA0 */ + >; + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + >; + }; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "SODIMM_17", + "", + "", + "", + "SODIMM_244", + "SODIMM_250", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "", + "", + "", + "SODIMM_174", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi new file mode 100755 index 000000000000..cb6b6d7287ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi @@ -0,0 +1,1330 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019-2020 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8mm.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bkl_en>; + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + power-supply = <®_3p3v>; + status = "disabled"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon"; + stdout-path = &uart1; + }; + + /* fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + /* Carrier Board Supply */ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "REG_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_aux_usb: regulator-aux-usb { + compatible = "regulator-fixed"; + regulator-name = "REG_AUX_USB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_mipi_phy: regulator-mipi-phy { + compatible = "regulator-fixed"; + regulator-name = "REG_MIPI_PHY"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + reg_ethphy: regulator-ethphy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-boot-on; + regulator-name = "V3.3_ETH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB1_EN */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB2_EN */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-name = "V3.3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + off-on-delay = <100000>; + }; + + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +/* + * The AUDIO PLLs support max 650MHz, so use the suitable settings. + * Originally introduced by NXP in the NXP commit a4b0c7c3fadc7. + */ +&clk { + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&csi1_bridge { + fsl,mipi-mode; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +/* On-module CAN controller 1 & 2 */ +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, + <&gpio1 5 GPIO_ACTIVE_LOW>; + /* This property is required, even if marked as obsolete in the doku */ + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can1: can@0 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + microchip,clock-allways-on; + microchip,clock-out-div = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + can2: can@1 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_int>; + reg = <1>; + spi-max-frequency = <2000000>; + /* not assembled */ + status = "disabled"; + }; +}; + +&fec1 { + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + phy-supply = <®_ethphy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; +#if 0 + flash0: mt25qu256aba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu256aba"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +#endif +}; + +&gpio1 { + gpio-line-names = "SODIMM_216", + "SODIMM_19", + "", + "", + "", + "", + "", + "", + "SODIMM_220", + "SODIMM_222", + "", + "SODIMM_218", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_187"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; +}; + +&gpio4 { + /* + * The SE050 security element may be driven via I2C from user space. + * The element itself is enabled here as it has no kernel driver. + */ + se050_ena { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + line-name = "SE050_ENABLE"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_se050_ena>; + }; +}; + +&gpio5 { + gpio-line-names = "SODIMM_131", + "", + "SODIMM_91", + "SODIMM_16", + "SODIMM_15", + "SODIMM_208", + "SODIMM_137", + "SODIMM_139", + "SODIMM_141", + "SODIMM_143", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_151", + "SODIMM_153"; + + ctrl_sleep_moci { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pintctrl_ctrl_sleep_moci>; + }; +}; + +&gpu { + status = "okay"; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + compatible = "rohm,bd71840", "rohm,bd71837"; + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x4b>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + buck1_reg: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck1"; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck2"; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck5_reg: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck5"; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + buck6_reg: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck6"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + buck7_reg: BUCK7 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck7"; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + }; + + buck8_reg: BUCK8 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck8"; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + ldo1_reg: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo1"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + ldo2_reg: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo2"; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + }; + + ldo3_reg: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo4"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + ldo5_reg: LDO5 { + regulator-compatible = "ldo5"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo6"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; + + rtc: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + adc: adc@34 { + compatible = "maxim,max11607"; + reg = <0x34>; + vcc-supply = <&ldo5_reg>; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +/* Verdin I2C_3_HDMI N/A */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "csi_mclk"; + clocks = <&clk IMX8MM_CLK_CLKO1>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + PVDD-supply = <®_3p3v>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; + pwn-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + + /* Audio Codec */ + wm8904_1a: codec@1a { + compatible = "wlf,wm8904"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + clock-names = "mclk"; + reg = <0x1a>; + status = "disabled"; + DCVDD-supply = <®_3p3v>; + DBVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + CPVDD-supply = <®_3p3v>; + MICVDD-supply = <®_3p3v>; + }; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + status = "disabled"; + vcc-supply = <®_3p3v>; + }; + + lvds_bridge: bridge@2c { + compatible = "ti,sn65dsi83"; + enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + reg = <0x2c>; + ti,dsi-lanes = <4>; + ti,lvds-bpp = <24>; + ti,lvds-format = <2>; + ti,height-mm = <136>; + ti,width-mm = <217>; + status = "disabled"; + + display-timings { + native-mode = <&lvds_timing0>; + lvds_timing0: lt170410_2whc { + /* + * Take the minimum pixelclock as 71.1 MHz is + * not working on iMX8MM + */ + clock-frequency = <68900000>; + hactive = <1280 1280 1280>; + hfront-porch = <23 60 71>; + hback-porch = <23 60 71>; + hsync-len = <15 40 47>; + vactive = <800 800 800>; + vfront-porch = <5 7 10>; + vback-porch = <5 7 10>; + vsync-len = <6 9 12>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + port{ + dsi85_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + + /* Current measurement into module VCC */ + hwmon: hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "disabled"; + }; + + /* MIPI-DSI to HDMI adapter */ + mipi_dsi_hdmi: hdmi@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c2>; + hpd-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hpd>, <&pinctrl_gpio1>, + <&pinctrl_gpio2>; + reg = <0x48>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 17 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hpd>, <&pinctrl_gpio2>; + reg = <0x4a>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* SODIMM 208 */ + status = "disabled"; + }; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + status = "disabled"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + mipi-phy-supply = <®_mipi_phy>; + + port { + mipi1_sensor_ep: endpoint1 { + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + data-lanes = <2>; + remote-endpoint = <&ov5640_mipi1_ep>; + }; + + csi1_mipi_ep: endpoint2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_dsi { + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; + +&mu { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + /* on-module ext oscillator */ + clkreq-gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + epdev_on-supply = <®_3p3v>; + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_2 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; +}; + +/* VERDIN I2S_1 */ +&sai2 { + #sound-dai-cells = <0>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; +}; + +/* Verdin UART_3 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_4 */ +/* + * resource allocated to M4 by default, must not be accessed from A-35 or you + * get an OOPS + */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbmisc1 { + vbus-wakeup-supply = <®_aux_usb>; +}; + +&usbmisc2 { + vbus-wakeup-supply = <®_aux_usb>; +}; + +/* Verdin USB_1 */ +&usbotg1 { + dr_mode = "otg"; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg1_vbus>; +}; + +/* Verdin USB_2 */ +&usbotg2 { + dr_mode = "host"; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usbphynop1 { + vcc-supply = <®_aux_usb>; +}; + +&usbphynop2 { + vcc-supply = <®_aux_usb>; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pm-ignore-notify; + status = "okay"; + /* TODO Strobe */ +}; + +/* Verdin SD_1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio7>, + <&pinctrl_gpio8>, <&pinctrl_gpio_hog1>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_sai5>; + + pinctrl_can1_int: can1intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 /* CAN_1_SPI_INT#_1.8V */ + >; + }; + + pinctrl_can2_int: can2intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 /* CAN_2_SPI_INT#_1.8V */ + >; + }; + + pinctrl_ctrl_force_off_moci: ctrlforceoffgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */ + >; + }; + + pintctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* CTRL_SLEEP_MOCI */ + >; + }; + + pinctrl_dsi_bkl_en: dsi_bkl_en { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + >; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + >; + }; + + /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */ + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + >; + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + >; + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + >; + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + >; + }; + + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ + >; + }; + + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ + >; + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ + >; + }; + + /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */ + pinctrl_gpio_hpd: gpiohpdgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4 /* SODIMM 252 */ + >; + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */ + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /* PMIC_INT# */ + >; + }; + + pinctrl_pwm_1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */ + >; + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */ + >; + }; + + pinctrl_pwm_3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */ + >; + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 /* PMIC_EN_ETH */ + >; + }; + + pinctrl_reg_usb1_en: regusb1engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + >; + }; + + pinctrl_reg_usb2_en: regusb2engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ + >; + }; + + pinctrl_se050_ena: se050enagrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184 /* PMIC_TPM_ENA */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1c4 /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1c4 /* SODIMM 147 */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1c4 /* SODIMM 129 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1c4 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + >; + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + /* On-module Wi-Fi/BT or SDHC interface on the X52 extention slot */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 /* PMIC_WDI */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index 6619f05b694e..c29bdebc139d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -766,6 +766,7 @@ fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; + max-frequency = <100000000>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dts new file mode 100644 index 000000000000..bef11172983e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qm-apalis.dtsi" +#include "fsl-imx8qm-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8qm-eval", "toradex,apalis-imx8qm", "fsl,imx8qm"; +};
\ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dtsi new file mode 100644 index 000000000000..6153e6ad1b46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dtsi @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC USBH2(ABCD) / USBH(3|4)"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&lvds1_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio2 { + /* + * Add GPIO2_20 as a wakeup source: + * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: 20 + */ + pad-wakeup = <101 5 20>; + pad-wakeup-num = <1>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "okay"; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QM_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio12>; + pwn-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis BKL1_PWM */ +&lvds1_pwm { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +&pixel_combiner1 { + status = "okay"; +}; + +&pixel_combiner2 { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&rpmsg { + status = "okay"; +}; + +&rpmsg1 { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&sai7 { + status = "okay"; +}; + +&sai_hdmi_tx { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&wakeup_key { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dts new file mode 100644 index 000000000000..7a79599123a4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qm-apalis.dtsi" +#include "fsl-imx8qm-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Ixora Board"; + compatible = "toradex,apalis-imx8qm-ixora", "toradex,apalis-imx8qm", + "toradex,apalis-ixora", "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dtsi new file mode 100644 index 000000000000..0b85e608ce95 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dtsi @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + /* MXM3_188 */ + led4-green { + label = "LED_4_GREEN"; + gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_178 */ + led4-red { + label = "LED_4_RED"; + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_152 */ + led5-green { + label = "LED_5_GREEN"; + gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_156 */ + led5-red { + label = "LED_5_RED"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC_USBH(2|4)"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&lvds1_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio5 { + ngpios = <32>; + gpio-line-names = "gpio5-01", "gpio5-02", "gpio5-03", "gpio5-04", + "gpio5-05", "gpio5-06", "gpio5-07", "gpio5-08", + "gpio5-09", "gpio5-10", "gpio5-11", "gpio5-12", + "gpio5-13", "gpio5-14", "gpio5-15", "gpio5-16", + "gpio5-17", "gpio5-18", "gpio5-19", "LED-5-GREEN", + "LED-5-RED", "gpio5-22", "gpio5-23", "gpio5-24", + "UART24-FORCEOFF", "gpio5-26", "LED-4-GREEN", "gpio5-28", + "LED-4-RED", "gpio5-30", "gpio5-31", "gpio5-32"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "okay"; + }; +}; + +/* Apalis I2C_CAM1 */ +&i2c3 { + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QM_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio12>; + pwn-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio34>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>, + <&pinctrl_uart24_forceoff>; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 0x41 /* LED_4_GREEN */ + SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 0x41 /* LED_4_RED */ + SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 0x41 /* LED_5_GREEN */ + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x41 /* LED_5_RED */ + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 + >; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis BKL1_PWM */ +&lvds1_pwm { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +&pixel_combiner1 { + status = "okay"; +}; + +&pixel_combiner2 { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&rpmsg { + status = "okay"; +}; + +&rpmsg1 { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&sai7 { + status = "okay"; +}; + +&sai_hdmi_tx { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&wakeup_key { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..076cc394801c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1-eval.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qm-apalis-v1.1.dtsi" +#include "fsl-imx8qm-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8qm-v1.1-eval", "toradex,apalis-imx8qm", "fsl,imx8qm"; +};
\ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi new file mode 100644 index 000000000000..222a33d0084f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi @@ -0,0 +1,1558 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2020 Toradex + */ + +#include <dt-bindings/pwm/pwm.h> +#include "fsl-imx8qm.dtsi" + +/ { + model = "Toradex Apalis iMX8QM"; + compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart1; + }; + + /* Apalis BKL1 */ + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ + }; + + /* Apalis WAKE1_MICO */ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + wakeup_key: wakeup-key { + label = "Wake-Up"; + gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + imx8qm-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_3v3_brd_scfw: PD_3V3LDO1 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_NONE>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_3v3_eth: PD_3V3ETH { + reg = <SC_R_BOARD_R0>; + #power-domain-cells = <0>; + power-domains = <&pd_3v3_brd_scfw>; + }; + + pd_3v3_ext_rgmii: PD_3V3EXTRGMII { + reg = <SC_R_BOARD_R1>; + #power-domain-cells = <0>; + power-domains = <&pd_3v3_brd_scfw>; + }; + + pd_1v8_ext_rgmii: PD_1V8EXTRGMII { + reg = <SC_R_BOARD_R2>; + #power-domain-cells = <0>; + power-domains = <&pd_3v3_brd_scfw>; + }; + }; + }; + + /* Power management bus used for powering down phy in suspend */ + pmbus_onmodule_phy { + compatible = "simple-pm-bus"; + power-domains = <&pd_3v3_eth>; + }; + + /* + * Power management bus used for powering external RGMII rail. + * use either <&pd_3v3_ext_rgmii> or <&pd_1v8_ext_rgmii>. + * those two power domains are mutually exclusive + */ + pmbus_external_rgmii: pmbusextrgmii { + compatible = "simple-pm-bus"; + power-domains = <&pd_1v8_ext_rgmii>; + }; + + pcie_sata_refclk: sata-clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_wifi_refclk: wifi-clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_sata_refclk_gate: sata-ref-clock { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; + #clock-cells = <0>; + clocks = <&pcie_sata_refclk>; + enable-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + }; + + pcie_wifi_refclk_gate: wifi-ref-clock { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; + #clock-cells = <0>; + clocks = <&pcie_wifi_refclk>; + enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_wifi: regulator-module-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pdn>; + regulator-name = "wifi_pwrdn_fake_regulator"; + regulator-settling-time-us = <100>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + enable-active-high; + gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100000>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + gpio-fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio8>; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + /* simple-audio-card,mclk-fs = <1>; */ + simple-audio-card,name = "apalis-imx8qm-sgtl5000"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + sound-dai = <&sgtl5000>; + }; + }; + + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + hdmi-out; + model = "imx-audio-hdmi-tx"; + protocol = <1>; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + amix-controller = <&amix>; + dais = <&sai6>, <&sai7>; + model = "amix-audio-sai"; + status = "okay"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + touchscreen: vf50-touchscreen { + compatible = "toradex,vf50-touchscreen"; + io-channels = <&adc1 2>,<&adc1 1>, + <&adc1 0>,<&adc1 3>; + xp-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + xm-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + yp-gpios = <&gpio2 17 GPIO_ACTIVE_LOW>; + ym-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "idle","default"; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; + pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; + vf50-ts-min-pressure = <200>; + status = "okay"; + }; + + lvds1_panel { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +&adc1 { + /* pinctrl handled by touchscreen above */ + vref-supply = <®_vref_1v8>; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; +}; + +/* Apalis GLAN */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 11 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + /* xceiver-supply = <®_can_stby>; */ +}; + +/* Apalis CAN2 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + /* xceiver-supply = <®_can_stby>; */ +}; + +&gpio2 { + /* + * Add GPIO2_20 as a wakeup source: + * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: 20 + */ + pad-wakeup = <101 5 20>; + pad-wakeup-num = <1>; +}; + +/* Apalis HDMI1 */ +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ctrl>; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + hdmi-ctrl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +}; + +/* On-module I2C */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + /* SGTL5000 */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + power-domains = <&pd_mclk_out0>; + reg = <0x0a>; + VDDA-supply = <®_module_3v3_avdd>; + VDDD-supply = <®_vref_1v8>; + VDDIO-supply = <®_module_3v3>; + }; + + /* USB3503A */ + usb3503@8 { + compatible = "smsc,usb3503a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + connect-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + intn-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + refclk-frequency = <25000000>; + reg = <0x08>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +/* Apalis I2C1 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio34>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>; + + apalis-imx8qm { + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + SC_P_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + /* Apalis AN1_ADC1 */ + SC_P_ADC_IN1_DMA_ADC0_IN1 0xc0000060 + /* Apalis AN1_ADC2 */ + SC_P_ADC_IN2_DMA_ADC0_IN2 0xc0000060 + /* Apalis AN1_TSWIP_ADC3 */ + SC_P_ADC_IN3_DMA_ADC0_IN3 0xc0000060 + >; + }; + + /* Apalis AN1_TS */ + pinctrl_adc1: adc1grp { + fsl,pins = < + /* Apalis AN1_TSPX */ + SC_P_ADC_IN4_DMA_ADC1_IN0 0xc0000060 + /* Apalis AN1_TSMX */ + SC_P_ADC_IN5_DMA_ADC1_IN1 0xc0000060 + /* Apalis AN1_TSPY */ + SC_P_ADC_IN6_DMA_ADC1_IN2 0xc0000060 + /* Apalis AN1_TSMY */ + SC_P_ADC_IN7_DMA_ADC1_IN3 0xc0000060 + >; + }; + + /* Apalis BKL_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021 + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_bkl: pwmbklgrp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + /* Apalis CAM1 */ + pinctrl_cam1_gpios: cam1gpiosgrp { + fsl,pins = < + /* Apalis CAM1_D7 */ + SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021 + /* Apalis CAM1_D6 */ + SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021 + /* Apalis CAM1_D5 */ + SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021 + /* Apalis CAM1_D4 */ + SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021 + /* Apalis CAM1_D3 */ + SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021 + /* Apalis CAM1_D2 */ + SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021 + /* Apalis CAM1_D1 */ + SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021 + /* Apalis CAM1_D0 */ + SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021 + /* Apalis CAM1_PCLK */ + SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021 + /* Apalis CAM1_MCLK */ + SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021 + /* Apalis CAM1_VSYNC */ + SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021 + /* Apalis CAM1_HSYNC */ + SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021 + >; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_MCLK */ + SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021 + /* Apalis DAP1_D_OUT */ + SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021 + /* Apalis DAP1_RESET */ + SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + /* Apalis DAP1_BIT_CLK */ + SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021 + /* Apalis DAP1_D_IN */ + SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021 + /* Apalis DAP1_SYNC */ + SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + /* On-module Wi-Fi_I2S_EN# */ + SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021 + >; + }; + + /* Apalis GPIO1+2 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = < + /* Apalis GPIO1 */ + SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021 + /* Apalis GPIO2 */ + SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021 + >; + }; + + /* Apalis GPIO3+4 */ + pinctrl_gpio34: gpio34grp { + fsl,pins = < + /* Apalis GPIO3 */ + SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021 + /* Apalis GPIO4 */ + SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021 + >; + }; + + /* Apalis GPIO5+6 */ + pinctrl_touch: touchgrp { + fsl,pins = < + SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021 + SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021 + >; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7 { + fsl,pins = < + SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 + >; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8 { + fsl,pins = < + SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021 + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020 + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020 + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020 + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020 + >; + }; + + /* Apalis LCD1_G1+2 */ + pinctrl_esai0_gpios: esai0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G1 */ + SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021 + /* Apalis LCD1_G2 */ + SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021 + >; + }; + + /* Apalis LCD1_G6+7 */ + pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G6 */ + SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021 + /* Apalis LCD1_G7 */ + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_fec2_gpios: fec2gpiosgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + /* Apalis LCD1_R1 */ + SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021 + /* Apalis LCD1_R0 */ + SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021 + /* Apalis LCD1_G0 */ + SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021 + /* Apalis LCD1_R7 */ + SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021 + /* Apalis LCD1_DE */ + SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021 + /* Apalis LCD1_HSYNC */ + SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021 + /* Apalis LCD1_VSYNC */ + SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021 + /* Apalis LCD1_PCLK */ + SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021 + /* Apalis LCD1_R6 */ + SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021 + /* Apalis LCD1_R5 */ + SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021 + /* Apalis LCD1_R4 */ + SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021 + /* Apalis LCD1_R3 */ + SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021 + /* Apalis LCD1_R2 */ + SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_qspi1a_gpios: qspi1agpiosgrp { + fsl,pins = < + /* Apalis LCD1_B0 */ + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + /* Apalis LCD1_B1 */ + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021 + /* Apalis LCD1_B2 */ + SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021 + /* Apalis LCD1_B3 */ + SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021 + /* Apalis LCD1_B5 */ + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + /* Apalis LCD1_B7 */ + SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021 + /* Apalis LCD1_B4 */ + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021 + /* Apalis LCD1_B6 */ + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_sim0_gpios: sim0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G5 */ + SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 + /* Apalis LCD1_G3 */ + SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021 + /* Apalis TS_5 */ + SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021 + /* Apalis LCD1_G4 */ + SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021 + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_mmc1_cd: mmc1cdgrp { + fsl,pins = < + SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + SC_P_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020 + >; + }; + + /* Apalis PWM2 */ + pinctrl_pwm3: pwm3grp { + fsl,pins = < + SC_P_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020 + >; + }; + + /* Apalis PWM3 */ + pinctrl_pwm0: pwm0grp { + fsl,pins = < + SC_P_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020 + >; + }; + + /* Apalis PWM4 */ + pinctrl_pwm1: pwm1grp { + fsl,pins = < + SC_P_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020 + >; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + >; + }; + + /* Apalis SD1_CD# */ + pinctrl_sd1_cd: sd1cdgrp { + fsl,pins = < + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + /* Apalis SD1 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_touchctrl_idle: touchctrl_idle { + fsl,pins = < + SC_P_ADC_IN4_LSIO_GPIO3_IO22 0x00000021 + SC_P_ADC_IN5_LSIO_GPIO3_IO23 0x00000021 + SC_P_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + SC_P_ADC_IN7_LSIO_GPIO3_IO25 0x00000021 + >; + }; + + pinctrl_touchctrl_gpios: touchctrl_gpios { + fsl,pins = < + SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021 + SC_P_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + SC_P_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021 + SC_P_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + /* Apalis SPDIF */ + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_LSIO_GPIO3_IO05 0x0600004c + >; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + SC_P_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + SC_P_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + SC_P_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + SC_P_SPI2_CS0_LSIO_GPIO3_IO10 0x0600004c + >; + }; + + /* Apalis TS_1 */ + pinctrl_mlb_gpios: mlbgpiosgrp { + fsl,pins = < + SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021 + >; + }; + + /* Apalis TS_2 */ + pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio { + fsl,pins = < + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021 + >; + }; + + /* Apalis TS_3 */ + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + /* Apalis TS_4 */ + pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021 + >; + }; + + /* Apalis TS_6 */ + pinctrl_usdhc1_gpios: usdhc1gpiosgrp { + fsl,pins = < + SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021 + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + /* Apalis UART1_ */ + pinctrl_lpuart1ctrl: lpuart1ctrlgrp { + fsl,pins = < + /* Apalis UART1_DTR */ + SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021 + /* Apalis UART1_DSR */ + SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021 + /* Apalis UART1_DCD */ + SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021 + /* Apalis UART1_RI */ + SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021 + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020 + SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020 + SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020 + SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020 + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021 + >; + }; + + /* Apalis USBO1 */ + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + /* Apalis USBO1_EN */ + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + /* Apalis USBO1_OC# */ + SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021 + >; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* On-module ETH_RESET# */ + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 + /* On-module ETH_INT# */ + SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000060 + >; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040 + SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040 + SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040 + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040 + SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040 + SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040 + SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040 + SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040 + SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040 + SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040 + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040 + SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040 + >; + }; + + /* On-module HDMI_CTRL */ + pinctrl_hdmi_ctrl: hdmictrlgrp { + fsl,pins = < + SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020 + >; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_TXD_AUD_SAI1_TXD 0xc600006c + SC_P_SAI1_RXD_AUD_SAI1_RXD 0xc600004c + SC_P_SAI1_TXC_AUD_SAI1_TXC 0xc600004c + SC_P_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c + >; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + /* On-module PCIe_CLK_EN1 */ + pinctrl_pcie_sata_refclk: pciesatarefclkgrp { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + /* On-module PCIe_CLK_EN2 */ + pinctrl_pcie_wifi_refclk: pciewifirefclkgrp { + fsl,pins = < + SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021 + >; + }; + + /* On-module PCIe_Wi-Fi */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021 + >; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: resetmocigrp { + fsl,pins = < + SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 + >; + }; + + /* On-module USB HSIC HUB */ + pinctrl_usb3503a: usb3503agrp { + fsl,pins = < + /* On-module HSIC_HUB_CONNECT */ + SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000041 + /* On-module HSIC_INT_N */ + SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021 + /* On-module HSIC_RESET_N */ + SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000041 + >; + }; + + /* On-module USB HSIC HUB (idle) */ + pinctrl_usb_hsic_idle: usbh1_1 { + fsl,pins = < + SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0xc60000c5 + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000c5 + >; + }; + + /* On-module USB HSIC HUB (active) */ + pinctrl_usb_hsic_active: usbh1_2 { + fsl,pins = < + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000d5 + >; + }; + + /* On-module Wi-Fi */ + pinctrl_wifi: wifigrp { + fsl,pins = < + /* On-module Wi-Fi_SUSCLK_32k */ + SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021 + /* On-module Wi-Fi_PCIE_W_DISABLE */ + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021 + >; + }; + + pinctrl_wifi_pdn: wifipdngrp { + fsl,pins = < + /* On-module Wi-Fi_POWER_DOWN */ + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021 + >; + }; + }; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + + spidev0: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis SPI2 */ +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + + spidev1: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis UART3 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART2 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +/* Apalis BKL1_PWM */ +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; + #pwm-cells = <3>; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + + mipi_csi1_ep: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +/* Apalis PCIE1 */ +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&pcie_sata_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi", "pcie_ext"; + ext_osc = <1>; + fsl,max-link-speed = <1>; + reset-gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_switch>; +}; + +/* On-module Wi-Fi */ +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&pcie_wifi_refclk_gate>; + /*clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>;*/ + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi", "pcie_ext"; + epdev_on-supply = <®_module_wifi>; + ext_osc = <1>; + fsl,max-link-speed = <1>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pd_cm40_intmux { + early_power_on; +}; + +&pd_cm41_intmux { + early_power_on; +}; + +&pd_dma_lpuart1 { + debug_console; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + #pwm-cells = <3>; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + #pwm-cells = <3>; +}; + +&rpmsg { + /* + * 64K for one rpmsg instance: + */ + reg = <0x0 0x90000000 0x0 0x20000>; + vdev-nums = <2>; +}; + +&rpmsg1 { + /* + * 64K for one rpmsg instance: + */ + reg = <0x0 0x90100000 0x0 0x20000>; + vdev-nums = <2>; +}; + +&sai1 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_1_MCLK>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,sai-asynchronous; +}; + +/* Apalis SATA1 */ +&sata { + clocks = <&clk IMX8QM_HSIO_SATA_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>, + <&pcie_sata_refclk_gate>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "phy_pclk0", "phy_pclk1", "phy_apbclk", "sata_ext"; + ext_osc = <1>; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsens 5>; + + trips { + pmic_alert0: trip0 { + hysteresis = <2000>; + temperature = <110000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + hysteresis = <2000>; + temperature = <125000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pmic_alert0>; + }; + + map1 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pmic_alert0>; + }; + }; + }; +}; + +&tsens { + tsens-num = <6>; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usb_hsic_idle>; + pinctrl-1 = <&pinctrl_usb_hsic_active>; + adp-disable; + disable-over-current; + hnp-disable; + srp-disable; +}; + +/* Apalis USBO1 */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + adp-disable; + ci-disable-lpm; + hnp-disable; + power-polarity-active-high; + srp-disable; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <8>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_mmc1_cd>; +}; + +/* Apalis SD1 */ +&usdhc3 { + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; +}; + +&vpu_decoder { + core_type = <2>; +}; + +&vpu_encoder { + core_type = <2>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi new file mode 100644 index 000000000000..01e2dbf4537d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2020 Toradex + */ + +#include "fsl-imx8qm-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM"; + compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; +}; + +/delete-node/ &pd_3v3_ext_rgmii; +/delete-node/ &pd_1v8_ext_rgmii; +/delete-node/ &pmbus_external_rgmii; +/delete-node/ &pcie_wifi_refclk; +/delete-node/ &pcie_wifi_refclk_gate; + +ðphy0 { + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +}; + +&gpio0 { + gpio-line-names = "MXM3_279", + "MXM3_277", + "MXM3_135", + "MXM3_203", + "MXM3_201", + "MXM3_275", + "MXM3_110", + "MXM3_120", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_124", + "MXM3_122", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "", + "", + "MXM3_4", + "MXM3_211", + "MXM3_209", + "MXM3_2", + "MXM3_136", + "MXM3_134", + "MXM3_6", + "MXM3_8", + "MXM3_112", + "MXM3_118", + "MXM3_114", + "MXM3_116"; +}; + +&gpio1 { + gpio-line-names = "", + "", + "", + "", + "MXM3_286", + "", + "MXM3_87", + "MXM3_99", + "MXM3_138", + "MXM3_140", + "MXM3_239", + "", + "MXM3_281", + "MXM3_283", + "MXM3_126", + "MXM3_132", + "", + "", + "", + "", + "MXM3_173", + "MXM3_175", + "MXM3_123"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "MXM3_198", + "MXM3_35", + "MXM3_164", + "", + "", + "", + "", + "MXM3_217", + "MXM3_215", + "", + "", + "MXM3_193", + "MXM3_194", + "MXM3_37", + "", + "MXM3_271", + "MXM3_273", + "MXM3_195", + "MXM3_197", + "MXM3_177", + "MXM3_179", + "MXM3_181", + "MXM3_183", + "MXM3_185", + "MXM3_187"; +}; + +&gpio3 { + gpio-line-names = "MXM3_191", + "", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_200", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_204", + "MXM3_196", + "", + "MXM3_202", + "", + "", + "", + "MXM3_305", + "MXM3_307", + "MXM3_309", + "MXM3_311", + "MXM3_315", + "MXM3_317", + "MXM3_319", + "MXM3_321", + "MXM3_15/GPIO7", + "MXM3_63", + "MXM3_17/GPIO8", + "MXM3_12", + "MXM3_14", + "MXM3_16"; +}; + +&gpio4 { + gpio-line-names = "MXM3_18", + "MXM3_11/GPIO5", + "MXM3_13/GPIO6", + "MXM3_274", + "MXM3_84", + "MXM3_262", + "MXM3_96", + "", + "", + "", + "", + "", + "MXM3_190", + "", + "", + "", + "MXM3_269", + "MXM3_251", + "MXM3_253", + "MXM3_295", + "MXM3_299", + "MXM3_301", + "MXM3_297", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_159", + "MXM3_184", + "MXM3_180", + "MXM3_186", + "MXM3_188", + "MXM3_176", + "MXM3_178"; +}; + +&gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_261", + "MXM3_263", + "MXM3_259", + "MXM3_257", + "MXM3_255", + "MXM3_128", + "MXM3_130", + "MXM3_265", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_243"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c0>; +}; + +&pinctrl_fec1 { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 1.8V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* On-module ETH_RESET# */ + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 + /* On-module ETH_INT# */ + SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000060 + >; +}; + +&pinctrl_fec1_sleep { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040 + SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040 + SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040 + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040 + SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040 + SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040 + SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040 + SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040 + SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040 + SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040 + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040 + SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040 + >; +}; + +&iomuxc { + apalis-imx8qm { + /* Apalis I2C2 (DDC) */ + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022 + >; + }; + }; +}; + +/* On-module PCIe_CTRL0_CLKREQ */ +&pinctrl_pcie_sata_refclk { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 + >; +}; + +&pcie_sata_refclk_gate { + enable-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; +}; + +/* On-module Wi-Fi */ +&pcieb{ + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&pcie_sata_refclk_gate>; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +};
\ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 952954294f95..71133435d2f6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1046,6 +1046,16 @@ #power-domain-cells = <0>; power-domains = <&pd_dma>; }; + pd_dma0_chan4: PD_LPSPI2_RX { + reg = <SC_R_DMA_0_CH4>; + power-domains =<&pd_dma>; + #power-domain-cells = <0>; + }; + pd_dma0_chan5: PD_LPSPI2_TX { + reg = <SC_R_DMA_0_CH5>; + power-domains =<&pd_dma>; + #power-domain-cells = <0>; + }; pd_dma_lpspi3: PD_DMA_SPI_3 { reg = <SC_R_SPI_3>; #power-domain-cells = <0>; @@ -2585,6 +2595,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2599,6 +2610,7 @@ adc1: adc@5a890000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a890000 0x0 0x10000>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2906,13 +2918,29 @@ <&clk IMX8QM_SPI0_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QM_SPI0_CLK>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <24000000>; power-domains = <&pd_dma_lpspi0>; dma-names = "tx","rx"; dmas = <&edma0 1 0 0>, <&edma0 0 0 1>; status = "disabled"; }; + lpspi2: lpspi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a020000 0x0 0x10000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI2_CLK>, + <&clk IMX8QM_SPI2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_SPI2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpspi2>; + dma-names = "tx","rx"; + dmas = <&edma0 5 0 0>, <&edma0 4 0 1>; + status = "disabled"; + }; + lpspi3: lpspi@5a030000 { compatible = "fsl,imx7ulp-spi"; reg = <0x0 0x5a030000 0x0 0x10000>; @@ -3062,6 +3090,8 @@ compatible = "fsl,imx8qm-edma"; reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */ + <0x0 0x5a240000 0x0 0x10000>, /* channel4 LPSPI2 rx */ + <0x0 0x5a250000 0x0 0x10000>, /* channel5 LPSPI2 tx */ <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */ <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ @@ -3075,9 +3105,11 @@ <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ #dma-cells = <3>; - dma-channels = <14>; + dma-channels = <16>; interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, @@ -3091,6 +3123,7 @@ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan4-rx", "edma0-chan5-tx", "edma0-chan6-rx", "edma0-chan7-tx", "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", @@ -3098,6 +3131,7 @@ "edma0-chan18-rx", "edma0-chan19-tx", "edma0-chan20-rx", "edma0-chan21-tx"; pdomains = <&pd_dma0_chan0>, <&pd_dma0_chan1>, /* lpspi0 */ + <&pd_dma0_chan4>, <&pd_dma0_chan5>, /* lpspi2 */ <&pd_dma0_chan6>, <&pd_dma0_chan7>, /* lpspi3 */ <&pd_dma0_chan12>, <&pd_dma0_chan13>, /* lpuart0 */ <&pd_dma0_chan14>, <&pd_dma0_chan15>, /* lpuart1 */ @@ -3348,12 +3382,14 @@ pwm0: pwm@5d000000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d000000 0 0x10000>; - clocks = <&clk IMX8QM_PWM0_HF_CLK>, + clocks = <&clk IMX8QM_PWM0_IPG_MSTR_CLK>, <&clk IMX8QM_PWM0_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>, + <&clk IMX8QM_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; status = "disabled"; }; @@ -3361,84 +3397,98 @@ pwm1: pwm@5d010000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d010000 0 0x10000>; - clocks = <&clk IMX8QM_PWM1_HF_CLK>, + clocks = <&clk IMX8QM_PWM1_IPG_MSTR_CLK>, <&clk IMX8QM_PWM1_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>, + <&clk IMX8QM_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; status = "disabled"; }; pwm2: pwm@5d020000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d020000 0 0x10000>; - clocks = <&clk IMX8QM_PWM2_HF_CLK>, + clocks = <&clk IMX8QM_PWM2_IPG_MSTR_CLK>, <&clk IMX8QM_PWM2_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>, + <&clk IMX8QM_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; status = "disabled"; }; pwm3: pwm@5d030000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d030000 0 0x10000>; - clocks = <&clk IMX8QM_PWM3_HF_CLK>, + clocks = <&clk IMX8QM_PWM3_IPG_MSTR_CLK>, <&clk IMX8QM_PWM3_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>, + <&clk IMX8QM_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; status = "disabled"; }; pwm4: pwm@5d040000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d040000 0 0x10000>; - clocks = <&clk IMX8QM_PWM4_HF_CLK>, + clocks = <&clk IMX8QM_PWM4_IPG_MSTR_CLK>, <&clk IMX8QM_PWM4_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>, + <&clk IMX8QM_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; status = "disabled"; }; pwm5: pwm@5d050000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d050000 0 0x10000>; - clocks = <&clk IMX8QM_PWM5_HF_CLK>, + clocks = <&clk IMX8QM_PWM5_IPG_MSTR_CLK>, <&clk IMX8QM_PWM5_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>, + <&clk IMX8QM_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; status = "disabled"; }; pwm6: pwm@5d060000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d060000 0 0x10000>; - clocks = <&clk IMX8QM_PWM6_HF_CLK>, + clocks = <&clk IMX8QM_PWM6_IPG_MSTR_CLK>, <&clk IMX8QM_PWM6_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>, + <&clk IMX8QM_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; status = "disabled"; }; pwm7: pwm@5d070000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d070000 0 0x10000>; - clocks = <&clk IMX8QM_PWM7_HF_CLK>, + clocks = <&clk IMX8QM_PWM7_IPG_MSTR_CLK>, <&clk IMX8QM_PWM7_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>, + <&clk IMX8QM_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; status = "disabled"; }; @@ -4093,6 +4143,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; @@ -4117,10 +4168,10 @@ "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic 0 73 4>, - <0 0 0 2 &gic 0 74 4>, - <0 0 0 3 &gic 0 75 4>, - <0 0 0 4 &gic 0 76 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_pcie0>; fsl,max-link-speed = <3>; hsio-cfg = <PCIEAX1PCIEBX1SATA>; @@ -4139,6 +4190,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; @@ -4164,10 +4216,10 @@ "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_pcie1>; fsl,max-link-speed = <3>; hsio-cfg = <PCIEAX1PCIEBX1SATA>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts index 13ecc444bca9..340f1949210c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts @@ -377,6 +377,7 @@ /delete-node/ &irqsteer_csi1; /delete-node/ &i2c0_mipi_csi1; /delete-node/ &lpspi0; +/delete-node/ &lpspi2; /delete-node/ &lpspi3; /delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts index a812b6a522ff..70513b347167 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts @@ -538,6 +538,7 @@ /delete-node/ &irqsteer_csi1; /delete-node/ &i2c0_mipi_csi1; /delete-node/ &lpspi0; +/delete-node/ &lpspi2; /delete-node/ &lpspi3; /delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts index cf43838cae35..416ef7acc768 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -719,6 +719,7 @@ /delete-node/ &irqsteer_csi1; /delete-node/ &i2c0_mipi_csi1; /delete-node/ &lpspi0; +/delete-node/ &lpspi2; /delete-node/ &lpspi3; /delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi index 5b11bb8337b8..e4fc23b09c49 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi @@ -443,6 +443,11 @@ dmas = <&edma0a 1 0 0>, <&edma0a 0 0 1>; }; +&lpspi2 { + interrupt-parent = <&gic>; + dmas = <&edma0d 5 0 0>, <&edma0d 4 0 1>; +}; + &lpspi3 { interrupt-parent = <&gic>; dmas = <&edma0d 7 0 0>, <&edma0d 6 0 1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dts new file mode 100644 index 000000000000..79bdbf73ff75 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-apalis.dtsi" +#include "fsl-imx8qxp-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QXP/DX on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8qxp-eval", "toradex,apalis-imx8qxp", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dtsi new file mode 100644 index 000000000000..96e35e54c26f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dtsi @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + display-subsystem { + status = "okay"; + }; + + /* Apalis WAKE1_MICO */ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbo1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBO1_EN */ + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-name = "usb_host_vbus_hub"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* Apalis AN1_ADC */ +&adc0 { + status = "okay"; +}; + +/* Apalis Parallel RGB */ +&adma_lcdif { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm_mipi_lvds1 0 6666667 PWM_POLARITY_INVERTED>; + status= "okay"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan3 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + status = "okay"; +}; + +&gpio1 { + /* + * Add GPIO1_26 as a wakeup source: + * Pin: SC_P_MIPI_DSI0_I2C0_SDA (MXM3_37) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: GPIO1_IO26 + */ + pad-wakeup = <117 5 26>; + pad-wakeup-num = <1>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0_mipi_lvds1 { + status = "okay"; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QXP_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio12>; + pwn-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3v3>; + AVDD-supply = <®_3v3>; + DVDD-supply = <®_3v3>; + PVDD-supply = <®_3v3>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + + /** + * Todo: The ADV7280 driver does not yet support this remote + * endpoint / port linking between the chain. + * + * port { + * adv7280_ep: endpoint { + * remote-endpoint = <¶llel_csi_ep>; + * }; + * }; + */ + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +&isi_0 { + interface = <2 0 2>; + /** + * interface = <Input MIPI_VCx Output> + * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI + * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + * Output: 0-DC0, 1-DC1, 2-MEM + */ + status = "okay"; +}; + +&isi_1 { + interface = <6 0 2>; + parallel_csi; + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&ldb1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; + + spidev0: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; + + spidev1: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart3 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "disabled"; +}; + +&mipi_dsi_phy1 { + status = "disabled"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /** + * Todo: The ADV7280 driver does not yet support this remote endpoint / + * port linking between the chain. + * + * port@1 { + * reg = <1>; + * + * parallel_csi_ep: endpoint { + * data-lanes = <1 2>; + * remote-endpoint = <¶llel_csi_ep>; + * }; + * }; + */ +}; + +/* On-module GPIO Expander */ +&pcal6416_1 { + /* + * This gpio-hog drives a muxing device. With that we can choose + * if LVDS1_B pins are active or if DVI signals are active. Those + * signals are then muxed to MIPI_DSI1 PADs. + * + * output-high; muxes to DVI signals + * output-low; muxes to LVDS1_B signals + */ + LVDS_HDMI_MUX { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "LVDS_HDMI_MUX"; + }; +}; + +/* Apalis PCIE1 */ +&pcieb { + status = "okay"; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +/* Apalis BKL1_PWM */ +&pwm_mipi_lvds1 { + status = "okay"; +}; + +/* Apalis PWM1 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2 */ +&pwm_mipi_lvds0 { + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + vbus-regulator = <®_usb_host_vbus>; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis.dtsi new file mode 100644 index 000000000000..404e77779bdc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis.dtsi @@ -0,0 +1,1230 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/gpio/gpio.h> +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Toradex Apalis iMX8QXP/DX Module"; + compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart1; + }; + + panel_1: panel-1 { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + * logictechno,lt161010-2nhc: Cap. Touch Display 7" Parallel + * logictechno,lt161010-2nhr: Res. Touch Display 7" Parallel + * logictechno,lt170410-2whc: Cap. Touch Display 10.1" LVDS + * tpk,f07a-0102: Capacitive Multi-Touch Display Fusion 7" + * tpk,f10a-0102: Capacitive Multi-Touch Display Fusion 10" + */ + compatible = "panel-dpi"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "bgr666"; + + panel-timing { + /* Default VESA VGA display timings */ + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + pixelclk-active = <0>; + }; + + port { + lcd_panel1_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel_2: panel-2 { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight>; + + port { + lcd_panel2_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + enable-active-high; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx8qxp-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + }; + }; +}; + +/* Apalis AN1_ADC */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +/* Apalis Parallel RGB */ +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + bus-width = <18>; + status = "disabled"; + + port@0 { + lcd_display_out: lcdif-endpoint { + remote-endpoint = <&lcd_panel1_in>; + }; + }; +}; + +&gpio0 { + gpio-line-names = "", + "MXM3_293", + "MXM3_295", + "MXM3_297", + "MXM3_299", + "MXM3_301", + "MXM3_273", + "MXM3_275", + "MXM3_277", + "MXM3_279", + "MXM3_281", + "MXM3_283", + "MXM3_255", + "MXM3_257", + "MXM3_259", + "MXM3_261", + "MXM3_247", + "", + "", + "MXM3_245", + "MXM3_243", + "MXM3_112", + "MXM3_118", + "", + "MXM3_265", + "MXM3_196", + "MXM3_200", + "MXM3_202", + "MXM3_204", + "MXM3_310", + "MXM3_312", + "MXM3_318"; +}; + +&gpio1 { + gpio-line-names = "MXM3_235", + "MXM3_233", + "MXM3_231", + "MXM3_229", + "MXM3_221", + "MXM3_223", + "MXM3_225", + "MXM3_316", + "MXM3_227", + "MXM3_307", + "MXM3_305", + "MXM3_194", + "", + "MXM3_311", + "MXM3_309", + "MXM3_128", + "MXM3_130", + "MXM3_12", + "MXM3_14", + "MXM3_16", + "MXM3_18", + "MXM3_132", + "MXM3_126", + "MXM3_134", + "MXM3_136", + "MXM3_35", + "MXM3_37", + "MXM3_4", + "MXM3_6", + "MXM3_207", + "MXM3_205", + "MXM3_239"; +}; + +&gpio2 { + gpio-line-names = "MXM3_8", + "", + "", + "MXM3_140"; +}; + +&gpio3 { + gpio-line-names = "MXM3_191", + "MXM3_193", + "MXM3_203", + "MXM3_201", + "", + "", + "", + "", + "", + "MXM3_96", + "MXM3_110", + "MXM3_114", + "MXM3_116", + "MXM3_286", + "MXM3_158", + "MXM3_198", + "MXM3_274", + "MXM3_11", + "MXM3_13", + "MXM3_15", + "MXM3_17", + "MXM3_1", + "MXM3_3", + "MXM3_5", + "MXM3_7"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "MXM3_211", + "MXM3_84", + "MXM3_262", + "MXM3_209", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_152", + "MXM3_148", + "MXM3_156", + "MXM3_164", + "MXM3_154", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_77", + "MXM3_79", + "MXM3_65"; +}; + +&gpio5 { + gpio-line-names = "MXM3_67", + "MXM3_71", + "MXM3_73", + "MXM3_113", + "MXM3_115", + "MXM3_119", + "MXM3_121", + "MXM3_125", + "MXM3_127", + "MXM3_131", + "MXM3_59", + "MXM3_61"; +}; + +/* Apalis Gigabit Ethernet */ +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + reg = <4>; + micrel,led-mode = <0>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Apalis CAN2 */ +&flexcan3 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + /* SGTL5000 Audio Codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, + <12000000>, <12000000>; + power-domains = <&pd_mclk_out0>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_vref_1v8>; + }; + + /* PCAL6416A GPIO Expander */ + pcal6416_1: gpio@20 { + compatible = "nxp,pcal6416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_exp1_int>; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_module_3v3>; + ngpios = <16>; + gpio-line-names = "HDMI1_CEC", "SPDIF1_IN", "SPDIF1_OUT", + "UART4_TXD", "UART1_DCD", "UART1_RI", "UART1_DSR", + "UART1_DTR", "PWM1", "Wi-Fi_WKUP_WLAN", + "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_BT", "Wi-Fi_PDn", + "Wi-Fi_WKUP_HOST", "DSI_SW_SEL", "HDMI1_HPD"; + }; + + /* PCAL6416A GPIO Expander */ + pcal6416_2: gpio@21 { + compatible = "nxp,pcal6416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_exp2_int>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_module_3v3>; + }; + + /* Touch controller */ + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + /* LT8912B DSI to HDMI converter */ + lt8912@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c0_mipi_lvds1>; + hpd-gpios = <&pcal6416_1 15 GPIO_ACTIVE_HIGH>; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_out>; + }; + }; + }; + + /* On-Module EEPROM */ + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Apalis I2C1 */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + clock-frequency = <100000>; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio3>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "disabled"; + }; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + clock-frequency = <100000>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio34>, <&pinctrl_usbo1oc>, <&pinctrl_gpio8>, + <&pinctrl_qspi0a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_mmc1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_wifi_sclk>; + + apalis-imx8qxp { + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 /* MXM3 305 */ + /* Apalis AN1_ADC1 */ + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 /* MXM3 307 */ + /* Apalis AN1_ADC2 */ + SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 /* MXM3 309 */ + /* Apalis AN1_TSWIP_ADC3 */ + SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 /* MXM3 311 */ + >; + }; + + /* Apalis BKL1_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x21 /* MXM3 286 */ + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_mipi_lvds1: pwmmipilvds1grp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x60 /* MXM3 239 */ + >; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* MXM3 14 */ + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* MXM3 12 */ + >; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* MXM3 18 */ + SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* MXM3 16 */ + >; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_D_OUT */ + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x21 /* MXM3 196 */ + /* Apalis DAP1_RESET */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x21 /* MXM3 198 */ + /* Apalis DAP1_BIT_CLK */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x21 /* MXM3 200 */ + /* Apalis DAP1_D_IN */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x21 /* MXM3 202 */ + /* Apalis DAP1_SYNC */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x21 /* MXM3 204 */ + >; + }; + + /* Apalis GPIO1+2 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = < + /* Apalis GPIO 1 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x21 /* MXM3 1 */ + /* Apalis GPIO 2 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x21 /* MXM3 3 */ + >; + }; + + /* Apalis GPIO3+4 */ + pinctrl_gpio34: gpio34grp { + fsl,pins = < + /* Apalis GPIO 3 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x21 /* MXM3 5 */ + /* Apalis GPIO 4 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* MXM3 7 */ + >; + }; + + /* Apalis GPIO5+6 */ + pinctrl_touch: touchgrp { + fsl,pins = < + /* Apalis GPIO 5 */ + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x21 /* MXM3 11 */ + /* Apalis GPIO 6 */ + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x21 /* MXM3 13 */ + >; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7 { + fsl,pins = < + /* Apalis GPIO 7 */ + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x21 /* MXM3 15 */ + >; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8 { + fsl,pins = < + /* Apalis GPIO 8 */ + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x21 /* MXM3 17 */ + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000021 /* MXM3 211 */ + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 /* MXM3 209 */ + >; + }; + + /* Apalis I2C2 (DDC) */ + pinctrl_i2c0_mipi_lvds1: mipilvds1i2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* MXM3 205 */ + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* MXM3 207 */ + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_CSI_EN_ADMA_I2C3_SCL 0xc6000020 /* MXM3 203 */ + SC_P_CSI_RESET_ADMA_I2C3_SDA 0xc6000020 /* MXM3 201 */ + >; + }; + + /* Apalis MMC1_ */ + pinctrl_mmc1_gpios: mmc1gpiosgrp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x21 /* MXM3 148 */ + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x21 /* MXM3 158 */ + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x21 /* MXM3 156 */ + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x21 /* MXM3 152 */ + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_usdhc2_gpio: mmc1gpiogrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* MXM3 164 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* MXM3 164 */ + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* MXM3 154 */ + SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* MXM3 150 */ + SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* MXM3 160 */ + SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* MXM3 162 */ + SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* MXM3 144 */ + SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* Apalis Parallel Camera */ + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 /* MXM3 187 */ + SC_P_CSI_D01_CI_PI_D03 0xC0000041 /* MXM3 185 */ + SC_P_CSI_D02_CI_PI_D04 0xC0000041 /* MXM3 183 */ + SC_P_CSI_D03_CI_PI_D05 0xC0000041 /* MXM3 181 */ + SC_P_CSI_D04_CI_PI_D06 0xC0000041 /* MXM3 179 */ + SC_P_CSI_D05_CI_PI_D07 0xC0000041 /* MXM3 177 */ + SC_P_CSI_D06_CI_PI_D08 0xC0000041 /* MXM3 175 */ + SC_P_CSI_D07_CI_PI_D09 0xC0000041 /* MXM3 173 */ + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 /* MXM3 193 */ + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 /* MXM3 191 */ + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 /* MXM3 197 */ + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 /* MXM3 195 */ + >; + }; + + /* Apalis Parallel RGB LCD Interface */ + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* MXM3 243 */ + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* MXM3 245 */ + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* MXM3 247 */ + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* MXM3 249 */ + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* MXM3 255 */ + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* MXM3 257 */ + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* MXM3 259 */ + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* MXM3 261 */ + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* MXM3 263 */ + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* MXM3 265 */ + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* MXM3 273 */ + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* MXM3 275 */ + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* MXM3 277 */ + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* MXM3 279 */ + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* MXM3 281 */ + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* MXM3 283 */ + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* MXM3 291 */ + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* MXM3 293 */ + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* MXM3 295 */ + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* MXM3 297 */ + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* MXM3 299 */ + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* MXM3 301 */ + >; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* MXM3 2 */ + >; + }; + + /* Apalis PWM2 */ + pinctrl_pwm_mipi_lvds0: pwmmipilvds0grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x60 /* MXM3 4 */ + >; + }; + + /* Apalis PWM_ */ + pinctrl_pwm_gpios: gpiospwmgrp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x21 /* MXM3 6 */ + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x21 /* MXM3 8 */ + >; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0x21 /* MXM3 35 */ + >; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO1_IO08 0x06000040 /* MXM3 227 */ + SC_P_SPI0_SDI_ADMA_SPI0_SDI 0x06000040 /* MXM3 223 */ + SC_P_SPI0_SDO_ADMA_SPI0_SDO 0x06000040 /* MXM3 225 */ + SC_P_SPI0_SCK_ADMA_SPI0_SCK 0x06000040 /* MXM3 221 */ + >; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* MXM3 233 */ + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* MXM3 229 */ + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* MXM3 231 */ + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* MXM3 235 */ + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* MXM3 118 */ + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* MXM3 112 */ + >; + }; + + /* Apalis UART1_ */ + pinctrl_qspi0a_gpios: qspi0agpiosgrp { + fsl,pins = < + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x21 /* MXM3 114 */ + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x21 /* MXM3 116 */ + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 /* MXM3 126 */ + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 /* MXM3 132 */ + SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* MXM3 128 */ + SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* MXM3 130 */ + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 /* MXM3 134 */ + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 /* MXM3 136 */ + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_SCU_GPIO0_01_ADMA_UART3_TX 0x06000020 /* MXM3 138 */ + SC_P_SCU_GPIO0_00_ADMA_UART3_RX 0x06000020 /* MXM3 140 */ + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x21 /* MXM3 84 */ + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x04000020 /* MXM3 96 */ + >; + }; + + /* Apalis USBO1_EN */ + pinctrl_usbo1_en: usbo1en { + fsl,pins = < + /* Apalis USBO1_EN */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x21 /* MXM3 274 */ + >; + }; + + /* Apalis USBO1 */ + pinctrl_usbo1oc: usbo1oc { + fsl,pins = < + /* Apalis USBO1_OC# */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x04000020 /* MXM3 262 */ + >; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0x06680021 /* MXM3 37 */ + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 + /* On-module ETH_RESET# */ + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x21 + /* On-module ETH_INT# */ + SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 + >; + }; + + /* On-module GPIO expanders */ + pinctrl_i2c_exp1_int: i2cexp1int { + fsl,pins = < + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x21 + >; + }; + + pinctrl_i2c_exp2_int: i2cexp2int { + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x21 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c0: i2c0csi0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0xc6000020 /* MXM3 140 */ + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0xc6000020 /* MXM3 142 */ + >; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + SC_P_SPI0_CS1_ADMA_SAI1_TXD 0x06000040 + SC_P_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + SC_P_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + >; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: gpioresetmocigrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x11 + >; + }; + + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879-int { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 + >; + }; + + pinctrl_wifi_sclk: wifigrp { + fsl,pins = < + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 /* WiFi Sleep clock */ + >; + }; + }; +}; + +&ldb1 { + lvds-channel@0 { + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&lcd_panel2_in>; + }; + }; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +}; + +/* Apalis SPI2 */ +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART2 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART3 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART4 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; +}; + +&mipi_dsi1 { + pwr-delay = <10>; +}; + +&mipi_dsi2 { + pwr-delay = <10>; +}; + +&mipi_dsi_bridge2 { + port@1 { + mipi_dsi_bridge2_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; + +/* Apalis PCIE1 */ +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + bus-range = <0x00 0xff>; + ext_osc = <0>; + fsl,max-link-speed = <2>; + reset-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_switch>; +}; + +/* Apalis console */ +&pd_dma_lpuart1 { + debug_console; +}; + +/* Apalis BKL1_PWM */ +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +/* Apalis PWM2 */ +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +/* On-module I2S */ +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + + trips { + pmic_alert0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* Manage on-module USB WiFi */ +&usbphynop1 { + status = "okay"; + reset-on-resume; +}; + +/* + * Apalis USB 3.0 Host. Serves USB 3.0 4-port hub on module and + * USB 3.0 ports on-board + */ +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + core_type = <1>; +}; + +&vpu_encoder { + core_type = <1>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-aster.dts new file mode 100644 index 000000000000..71141ec066d9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-aster.dts @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on Aster Board"; + compatible = "toradex,colibri_imx8qxp-aster", \ + "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + display-subsystem { + status = "okay"; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + regulators { + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +/* Colibri I2C */ +&i2c1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog2>; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +/* Colibri SPI */ +&lpspi2 { + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* Colibri PWM_A */ +&pwm_adma_lcdif { + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&pwm2 { + status = "okay"; +}; + +/* + * Lower USB port, shared with micro-usb-connector + * The micro-usb connector may only be used in USB client mode. + */ +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +/* Upper USB port */ +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts new file mode 100644 index 000000000000..eccec4ba19a9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with LT8912 MIPI-DSI 2 HDMI bridge"; + compatible = "toradex,colibri-imx8qxp-dsihdmi-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + status = "disabled"; +}; + +&backlight { + status = "disabled"; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + status = "okay"; + + /* DSI to HDMI Adapter V1.1A */ + i2c-switch@70 { + compatible = "nxp,pca9540"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c_sw0: i2c-sw@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* DDC/EDID */ + }; + + i2c-sw@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + lt8912@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c_sw0>; + hpd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hpd>; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + /* DSI/LVDS Hot Plug Detect on FFC (X2) */ + pinctrl_gpio_hpd: gpio-hpd { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20 /* SODIMM 138 */ + >; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "disabled"; + }; +}; + +&ldb2 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts new file mode 100644 index 000000000000..bb565ab6ea76 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx8qxp-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..867de348041f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + /* fixed crystal dedicated to mpc25xx */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + display-subsystem { + status = "okay"; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + regulators { + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio3 { + /* + * Add GPIO3_10 as a wakeup source: + * Pin: SC_P_QSPI0A_DATA1 (SODIMM_45) + * Type: SC_PAD_WAKEUP_RISE_EDGE + * Line: GPIO3_IO10 + */ + pad-wakeup = <157 6 10>; + pad-wakeup-num = <1>; + }; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* Colibri SPI */ +&lpspi2 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "disabled"; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* Colibri PWM_A */ +&pwm_adma_lcdif { + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&pwm2 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts new file mode 100644 index 000000000000..71a1654a1163 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with dual channel lvds"; + compatible = "toradex,colibri-imx8qxp-lvds-dual-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + lvds1_panel { + compatible = "lg,lp156wf1"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + status = "disabled"; +}; + +&backlight { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bklght_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; /* Ext.Conn 25: LVDS1_GPIO0_00 */ + pwms = <&pwm_adma_lcdif 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */ + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* On-module MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts new file mode 100644 index 000000000000..5a5ed0f3f441 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with single channel lvds"; + compatible = "toradex,colibri-imx8qxp-lvds-single-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + lvds1_panel { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + status = "disabled"; +}; + +/* + * Atmel maxtouch controller + * To enable it, you should disable pwm0 (PWM_B) and pwm1 (PWM_C) + */ +&atmel_mxt_ts { + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio0>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ + reset-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + status = "okay"; +}; + +&backlight { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bklght_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; /* Ext.Conn 25: LVDS1_GPIO0_00 */ + pwms = <&pwm_adma_lcdif 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_touch: touchgrp { + fsl,pins = < + SC_P_UART1_TX_LSIO_GPIO0_IO21 0x06000040 /* SODIMM 28 */ + SC_P_UART1_RX_LSIO_GPIO0_IO22 0x06000020 /* SODIMM 30 */ + >; + }; + + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */ + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* On-module MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi new file mode 100644 index 000000000000..ed5293f23b52 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi @@ -0,0 +1,1300 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX Module"; + compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; + stdout-path = &lpuart3; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + enable-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "disabled"; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + * logictechno,lt161010-2nhc: Cap. Touch Display 7" Parallel + * logictechno,lt161010-2nhr: Res. Touch Display 7" Parallel + * logictechno,lt170410-2whc: Cap. Touch Display 10.1" LVDS + * tpk,f07a-0102: Capacitive Multi-Touch Display Fusion 7" + * tpk,f10a-0102: Capacitive Multi-Touch Display Fusion 10" + */ + compatible = "panel-dpi"; + backlight = <&backlight>; + enable-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "bgr666"; + + panel-timing { + /* Default VESA VGA display timings */ + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + pixelclk-active = <0>; + }; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdd_3v3_vga: regulator-vga-avcc { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVCC_VGA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx8qxp-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + /*simple-audio-card,mclk-fs = <1>;*/ + + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + }; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + bus-width = <18>; + status = "okay"; + + port@0 { + lcd_display_out: lcdif-endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm_adma_lcdif 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, + <&clk IMX8QXP_ENET0_AHB_CLK>, + <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, + <&clk IMX8QXP_ENET0_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +/* Colibri optional CAN on UART_B RTS/CTS */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on PS2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on UART_A TXD/RXD */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_module_3v3>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = "", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_68", + "", + "", + "SODIMM_82", + "SODIMM_56", + "SODIMM_28", + "SODIMM_30", + "", + "SODIMM_61", + "SODIMM_103", + "", + "", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_100"; +}; + +&gpio1 { + gpio-line-names = "SODIMM_86", + "SODIMM_92", + "SODIMM_90", + "SODIMM_88", + "", + "", + "", + "SODIMM_59", + "", + "SODIMM_6", + "SODIMM_8", + "", + "", + "SODIMM_2", + "SODIMM_4", + "SODIMM_34", + "SODIMM_32", + "SODIMM_63", + "SODIMM_55", + "SODIMM_33", + "SODIMM_35", + "SODIMM_36", + "SODIMM_38", + "SODIMM_21", + "SODIMM_19", + "SODIMM_140", + "SODIMM_142", + "SODIMM_196", + "SODIMM_194", + "SODIMM_186", + "SODIMM_188", + "SODIMM_138"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_23", + "", + "", + "SODIMM_144"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_96", + "SODIMM_75", + "SODIMM_37", + "SODIMM_29", + "", + "", + "", + "", + "", + "SODIMM_43", + "SODIMM_45", + "SODIMM_69", + "SODIMM_71", + "SODIMM_73", + "SODIMM_77", + "SODIMM_89", + "SODIMM_93", + "SODIMM_95", + "SODIMM_99", + "SODIMM_105", + "SODIMM_107", + "SODIMM_98", + "SODIMM_102", + "SODIMM_104", + "SODIMM_106"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "SODIMM_129", + "SODIMM_133", + "SODIMM_127", + "SODIMM_131", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_44", + "", + "SODIMM_76", + "SODIMM_31", + "SODIMM_47", + "SODIMM_190", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio5 { + gpio-line-names = "", + "SODIMM_57", + "SODIMM_65", + "SODIMM_85", + "", + "", + "", + "", + "SODIMM_135", + "SODIMM_137", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184"; +}; + + +&gpu_3d0 { + status = "okay"; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; + status = "okay"; + + /* + * IMX8QXP_AUD_MCLKOUT0 is used by both the usb3803 and sgtl5000 + * So do the pinmuxing and setup for both here + */ + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + + /* USB3503A */ + usb3803@08 { + compatible = "smsc,usb3803"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + reg = <0x08>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "refclk"; + power-domains = <&pd_mclk_out0>; + bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; + intn-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; + disabled-ports = <2>; + initial-mode = <1>; + non-removable-devices = <1>; + }; + + /* SGTL5000 */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + power-domains = <&pd_mclk_out0>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_vref_1v8>; + }; + + /* GPIO expander */ + gpio_expander_43: gpio-expander@43 { + compatible = "fcs,fxl6408"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x43>; + inital_io_dir = <0xff>; + inital_output = <0x05>; + }; + + /* Touch controller */ + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +/* MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; +}; + +/* On-module MIPI CSI I2C accessible on FFC (X3) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QXP_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_ctl>; + pwn-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +/* Colibri I2C */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + reg = <0x4a>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>, + <&pinctrl_ext_io0>, <&pinctrl_mxt_ts>; + + colibri-imx8qxp { + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879-int { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 + >; + }; + + /* Colibri Analogue Inputs */ + pinctrl_adc0: adc0grp { + fsl,pins = < + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ + SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ + SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ + >; + }; + + pinctrl_can_int: can-int-grp { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ + >; + }; + + pinctrl_csi_ctl: csictlgrp { + fsl,pins = < + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ + >; + }; + + /* Colibri UART_B */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ + SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ + SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ + >; + }; + + /* Colibri UART_C */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ + >; + }; + + /* Colibri UART_A */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ + >; + }; + + /* Colibri UART_A Control */ + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ + SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ + SC_P_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ + >; + }; + + /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 + >; + }; + + pinctrl_fec1_sleep: fec1-sleep-grp { + fsl,pins = < + SC_P_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 + SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 + SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 + SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 + SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 + SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 + SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 + >; + }; + + /* Colibri LCD Back-Light GPIO */ + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ + SC_P_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + SC_P_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ + SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + SC_P_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + SC_P_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + SC_P_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + SC_P_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ + >; + }; + + pinctrl_hog2: hog2grp { + fsl,pins = < + SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ + >; + }; + + /* + * This pin is used in the SCFW as a UART. Using it from + * Linux would require rewritting the SCFW board file. + */ + pinctrl_hog_scfw: hogscfwgrp { + fsl,pins = < + SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ + >; + }; + + /* On Module I2C */ + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + >; + }; + + /* Colibri I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ + >; + }; + + /* Colibri optional CAN on UART_B RTS/CTS */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ + >; + }; + + /* Colibri optional CAN on PS2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ + >; + }; + + /* Colibri optional CAN on UART_A TXD/RXD */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ + SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ + >; + }; + + /* On module wifi module */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ + >; + }; + + /* Colibri PWM_A */ + pinctrl_pwm_a: pwma { + /* both pins are connected together, reserve the unused CSI_D05 */ + fsl,pins = < + SC_P_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ + SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ + >; + }; + + /* Colibri PWM_B */ + pinctrl_pwm_b: pwmb { + fsl,pins = < + SC_P_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ + >; + }; + + /* Colibri PWM_C */ + pinctrl_pwm_c: pwmc { + fsl,pins = < + SC_P_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ + >; + }; + + /* Colibri PWM_D */ + pinctrl_pwm_d: pwmd { + /* both pins are connected together, reserve the unused CSI_D04 */ + fsl,pins = < + SC_P_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ + SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ + >; + }; + + /* On-module I2S */ + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + SC_P_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + SC_P_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + SC_P_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + /* Colibri Audio Analogue Microphone GND */ + pinctrl_sgtl5000: sgtl5000 { + fsl,pins = < + /* MIC GND EN */ + SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 + >; + }; + + /* On-module SGTL5000 clock */ + pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { + fsl,pins = < + SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module USB interrupt */ + pinctrl_usb3503a: usb3503a-grp { + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 + >; + }; + + /* Colibri USB Client Cable Detect */ + pinctrl_usbc_det: usbc-det { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ + >; + }; + + pinctrl_ext_io0: ext-io0 { + fsl,pins = < + SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ + >; + }; + + /* Colibri Parallel RGB LCD Interface */ + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ + >; + }; + + /* USB Host Power Enable */ + pinctrl_usbh1_reg: usbh1-reg { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Colibri SDCard CardDetect */ + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ + >; + }; + + /* Colibri SDCard */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ + SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ + >; + }; + + /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ + >; + }; + + /* Colibri SPI */ + pinctrl_lpspi2: lpspi2 { + fsl,pins = < + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ + >; + }; + }; +}; + +&isi_0 { + interface = <2 0 2>; + /** + * interface = <Input MIPI_VCx Output> + * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI + * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + * Output: 0-DC0, 1-DC1, 2-MEM + */ + status = "okay"; +}; + +&isi_1 { + interface = <6 0 2>; + parallel_csi; + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +/* Colibri SPI */ +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +}; + +/* Colibri UART_B */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Colibri UART_C */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Colibri UART_A */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; +}; + +/* MIPI CSI accessible via FFC (X3) */ +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&mipi_dsi1 { + pwr-delay = <10>; +}; + +&mipi_dsi2 { + pwr-delay = <10>; +}; + +/* On-module PCIe for wifi */ +&pcieb{ +/* + * WARNING! Enabling "epdev_on-supply" leads a crash of pcie driver on + * system suspend. + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + ext_osc = <1>; + clkreq-gpio = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; + disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + fsl,max-link-speed = <1>; + status = "okay"; +}; + +&pd_dma_lpuart3 { + debug_console; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +/* Colibri PWM_A */ +&pwm_adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_a>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_B */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_b>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_C */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_c>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_D */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_d>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +/* On-module I2S */ +&sai0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + + trips { + pmic_alert0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + disable-wp; + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + core_type = <1>; +}; + +&vpu_encoder { + core_type = <1>; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 3aee6123d161..6887cc1a743d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -118,6 +118,7 @@ reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; clocks = <&pmic>; clock-names = "ext_clock"; + post-power-on-delay-ms = <10>; power-off-delay-us = <10>; }; diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 860c8fb10795..4bde7b6f2b11 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -168,14 +168,14 @@ clock-names = "apb_pclk"; status="disabled"; }; - spi0: ssp@fe800000 { + spi0: spi@fe800000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xfe800000 0x1000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; - spi1: ssp@fe900000 { + spi1: spi@fe900000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xfe900000 0x1000>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 1887af654a7d..16ced1ff1ad3 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -168,14 +168,14 @@ clock-names = "apb_pclk"; status="disabled"; }; - spi0: ssp@fe800000 { + spi0: spi@fe800000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xfe800000 0x1000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; - spi1: ssp@fe900000 { + spi1: spi@fe900000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xfe900000 0x1000>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 8c0cf7efac65..b554cdaf5e53 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -134,7 +134,7 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; + reg = <0x12000 0x200>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 30d48ecf46e0..27d2bd85d1ae 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -65,6 +65,23 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * This area matches the mapping done with a + * mainline U-Boot, and should be updated by the + * bootloader. + */ + + psci-area@4000000 { + reg = <0x0 0x4000000 0x0 0x200000>; + no-map; + }; + }; + ap806 { #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index d10d4430537a..be91873c0878 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -282,6 +282,7 @@ status = "okay"; bus-width = <8>; non-removable; + vqmmc-supply = <&vdd_1v8>; }; clocks { @@ -307,7 +308,8 @@ regulator-max-microvolt = <1320000>; enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <1000>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index d67ef4319f3b..97f31bc4fa1e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1584,7 +1584,7 @@ regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&exp1 12 GPIO_ACTIVE_LOW>; + gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_5v0_sys>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 9bdf19f2cca7..466199766848 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1103,7 +1103,7 @@ compatible = "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x702f9000 0x2000>, + reg = <0x702f9000 0x1000>, <0x702fa000 0x2000>; interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&tegra_car TEGRA210_CLK_APE>; diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index b6b44fdf7fac..c1028b47edde 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -458,6 +458,8 @@ l11 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <3337000>; + regulator-allow-set-load; + regulator-system-load = <200000>; }; l12 { diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 789f3e87321e..7a510505e0c2 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -262,6 +262,8 @@ l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; }; l22 { regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ab00be277c6f..6f372ec055dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -359,7 +359,7 @@ }; intc: interrupt-controller@9bc0000 { - compatible = "arm,gic-v3"; + compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 369092e17e34..016b84552a62 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -937,6 +937,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 28257724a56e..3f8f528099a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -77,17 +77,18 @@ pinctrl-0 = <&usb30_host_drv>; regulator-name = "vcc_host_5v"; regulator-always-on; + regulator-boot-on; vin-supply = <&vcc_sys>; }; vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb20_host_drv>; regulator-name = "vcc_host1_5v"; regulator-always-on; + regulator-boot-on; vin-supply = <&vcc_sys>; }; @@ -275,7 +276,7 @@ usb2 { usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index efac2202b16e..c34daae3c37c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -685,6 +685,7 @@ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; @@ -696,6 +697,7 @@ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; @@ -707,6 +709,7 @@ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; @@ -1333,11 +1336,11 @@ sdmmc0 { sdmmc0_clk: sdmmc0-clk { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; }; sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; }; sdmmc0_dectn: sdmmc0-dectn { @@ -1349,14 +1352,14 @@ }; sdmmc0_bus1: sdmmc0-bus1 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; }; sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>, - <1 RK_PA1 1 &pcfg_pull_up_4ma>, - <1 RK_PA2 1 &pcfg_pull_up_4ma>, - <1 RK_PA3 1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, + <1 RK_PA1 1 &pcfg_pull_up_8ma>, + <1 RK_PA2 1 &pcfg_pull_up_8ma>, + <1 RK_PA3 1 &pcfg_pull_up_8ma>; }; sdmmc0_gpio: sdmmc0-gpio { @@ -1530,50 +1533,50 @@ rgmiim1_pins: rgmiim1-pins { rockchip,pins = /* mac_txclk */ - <1 RK_PB4 2 &pcfg_pull_none_12ma>, + <1 RK_PB4 2 &pcfg_pull_none_8ma>, /* mac_rxclk */ - <1 RK_PB5 2 &pcfg_pull_none_2ma>, + <1 RK_PB5 2 &pcfg_pull_none_4ma>, /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_2ma>, + <1 RK_PC3 2 &pcfg_pull_none_4ma>, /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_12ma>, + <1 RK_PD1 2 &pcfg_pull_none_8ma>, /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_2ma>, + <1 RK_PC5 2 &pcfg_pull_none_4ma>, /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_2ma>, + <1 RK_PC6 2 &pcfg_pull_none_4ma>, /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_2ma>, + <1 RK_PC7 2 &pcfg_pull_none_4ma>, /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_2ma>, + <1 RK_PB2 2 &pcfg_pull_none_4ma>, /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_2ma>, + <1 RK_PB3 2 &pcfg_pull_none_4ma>, /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_12ma>, + <1 RK_PB0 2 &pcfg_pull_none_8ma>, /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_12ma>, + <1 RK_PB1 2 &pcfg_pull_none_8ma>, /* mac_rxd3 */ - <1 RK_PB6 2 &pcfg_pull_none_2ma>, + <1 RK_PB6 2 &pcfg_pull_none_4ma>, /* mac_rxd2 */ - <1 RK_PB7 2 &pcfg_pull_none_2ma>, + <1 RK_PB7 2 &pcfg_pull_none_4ma>, /* mac_txd3 */ - <1 RK_PC0 2 &pcfg_pull_none_12ma>, + <1 RK_PC0 2 &pcfg_pull_none_8ma>, /* mac_txd2 */ - <1 RK_PC1 2 &pcfg_pull_none_12ma>, + <1 RK_PC1 2 &pcfg_pull_none_8ma>, /* mac_txclk */ - <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB0 1 &pcfg_pull_none_8ma>, /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none_8ma>, /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none>, + <0 RK_PD0 1 &pcfg_pull_none_4ma>, /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none_8ma>, /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none_8ma>, /* mac_txd3 */ - <0 RK_PC7 1 &pcfg_pull_none>, + <0 RK_PC7 1 &pcfg_pull_none_8ma>, /* mac_txd2 */ - <0 RK_PC6 1 &pcfg_pull_none>; + <0 RK_PC6 1 &pcfg_pull_none_8ma>; }; rmiim1_pins: rmiim1-pins { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index ce592a4c0c4c..075659847791 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -113,6 +113,19 @@ vin-supply = <&vcc_1v8>; }; + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -136,7 +149,7 @@ vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; @@ -315,7 +328,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; @@ -490,6 +503,13 @@ }; }; + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb2 { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = @@ -537,6 +557,7 @@ }; &sdmmc { + broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; @@ -545,6 +566,7 @@ max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; vqmmc-supply = <&vcc_sdio>; status = "okay"; }; |