diff options
Diffstat (limited to 'arch/arm64')
42 files changed, 9027 insertions, 461 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d5eb439fe4a6..a45e8def8d39 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -52,7 +52,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191 imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \ imx8mm-ddr4-evk-rm67191.dtb imx8mm-evk-revb.dtb imx8mm-ddr4-evk-revb.dtb \ imx8mm-ddr4-evk-revb-rm67191.dtb imx8mm-ddr3l-val.dtb \ - imx8mm-evk-usd-wifi.dtb + imx8mm-evk-usd-wifi.dtb \ + imx8mm-verdin-nonwifi-dahlia.dtb \ + imx8mm-verdin-nonwifi-dev.dtb \ + imx8mm-verdin-nonwifi-v1.1-dahlia.dtb \ + imx8mm-verdin-nonwifi-v1.1-dev.dtb \ + imx8mm-verdin-wifi-dahlia.dtb \ + imx8mm-verdin-wifi-dev.dtb \ + imx8mm-verdin-wifi-v1.1-dahlia.dtb \ + imx8mm-verdin-wifi-v1.1-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb @@ -91,7 +99,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \ imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \ imx8qm-mek-dsi-rm67191.dtb imx8qm-lpddr4-val-dp.dtb\ - imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb + imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb \ + imx8qm-apalis-eval.dtb \ + imx8qm-apalis-ixora-v1.1.dtb \ + imx8qm-apalis-v1.1-eval.dtb \ + imx8qm-apalis-v1.1-ixora-v1.1.dtb \ + imx8qp-apalis-v1.1-eval.dtb \ + imx8qp-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb @@ -134,7 +148,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640 imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \ - imx8qxp-lpddr4-val-mlb.dtb + imx8qxp-lpddr4-val-mlb.dtb \ + imx8qxp-colibri-aster.dtb \ + imx8qxp-colibri-dsihdmi-eval-v3.dtb \ + imx8qxp-colibri-eval-v3.dtb \ + imx8qxp-colibri-lvds-dual-eval-v3.dtb \ + imx8qxp-colibri-lvds-single-eval-v3.dtb \ + imx8qxp-apalis-eval.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ imx8qxp-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi new file mode 100644 index 000000000000..62af86afb69e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019-2020 Toradex + */ + +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC USBH2(ABCD) / USBH(3|4)"; + }; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +/* Apalis HDMI1 */ +&hdmi { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; + reg = <0x4a>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&wakeup_key { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi new file mode 100644 index 000000000000..7440b83c1424 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019-2020 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + /* MXM3_188 */ + led4-green { + label = "LED_4_GREEN"; + gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_178 */ + led4-red { + label = "LED_4_RED"; + gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_152 */ + led5-green { + label = "LED_5_GREEN"; + gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_156 */ + led5-red { + label = "LED_5_RED"; + gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC_USBH(2|4)"; + }; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +/* Apalis HDMI1 */ +&hdmi { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; + reg = <0x4a>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>, + <&pinctrl_uart24_forceoff>; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x41 /* LED_4_GREEN */ + IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x41 /* LED_4_RED */ + IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x41 /* LED_5_GREEN */ + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x41 /* LED_5_RED */ + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 + >; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&lsio_gpio5 { + ngpios = <32>; + gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03", + "gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07", + "gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11", + "gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15", + "gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19", + "LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23", + "gpio5-24", "UART24-FORCEOFF", "gpio5-26", + "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30", + "gpio5-31"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&wakeup_key { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi new file mode 100644 index 000000000000..63e3341a677e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -0,0 +1,1846 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2020 Toradex + */ + +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + stdout-path = &lpuart1; + }; + + /* Apalis BKL1 */ + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ + }; + + gpio-fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio8>; + gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + + /* Apalis WAKE1_MICO */ + wakeup_key: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + wakeup-key { + label = "Wake-Up"; + gpios = <&lsio_gpio2 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + + status = "disabled"; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + pcie_sata_refclk: sata-clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_sata_refclk_gate: sata-ref-clock { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; + #clock-cells = <0>; + clocks = <&pcie_sata_refclk>; + enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; + }; + + /* + * Power management bus used to control LDO1OUT of the + * second PMIC PF8100. This is used for controlling voltage levels of + * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS. + * + * IMX_SC_R_BOARD_R1 for 3.3V + * IMX_SC_R_BOARD_R2 for 1.8V + * IMX_SC_R_BOARD_R3 for 2.5V + * Note that for 2.5V operation the pad muxing needs to be changed, + * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD. + * + * those power domains are mutually exclusive. + */ + pmbus_external_rgmii: pmbusextrgmii { + compatible = "simple-pm-bus"; + power-domains = <&pd IMX_SC_R_BOARD_R1>; + }; + + pcie_wifi_refclk: wifi-clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_wifi_refclk_gate: wifi-ref-clock { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; + #clock-cells = <0>; + clocks = <&pcie_wifi_refclk>; + enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_wifi: regulator-module-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pdn>; + regulator-name = "wifi_pwrdn_fake_regulator"; + regulator-settling-time-us = <100>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + enable-active-high; + gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100000>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBH_EN */ + gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + ts_boot: ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + /* simple-audio-card,mclk-fs = <1>; */ + simple-audio-card,name = "apalis-imx8qm-sgtl5000"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + clocks = <&mclkout0_lpcg 0>; + sound-dai = <&sgtl5000>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai5>; + protocol = <1>; + hdmi-out; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + touchscreen: vf50-touchscreen { + compatible = "toradex,vf50-touchscreen"; + io-channels = <&adc1 2>,<&adc1 1>, + <&adc1 0>,<&adc1 3>; + xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; + xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>; + yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>; + ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "idle","default"; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; + pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; + vf50-ts-min-pressure = <200>; + /* NOTE: you must remove the pinctrl-adc1 from the adc1 + node below to use the touchscreen */ + status = "disabled"; + }; + +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_vref_1v8>; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; +}; + +/* Apalis GLAN */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,mii-exclusive; + phy-handle = <ðphy0>; + phy-mode = "rgmii-rxid"; + phy-reset-duration = <10>; + phy-reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&lsio_gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + power-domains = <&pd IMX_SC_R_BOARD_R0>; + reg = <7>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + /* xceiver-supply = <®_can_stby>; */ +}; + +/* Apalis CAN2 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + /* xceiver-supply = <®_can_stby>; */ +}; + +/* Apalis HDMI1 */ +&hdmi { + compatible = "cdn,imx8qm-hdmi"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ctrl>; + firmware-name = "imx/hdmi/hdmitxfw.bin"; + hdmi-ctrl-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + lane-mapping = <0x93>; +}; + +&hsio_refa_clk { + status = "disabled"; +}; + +&hsio_refb_clk { + status = "disabled"; +}; + +/* On-module I2C */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + reg = <0x0a>; + VDDA-supply = <®_module_3v3_avdd>; + VDDD-supply = <®_vref_1v8>; + VDDIO-supply = <®_module_3v3>; + }; + + /* USB3503A */ + usb3503@8 { + compatible = "smsc,usb3503a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; + refclk-frequency = <25000000>; + reg = <0x08>; + reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +/* Apalis I2C1 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, + <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, + <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, + <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>, + <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, + <&pinctrl_usdhc1_gpios>; + + apalis-imx8qm { + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + /* Apalis AN1_ADC1 */ + IMX8QM_ADC_IN1_DMA_ADC0_IN1 0xc0000060 + /* Apalis AN1_ADC2 */ + IMX8QM_ADC_IN2_DMA_ADC0_IN2 0xc0000060 + /* Apalis AN1_TSWIP_ADC3 */ + IMX8QM_ADC_IN3_DMA_ADC0_IN3 0xc0000060 + >; + }; + + /* Apalis AN1_TS */ + pinctrl_adc1: adc1grp { + fsl,pins = < + /* Apalis AN1_TSPX */ + IMX8QM_ADC_IN4_DMA_ADC1_IN0 0xc0000060 + /* Apalis AN1_TSMX */ + IMX8QM_ADC_IN5_DMA_ADC1_IN1 0xc0000060 + /* Apalis AN1_TSPY */ + IMX8QM_ADC_IN6_DMA_ADC1_IN2 0xc0000060 + /* Apalis AN1_TSMY */ + IMX8QM_ADC_IN7_DMA_ADC1_IN3 0xc0000060 + >; + }; + + /* Apalis BKL_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021 + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_bkl: pwmbklgrp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + /* Apalis CAM1 */ + pinctrl_cam1_gpios: cam1gpiosgrp { + fsl,pins = < + /* Apalis CAM1_D7 */ + IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021 + /* Apalis CAM1_D6 */ + IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021 + /* Apalis CAM1_D5 */ + IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021 + /* Apalis CAM1_D4 */ + IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021 + /* Apalis CAM1_D3 */ + IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021 + /* Apalis CAM1_D2 */ + IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021 + /* Apalis CAM1_D1 */ + IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021 + /* Apalis CAM1_D0 */ + IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021 + /* Apalis CAM1_PCLK */ + IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021 + /* Apalis CAM1_MCLK */ + IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021 + /* Apalis CAM1_VSYNC */ + IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021 + /* Apalis CAM1_HSYNC */ + IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021 + >; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_MCLK */ + IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021 + /* Apalis DAP1_D_OUT */ + IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021 + /* Apalis DAP1_RESET */ + IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + /* Apalis DAP1_BIT_CLK */ + IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021 + /* Apalis DAP1_D_IN */ + IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021 + /* Apalis DAP1_SYNC */ + IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + /* On-module Wi-Fi_I2S_EN# */ + IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021 + >; + }; + + /* Apalis GPIO1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = < + IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021 + >; + }; + + /* Apalis GPIO2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = < + IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021 + >; + }; + + /* Apalis GPIO3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021 + >; + }; + + /* Apalis GPIO4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = < + IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021 + >; + }; + + /* Apalis GPIO5 */ + pinctrl_gpio5: gpio5grp { + fsl,pins = < + IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021 + >; + }; + + /* Apalis GPIO6 */ + pinctrl_gpio6: gpio6grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x00000021 + >; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7grp { + fsl,pins = < + IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 + >; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8grp { + fsl,pins = < + IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 0x00000021 + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0x04000020 + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020 + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX8QM_SIM0_PD_DMA_I2C3_SCL 0x04000020 + IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020 + >; + }; + + /* Apalis LCD1_G1+2 */ + pinctrl_esai0_gpios: esai0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G1 */ + IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021 + /* Apalis LCD1_G2 */ + IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021 + >; + }; + + /* Apalis LCD1_G6+7 */ + pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G6 */ + IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021 + /* Apalis LCD1_G7 */ + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_fec2_gpios: fec2gpiosgrp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + /* Apalis LCD1_R1 */ + IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021 + /* Apalis LCD1_R0 */ + IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021 + /* Apalis LCD1_G0 */ + IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021 + /* Apalis LCD1_R7 */ + IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021 + /* Apalis LCD1_DE */ + IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021 + /* Apalis LCD1_HSYNC */ + IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021 + /* Apalis LCD1_VSYNC */ + IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021 + /* Apalis LCD1_PCLK */ + IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021 + /* Apalis LCD1_R6 */ + IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021 + /* Apalis LCD1_R5 */ + IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021 + /* Apalis LCD1_R4 */ + IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021 + /* Apalis LCD1_R3 */ + IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021 + /* Apalis LCD1_R2 */ + IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_qspi1a_gpios: qspi1agpiosgrp { + fsl,pins = < + /* Apalis LCD1_B0 */ + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + /* Apalis LCD1_B1 */ + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021 + /* Apalis LCD1_B2 */ + IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021 + /* Apalis LCD1_B3 */ + IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021 + /* Apalis LCD1_B5 */ + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + /* Apalis LCD1_B7 */ + IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021 + /* Apalis LCD1_B4 */ + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021 + /* Apalis LCD1_B6 */ + IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_sim0_gpios: sim0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G5 */ + IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 + /* Apalis LCD1_G3 */ + IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021 + /* Apalis TS_5 */ + IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 0x00000021 + /* Apalis LCD1_G4 */ + IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 0x00000021 + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_mmc1_cd: mmc1cdgrp { + fsl,pins = < + IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 + IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 + IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 + IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 + IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 + IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 + IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 + IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 + IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 + IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020 + >; + }; + + /* Apalis PWM2 */ + pinctrl_pwm3: pwm3grp { + fsl,pins = < + IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020 + >; + }; + + /* Apalis PWM3 */ + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020 + >; + }; + + /* Apalis PWM4 */ + pinctrl_pwm1: pwm1grp { + fsl,pins = < + IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020 + >; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + >; + }; + + /* Apalis SD1_CD# */ + pinctrl_sd1_cd: sd1cdgrp { + fsl,pins = < + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + /* Apalis SD1 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_touchctrl_idle: touchctrl_idle { + fsl,pins = < + IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 0x00000021 + IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 0x00000021 + IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021 + >; + }; + + pinctrl_touchctrl_gpios: touchctrl_gpios { + fsl,pins = < + IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021 + IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021 + IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + /* Apalis SPDIF */ + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x0600004c + >; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x0600004c + >; + }; + + /* Apalis TS_1 */ + pinctrl_mlb_gpios: mlbgpiosgrp { + fsl,pins = < + IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 0x00000021 + >; + }; + + /* Apalis TS_2 */ + pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021 + >; + }; + + /* Apalis TS_3 */ + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + /* Apalis TS_4 */ + pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { + fsl,pins = < + IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021 + >; + }; + + /* Apalis TS_6 */ + pinctrl_usdhc1_gpios: usdhc1gpiosgrp { + fsl,pins = < + IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021 + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + /* Apalis UART1_ */ + pinctrl_lpuart1ctrl: lpuart1ctrlgrp { + fsl,pins = < + /* Apalis UART1_DTR */ + IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021 + /* Apalis UART1_DSR */ + IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021 + /* Apalis UART1_DCD */ + IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021 + /* Apalis UART1_RI */ + IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021 + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020 + IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020 + IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020 + IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020 + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021 + >; + }; + + /* Apalis USBO1 */ + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + /* Apalis USBO1_EN */ + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + /* Apalis USBO1_OC# */ + IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021 + >; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */ + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */ + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* On-module ETH_RESET# */ + IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 + /* On-module ETH_INT# */ + IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000060 + >; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040 + IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040 + IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040 + IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040 + IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040 + IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040 + IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040 + IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040 + IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040 + IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040 + IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040 + IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040 + IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040 + IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040 + IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040 + IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040 + IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040 + >; + }; + + /* On-module HDMI_CTRL */ + pinctrl_hdmi_ctrl: hdmictrlgrp { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x04000020 + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020 + >; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0xc600006c + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0xc600004c + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0xc600004c + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c + >; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + /* On-module PCIe_CLK_EN1 */ + pinctrl_pcie_sata_refclk: pciesatarefclkgrp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + /* On-module PCIe_CLK_EN2 */ + pinctrl_pcie_wifi_refclk: pciewifirefclkgrp { + fsl,pins = < + IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021 + >; + }; + + /* On-module PCIe_Wi-Fi */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021 + >; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: resetmocigrp { + fsl,pins = < + IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 + >; + }; + + /* On-module USB HSIC HUB */ + pinctrl_usb3503a: usb3503agrp { + fsl,pins = < + /* On-module HSIC_HUB_CONNECT */ + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000041 + /* On-module HSIC_INT_N */ + IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021 + /* On-module HSIC_RESET_N */ + IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000041 + >; + }; + + /* On-module USB HSIC HUB (idle) */ + pinctrl_usb_hsic_idle: usbh1_1 { + fsl,pins = < + IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0xc60000c5 + IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000c5 + >; + }; + + /* On-module USB HSIC HUB (active) */ + pinctrl_usb_hsic_active: usbh1_2 { + fsl,pins = < + IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000d5 + >; + }; + + /* On-module Wi-Fi */ + pinctrl_wifi: wifigrp { + fsl,pins = < + /* On-module Wi-Fi_SUSCLK_32k */ + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021 + /* On-module Wi-Fi_PCIE_W_DISABLE */ + IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021 + >; + }; + + pinctrl_wifi_pdn: wifipdngrp { + fsl,pins = < + /* On-module Wi-Fi_POWER_DOWN */ + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021 + >; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; + + spidev0: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis SPI2 */ +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + + spidev1: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis UART3 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART2 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&lsio_gpio0 { + gpio-line-names = "MXM3_279", + "MXM3_277", + "MXM3_135", + "MXM3_203", + "MXM3_201", + "MXM3_275", + "MXM3_110", + "MXM3_120", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_124", + "MXM3_122", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "", + "", + "MXM3_4", + "MXM3_211", + "MXM3_209", + "MXM3_2", + "MXM3_136", + "MXM3_134", + "MXM3_6", + "MXM3_8", + "MXM3_112", + "MXM3_118", + "MXM3_114", + "MXM3_116"; +}; + +&lsio_gpio1 { + gpio-line-names = "", + "", + "", + "", + "MXM3_286", + "", + "MXM3_87", + "MXM3_99", + "MXM3_138", + "MXM3_140", + "MXM3_239", + "", + "MXM3_281", + "MXM3_283", + "MXM3_126", + "MXM3_132", + "", + "", + "", + "", + "MXM3_173", + "MXM3_175", + "MXM3_123"; +}; + +&lsio_gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "MXM3_198", + "MXM3_35", + "MXM3_164", + "", + "", + "", + "", + "MXM3_217", + "MXM3_215", + "", + "", + "MXM3_193", + "MXM3_194", + "MXM3_37", + "", + "MXM3_271", + "MXM3_273", + "MXM3_195", + "MXM3_197", + "MXM3_177", + "MXM3_179", + "MXM3_181", + "MXM3_183", + "MXM3_185", + "MXM3_187"; + + /* + * Add GPIO2_20 as a wakeup source: + * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: 20 + */ + pad-wakeup = <101 5 20>; + pad-wakeup-num = <1>; +}; + +&lsio_gpio3 { + gpio-line-names = "MXM3_191", + "", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_200", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_204", + "MXM3_196", + "", + "MXM3_202", + "", + "", + "", + "MXM3_305", + "MXM3_307", + "MXM3_309", + "MXM3_311", + "MXM3_315", + "MXM3_317", + "MXM3_319", + "MXM3_321", + "MXM3_15/GPIO7", + "MXM3_63", + "MXM3_17/GPIO8", + "MXM3_12", + "MXM3_14", + "MXM3_16"; +}; + +&lsio_gpio4 { + gpio-line-names = "MXM3_18", + "MXM3_11/GPIO5", + "MXM3_13/GPIO6", + "MXM3_274", + "MXM3_84", + "MXM3_262", + "MXM3_96", + "", + "", + "", + "", + "", + "MXM3_190", + "", + "", + "", + "MXM3_269", + "MXM3_251", + "MXM3_253", + "MXM3_295", + "MXM3_299", + "MXM3_301", + "MXM3_297", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287"; +}; + +&lsio_gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_159", + "MXM3_184", + "MXM3_180", + "MXM3_186", + "MXM3_188", + "MXM3_176", + "MXM3_178"; +}; + +&lsio_gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_261", + "MXM3_263", + "MXM3_259", + "MXM3_257", + "MXM3_255", + "MXM3_128", + "MXM3_130", + "MXM3_265", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_243"; +}; + +&mu_m0{ + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu1_m0{ + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu2_m0{ + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&mu3_m0{ + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&pcie_sata_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per", + "pcie_ext"; + + ext_osc = <1>; + fsl,max-link-speed = <1>; + reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_switch>; +}; + +/* On-module Wi-Fi */ +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx2_lpcg 1>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&pcie_wifi_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per", + "pcie_ext"; + epdev_on-supply = <®_module_wifi>; + ext_osc = <1>; + fsl,max-link-speed = <1>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm_lvds1 { + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + #pwm-cells = <3>; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + #pwm-cells = <3>; +}; + +&rpmsg0{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + memory-region = <&vdevbuffer>; +}; + +&sai1 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; +}; + +/* Apalis SATA1 */ +&sata { + clocks = <&sata_lpcg 0>, + <&phyx1_lpcg 0>, + <&phyx1_lpcg 1>, + <&phyx1_lpcg 2>, + <&phyx2_crr0_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&sata_crr4_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx2_lpcg 1>, + <&phyx1_lpcg 3>, + <&pcie_sata_refclk_gate>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "per_clk0", "per_clk1", "per_clk2", + "per_clk3", "per_clk4", "per_clk5", + "phy_pclk0", "phy_pclk1", "phy_apbclk", + "sata_ext"; + ext_osc = <1>; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + cooling_maps_map0: map0 { + trip = <&pmic_alert0>; + }; + }; + }; +}; + +&usb3phynop1 { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usb_hsic_idle>; + pinctrl-1 = <&pinctrl_usb_hsic_active>; + adp-disable; + disable-over-current; + hnp-disable; + srp-disable; +}; + +&usbphynop2 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + adp-disable; + ci-disable-lpm; + hnp-disable; + over-current-active-low; + power-active-high; + srp-disable; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <8>; + cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_mmc1_cd>; +}; + +/* Apalis SD1 */ +&usdhc3 { + bus-width = <4>; + cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; +}; + +&vpu_decoder { + compatible = "nxp,imx8qm-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d080000>; + core_type = <2>; + status = "okay"; +}; + +&vpu_ts { + compatible = "nxp,imx8qm-b0-vpu-ts"; + boot-region = <&ts_boot>; + reg-csr = <0x2d0b0000>; + status = "okay"; +}; + +&vpu_encoder { + compatible = "nxp,imx8qm-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpuenc2", "vpu"; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", + "enc2_tx0", "enc2_tx1", "enc2_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0 + &mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + status = "okay"; + + vpu_enc_core0: core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + + vpu_enc_core1: core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10A0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 4eb51cad186d..9badc2bfa915 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -62,6 +62,31 @@ conn_subsys: bus@5b000000 { reg = <0x5b0d0200 0x200>; }; + usbh1: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x5b0e0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "hsic"; + dr_mode = "host"; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd IMX_SC_R_USB_1>; + status = "disabled"; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0e0200 0x200>; + }; + usbphy1: usbphy@0x5b100000 { compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; @@ -183,6 +208,14 @@ conn_subsys: bus@5b000000 { status = "disabled"; }; + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&usb2_lpcg 1>; + clock-names = "main_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "okay"; + }; + usbotg3: usb3@5b110000 { compatible = "Cadence,usb3"; reg = <0x5B110000 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 5e2cc2787716..fcf6fd415950 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -30,7 +30,7 @@ dma_subsys: bus@5a000000 { <&spi0_lpcg 1>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <60000000>; power-domains = <&pd IMX_SC_R_SPI_0>; dma-names = "tx","rx"; dmas = <&edma2 1 0 0>, <&edma2 0 0 1>; @@ -329,6 +329,7 @@ dma_subsys: bus@5a000000 { adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x5a880000 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -343,6 +344,7 @@ dma_subsys: bus@5a000000 { adc1: adc@5a890000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x5a890000 0x10000>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index f406f6adce31..83bb00300d47 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -27,6 +27,54 @@ lsio_subsys: bus@5d000000 { clock-output-names = "lsio_bus_clk"; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x5d000000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm0_lpcg 4>, + <&pwm0_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x5d010000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm1_lpcg 4>, + <&pwm1_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x5d020000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm2_lpcg 4>, + <&pwm2_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x5d030000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm3_lpcg 4>, + <&pwm3_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + lsio_gpio0: gpio@5d080000 { reg = <0x5d080000 0x10000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index cffa8991880d..e7fac56db320 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -430,18 +430,26 @@ #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1B0 0x418 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_RX 0x1B0 0x418 0x4F4 0x4 0x2 #define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_TX 0x1B4 0x41C 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_CTS_B 0x1B8 0x420 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 @@ -464,21 +472,37 @@ #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B 0x1D4 0x43C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1D8 0x440 0x4FC 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_RX 0x1D8 0x440 0x4FC 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1DC 0x444 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x4FC 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_TX 0x1DC 0x444 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi new file mode 100755 index 000000000000..78bec5e3c94b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +#include "imx8mm-verdin-dev.dtsi" + +&gpio_expander_21 { + status = "disabled"; +}; + +&sound_card { + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi new file mode 100755 index 000000000000..2c3872f3a8f3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/* Verdin SPI_1 */ +&ecspi2 { + status = "okay"; + + spidev20: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +&gpio_expander_21 { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* VERDIN I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Audio Codec */ +&wm8904_1a { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts new file mode 100755 index 000000000000..8bfcac726dd3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dahlia", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts new file mode 100755 index 000000000000..6f3e76283e54 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dev", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-v1.1-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-v1.1-dahlia.dts new file mode 100755 index 000000000000..7c5c319737b7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-v1.1-dahlia.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin-v1.1.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini V1.1 on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-v1.1-dahlia", + "toradex,verdin-imx8mm-nonwifi-dahlia", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-v1.1-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-v1.1-dev.dts new file mode 100755 index 000000000000..0ec570e098fd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-v1.1-dev.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin-v1.1.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini V1.1 on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-v1.1-dev", + "toradex,verdin-imx8mm-nonwifi-dev", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi new file mode 100755 index 000000000000..c488a4111cdb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_162", + "SODIMM_164", + "SODIMM_166", + "SODIMM_168", + "SODIMM_66", + "SODIMM_17", + "", + "SODIMM_156", + "SODIMM_160", + "SODIMM_244", + "SODIMM_250", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "SODIMM_148", + "SODIMM_152", + "SODIMM_154", + "SODIMM_174", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_150", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; + +&usdhc3 { + bus-width = <4>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi new file mode 100755 index 000000000000..12d05b137a7c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi @@ -0,0 +1,1310 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019-2020 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "imx8mm.dtsi" + +/ { + chosen { + bootargs = "console=ttymxc0,115200 earlycon"; + stdout-path = &uart1; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + /* fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + /* Carrier Board Supply */ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "REG_3P3V"; + }; + + reg_aux_usb: regulator-aux-usb { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "REG_AUX_USB"; + }; + + reg_mipi_phy: regulator-mipi-phy { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "REG_MIPI_PHY"; + }; + + reg_ethphy: regulator-ethphy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "V3.3_ETH"; + startup-delay-us = <200000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB1_EN */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg1_vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB2_EN */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg2_vbus"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "V3.3_SD"; + startup-delay-us = <2000>; + off-on-delay = <100000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@b8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +/* On-module CAN controller 1 & 2 */ +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, + <&gpio1 5 GPIO_ACTIVE_LOW>; + /* This property is required, even if marked as obsolete in the doku */ + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can1: can@0 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + microchip,clock-allways-on; + microchip,clock-out-div = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + can2: can@1 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_int>; + reg = <1>; + spi-max-frequency = <2000000>; + /* not assembled */ + status = "disabled"; + }; +}; + +&fec1 { + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + phy-supply = <®_ethphy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; +#if 0 + flash0: mt25qu256aba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu256aba"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +#endif +}; + +&gpio1 { + gpio-line-names = "SODIMM_216", + "SODIMM_19", + "", + "", + "", + "", + "", + "", + "SODIMM_220", + "SODIMM_222", + "", + "SODIMM_218", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_187"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_131", + "", + "SODIMM_91", + "SODIMM_16", + "SODIMM_15", + "SODIMM_208", + "SODIMM_137", + "SODIMM_139", + "SODIMM_141", + "SODIMM_143", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_151", + "SODIMM_153"; + + ctrl_sleep_moci { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + i2c-lt-en = <0x101>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin I2C_1 (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 ADC_4 */ + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 ADC_3 */ + channel@5 { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 ADC_2 */ + channel@6 { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + /* Verdin I2C_1 ADC_1 */ + channel@7 { + reg = <7>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_3_HDMI N/A */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + /* Audio Codec */ + wm8904_1a: codec@1a { + compatible = "wlf,wm8904"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + clock-names = "mclk"; + reg = <0x1a>; + status = "disabled"; + DCVDD-supply = <®_3p3v>; + DBVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + CPVDD-supply = <®_3p3v>; + MICVDD-supply = <®_3p3v>; + }; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + status = "disabled"; + vcc-supply = <®_3p3v>; + }; + + /* Current measurement into module VCC */ + hwmon: hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "disabled"; + }; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + status = "disabled"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mu { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_3p3v>; + ext_osc = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reserved-region = <&rpmsg_reserved>; + reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +/* Verdin PWM_1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_2 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; +}; + +/* VERDIN I2S_1 */ +&sai2 { + #sound-dai-cells = <0>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_4 */ +/* + * resource allocated to M4 by default, must not be accessed from A-35 or you + * get an OOPS + */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbmisc1 { + vbus-wakeup-supply = <®_aux_usb>; +}; + +&usbmisc2 { + vbus-wakeup-supply = <®_aux_usb>; +}; + +/* Verdin USB_1 */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + over-current-active-low; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; +}; + +/* Verdin USB_2 */ +&usbotg2 { + dr_mode = "host"; + over-current-active-low; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usbphynop1 { + vcc-supply = <®_aux_usb>; +}; + +&usbphynop2 { + vcc-supply = <®_aux_usb>; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pm-ignore-notify; + status = "okay"; + /* TODO Strobe */ +}; + +/* Verdin SD_1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio7>, + <&pinctrl_gpio8>, <&pinctrl_gpio_hog1>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_sai5>, <&pinctrl_pmic_tpm_ena>; + + pinctrl_can1_int: can1intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 /* CAN_1_SPI_INT#_1.8V */ + >; + }; + + pinctrl_can2_int: can2intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 /* CAN_2_SPI_INT#_1.8V */ + >; + }; + + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* CTRL_SLEEP_MOCI */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + >; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + >; + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + >; + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + >; + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + >; + }; + + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ + >; + }; + + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ + >; + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4 /* SODIMM 252 */ + >; + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 /* PMIC_I2C_SDA */ + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6 /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6 /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6 /* SODIMM 93 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6 /* SODIMM 12 */ + >; + }; + + /* Verdin MEZ_DSI_1_BKL_EN */ + pinctrl_mez_dsi_1_bkl_en: mezdsi1bklengrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + >; + }; + + /* Verdin MEZ_DSI_1_INT HPD (pulled-down as active-high) */ + pinctrl_mez_dsi_1_int_hpd: mezdsi1inthpdgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ + >; + }; + + /* Verdin MEZ_DSI_1_INT# (pulled-up as active-low) */ + pinctrl_mez_dsi_1_int_n: mezdsi1intngrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4 /* SODIMM 17 */ + >; + }; + + /* MEZ_GPIO_1 shared with MEZ_DSI_1_INT on Verdin DSI to HDMI Display Adapter */ + pinctrl_mez_gpio1: mezgpio1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + >; + }; + + pinctrl_mez_gpio2: mezgpio2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4 /* SODIMM 208 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */ + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /* PMIC_INT# */ + >; + }; + + pinctrl_pwm_1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */ + >; + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */ + >; + }; + + pinctrl_pwm_3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */ + >; + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 /* PMIC_EN_ETH */ + >; + }; + + pinctrl_reg_usb1_en: regusb1engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + >; + }; + + pinctrl_reg_usb2_en: regusb2engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ + >; + }; + + /* currently unused ctrl signal for SE050 or ATTPM20P */ + pinctrl_pmic_tpm_ena: pmictpmenagrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4 /* PMIC_TPM_ENA */ + >; + }; + + pinctrl_tsp: tspgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* SODIMM 148 */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* SODIMM 152 */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140 /* SODIMM 154 */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 /* SODIMM 179 */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 /* SODIMM 150 */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1c4 /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1c4 /* SODIMM 147 */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1c4 /* SODIMM 129 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1c4 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + >; + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + /* On-module Wi-Fi/BT or SDHC interface on the X52 extention slot */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 /* PMIC_WDI */ + >; + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ + >; + }; + + pinctrl_wifi_i2s: bti2sgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 /* WIFI_TX_BCLK */ + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 /* WIFI_TX_DATA0 */ + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 /* WIFI_TX_SYNC */ + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 /* WIFI_RX_DATA0 */ + >; + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts new file mode 100755 index 000000000000..452c06e44a21 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-wifi-dahlia", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts new file mode 100755 index 000000000000..c9df17fa48c5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-wifi-dev", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-v1.1-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-v1.1-dahlia.dts new file mode 100755 index 000000000000..dbc1b4b15c37 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-v1.1-dahlia.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin-v1.1.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB V1.1 on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-wifi-v1.1-dahlia", + "toradex,verdin-imx8mm-wifi-dahlia", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-v1.1-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-v1.1-dev.dts new file mode 100755 index 000000000000..0aec23ac9806 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-v1.1-dev.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin-v1.1.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB V1.1 on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-wifi-v1.1-dev", + "toradex,verdin-imx8mm-wifi-dev", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi new file mode 100755 index 000000000000..75c44efe8ac8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-name = "V3.3_WI-FI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + wifi-host; + status = "okay"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "SODIMM_17", + "", + "", + "", + "SODIMM_244", + "SODIMM_250", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "", + "", + "", + "SODIMM_174", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi new file mode 100644 index 000000000000..464b85291db0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2017-2020 Toradex + */ + +#include "imx8mm-verdin-v1.1.dtsi" + +/ { + pcie0_refclk: pcie0-refclk { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + /* on-module ext oscillator */ + enable-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + /delete-node/ pca9450@25; + + pmic_v10: bd71837@4b { + compatible = "rohm,bd71837"; + interrupt-parent = <&gpio1>; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + interrupts = <3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x4b>; + rohm,reset-snvs-powered; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + buck1_reg: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <1250>; + }; + + buck5_reg: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + regulator-name = "BUCK5"; + }; + + buck6_reg: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-name = "BUCK6"; + }; + + buck7_reg: BUCK7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + regulator-name = "BUCK7"; + }; + + buck8_reg: BUCK8 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + regulator-name = "BUCK8"; + }; + + ldo1_reg: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1900000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo2_reg: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO2"; + }; + + ldo3_reg: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO3"; + }; + + ldo4_reg: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + regulator-name = "LDO4"; + }; + + ldo5_reg: LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "LDO5"; + }; + + ldo6_reg: LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + regulator-name = "LDO6"; + }; + }; + }; + + adc: adc@34 { + compatible = "maxim,max11607"; + reg = <0x34>; + vcc-supply = <&ldo5_reg>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + ext_osc = <1>; +}; + +&iomuxc { + pinctrl_ctrl_force_off_moci: ctrlforceoffgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts new file mode 100644 index 000000000000..ebff51c16c03 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019-2020 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-eval", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts new file mode 100644 index 000000000000..91bc4435fb49 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019-2020 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8qp-ixora-v1.1", + "toradex,apalis-imx8-ixora-v1.1", + "toradex,apalis-imx8qp-ixora", + "toradex,apalis-imx8-ixora", + "toradex,apalis-imx8qp", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..6589cdb2251b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-v1.1-eval", + "toradex,apalis-imx8-eval", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts new file mode 100644 index 000000000000..579a27fb5662 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019-2020 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1", + "toradex,apalis-imx8-v1.1-ixora", + "toradex,apalis-imx8-v1.1", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi new file mode 100644 index 000000000000..65188f479d03 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2020 Toradex + */ + +#include <dt-bindings/pwm/pwm.h> +#include "imx8qm.dtsi" +#include "imx8-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1"; + compatible = "toradex,apalis-imx8-v1.1", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; + +&cooling_maps_map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi new file mode 100644 index 000000000000..1612e4bae594 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2020 Toradex + */ + +#include "imx8qm-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM"; + compatible = "toradex,apalis-imx8", + "fsl,imx8qm"; +}; + +/delete-node/ &pcie_wifi_refclk; +/delete-node/ &pcie_wifi_refclk_gate; + +ðphy0 { + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +}; + +&lsio_gpio0 { + gpio-line-names = "MXM3_279", + "MXM3_277", + "MXM3_135", + "MXM3_203", + "MXM3_201", + "MXM3_275", + "MXM3_110", + "MXM3_120", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_124", + "MXM3_122", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "", + "", + "MXM3_4", + "MXM3_211", + "MXM3_209", + "MXM3_2", + "MXM3_136", + "MXM3_134", + "MXM3_6", + "MXM3_8", + "MXM3_112", + "MXM3_118", + "MXM3_114", + "MXM3_116"; +}; + +&lsio_gpio1 { + gpio-line-names = "", + "", + "", + "", + "MXM3_286", + "", + "MXM3_87", + "MXM3_99", + "MXM3_138", + "MXM3_140", + "MXM3_239", + "", + "MXM3_281", + "MXM3_283", + "MXM3_126", + "MXM3_132", + "", + "", + "", + "", + "MXM3_173", + "MXM3_175", + "MXM3_123"; +}; + +&lsio_gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "MXM3_198", + "MXM3_35", + "MXM3_164", + "", + "", + "", + "", + "MXM3_217", + "MXM3_215", + "", + "", + "MXM3_193", + "MXM3_194", + "MXM3_37", + "", + "MXM3_271", + "MXM3_273", + "MXM3_195", + "MXM3_197", + "MXM3_177", + "MXM3_179", + "MXM3_181", + "MXM3_183", + "MXM3_185", + "MXM3_187"; +}; + +&lsio_gpio3 { + gpio-line-names = "MXM3_191", + "", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_200", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_204", + "MXM3_196", + "", + "MXM3_202", + "", + "", + "", + "MXM3_305", + "MXM3_307", + "MXM3_309", + "MXM3_311", + "MXM3_315", + "MXM3_317", + "MXM3_319", + "MXM3_321", + "MXM3_15/GPIO7", + "MXM3_63", + "MXM3_17/GPIO8", + "MXM3_12", + "MXM3_14", + "MXM3_16"; +}; + +&lsio_gpio4 { + gpio-line-names = "MXM3_18", + "MXM3_11/GPIO5", + "MXM3_13/GPIO6", + "MXM3_274", + "MXM3_84", + "MXM3_262", + "MXM3_96", + "", + "", + "", + "", + "", + "MXM3_190", + "", + "", + "", + "MXM3_269", + "MXM3_251", + "MXM3_253", + "MXM3_295", + "MXM3_299", + "MXM3_301", + "MXM3_297", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287"; +}; + +&lsio_gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_159", + "MXM3_184", + "MXM3_180", + "MXM3_186", + "MXM3_188", + "MXM3_176", + "MXM3_178"; +}; + +&lsio_gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_261", + "MXM3_263", + "MXM3_259", + "MXM3_257", + "MXM3_255", + "MXM3_128", + "MXM3_130", + "MXM3_265", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_243"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c0>; +}; + +&pinctrl_fec1 { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 1.8V mode */ + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* On-module ETH_RESET# */ + IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 + /* On-module ETH_INT# */ + IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000060 + >; +}; + +&pinctrl_fec1_sleep { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040 + IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040 + IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040 + IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040 + IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040 + IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040 + IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040 + IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040 + IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040 + IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040 + IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040 + IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040 + IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040 + IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040 + IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040 + IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040 + IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040 + >; +}; + +&iomuxc { + apalis-imx8qm { + /* Apalis I2C2 (DDC) */ + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022 + >; + }; + }; +}; + +/* On-module PCIe_CTRL0_CLKREQ */ +&pinctrl_pcie_sata_refclk { + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 + >; +}; + +&pcie_sata_refclk_gate { + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>; +}; + +/* On-module Wi-Fi */ +&pcieb { + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx2_lpcg 1>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&pcie_sata_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per", + "pcie_ext"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..80de879b15a1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8qp-v1.1-eval", + "toradex,apalis-imx8qp-v1.1", + "toradex,apalis-imx8-v1.1", + "toradex,apalis-imx8", + "fsl,imx8qp", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts new file mode 100644 index 000000000000..b57e9caccb42 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8qp-v1.1-ixora-v1.1", + "toradex,apalis-imx8qp-v1.1-ixora", + "toradex,apalis-imx8qp-v1.1", + "toradex,apalis-imx8-v1.1", + "toradex,apalis-imx8", + "fsl,imx8qp", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi new file mode 100644 index 000000000000..b40a9a4425c3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Toradex + */ + +#include "imx8qp.dtsi" +#include "imx8-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1"; + compatible = "toradex,apalis-imx8qp-v1.1", + "toradex,apalis-imx8qp", + "toradex,apalis-imx8", + "fsl,imx8qp", + "fsl,imx8qm"; +}; + +&cooling_maps_map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dts b/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dts new file mode 100644 index 000000000000..420a628794c0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-apalis.dtsi" +#include "imx8qxp-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QXP/DX on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8x-eval", + "toradex,apalis-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dtsi new file mode 100644 index 000000000000..d1ae7e18bee8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + /* TODO: Move this panel to the overlay */ + panel_dpi: panel-dpi { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + * logictechno,lt161010-2nhc: Cap. Touch Display 7" Parallel + * logictechno,lt161010-2nhr: Res. Touch Display 7" Paralle + * logictechno,lt170410-2whc: Cap. Touch Display 10.1" LVDS + * tpk,f07a-0102: Capacitive Multi-Touch Display Fusion 7" + * tpk,f10a-0102: Capacitive Multi-Touch Display Fusion 10" + */ + compatible = "panel-dpi"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "bgr666"; + status = "disabled"; + + panel-timing { + /* Default VESA VGA display timings */ + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + pixelclk-active = <0>; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbo1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBO1_EN */ + gpio = <&lsio_gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-name = "usb_host_vbus_hub"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + /* Apalis USBH_EN */ + gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&adc0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan3 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&isi_0 { + interface = <2 0 2>; + /** + * interface = <Input MIPI_VCx Output> + * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI + * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + * Output: 0-DC0, 1-DC1, 2-MEM + */ + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + interface = <6 0 2>; + parallel_csi; + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&ldb1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; + + spidev0: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; + + spidev1: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart3 { + status = "okay"; +}; + +&lsio_gpio1 { + /** + * Add GPIO1_26 as a wakeup source: + * Pin: SC_P_MIPI_DSI0_I2C0_SDA (MXM3_37) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: GPIO1_IO26 + */ + pad-wakeup = <117 5 26>; + pad-wakeup-num = <1>; +}; + +/* On-module GPIO Expander */ +&pcal6416_1 { + /* + * This gpio-hog drives a muxing device. With that we can choose + * if LVDS1_B pins are active or if DVI signals are active. Those + * signals are then muxed to MIPI_DSI1 PADs. + * + * output-high; muxes to DVI signals + * output-low; muxes to LVDS1_B signals + */ + LVDS_HDMI_MUX { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "LVDS_HDMI_MUX"; + }; +}; + +/* Apalis PCIE1 */ +&pcieb { + status = "okay"; +}; + +/* Apalis PWM2 */ +&pwm_mipi_lvds0 { + status = "okay"; +}; + +/* Apalis PWM1 */ +&pwm2 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + adp-disable; + ci-disable-lpm; + hnp-disable; + over-current-active-low; + srp-disable; + status = "okay"; + vbus-supply = <®_usb_otg1_vbus>; +}; + +&usbotg3 { + vbus-regulator = <®_usb_host_vbus>; +}; + +&usbphy1 { + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&vpu_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-apalis.dtsi new file mode 100644 index 000000000000..eceee543e6c6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-apalis.dtsi @@ -0,0 +1,1388 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/gpio/gpio.h> +#include "dt-bindings/pwm/pwm.h" +#include "imx8qxp.dtsi" + +/ { + model = "Toradex Apalis iMX8QXP/DX Module"; + compatible = "toradex,apalis-imx8x", + "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + enable-gpios = <&lsio_gpio3 13 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart1; + }; + + display_lcdif: display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + }; + + gpio-fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio8>; + gpios = <&lsio_gpio3 20 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + + /* Apalis WAKE1_MICO */ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + wakeup_key: wakeup-key { + label = "Wake-Up"; + gpios = <&lsio_gpio1 26 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + imx8x_cm4: imx8x_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + core-index = <0>; + core-id = <IMX_SC_R_M4_0_PID0>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + + status = "disabled"; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + enable-active-high; + gpio = <&lsio_gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8qxp-sgtl5000"; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000_a>; + clocks = <&mclkout0_lpcg 0>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; +}; + +/* Apalis AN1_ADC */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_module_vref_1v8>; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +/* Apalis Gigabit Ethernet */ +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&lsio_gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <4>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Apalis CAN2 */ +&flexcan3 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + /* On-Module EEPROM */ + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + /* PCAL6416A GPIO Expander */ + pcal6416_1: gpio@20 { + compatible = "nxp,pcal6416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_exp1_int>; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_module_3v3>; + ngpios = <16>; + gpio-line-names = "HDMI1_CEC", "SPDIF1_IN", "SPDIF1_OUT", + "UART4_TXD", "UART1_DCD", "UART1_RI", "UART1_DSR", + "UART1_DTR", "PWM1", "Wi-Fi_WKUP_WLAN", + "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_BT", "Wi-Fi_PDn", + "Wi-Fi_WKUP_HOST", "DSI_SW_SEL", "HDMI1_HPD"; + }; + + /* PCAL6416A GPIO Expander */ + pcal6416_2: gpio@21 { + compatible = "nxp,pcal6416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_exp2_int>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_module_3v3>; + }; + + sgtl5000_a: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&aud_pll_div0_lpcg 0>, + <&aud_rec0_lpcg 0>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + reg = <0xa>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_module_vref_1v8>; + }; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; +}; + +/* Apalis I2C1 */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + clock-frequency = <100000>; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + clock-frequency = <100000>; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dap1_gpios>, <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_mmc1_gpios>, <&pinctrl_qspi0a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_usbo1oc>, <&pinctrl_wifi_sclk>; + + apalis-imx8qxp { + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* MXM3 305 */ + /* Apalis AN1_ADC1 */ + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* MXM3 307 */ + /* Apalis AN1_ADC2 */ + IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* MXM3 309 */ + /* Apalis AN1_TSWIP_ADC3 */ + IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* MXM3 311 */ + >; + }; + + /* Apalis BKL1_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x21 /* MXM3 286 */ + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_mipi_lvds1: pwmmipilvds1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x60 /* MXM3 239 */ + >; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* MXM3 14 */ + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* MXM3 12 */ + >; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* MXM3 18 */ + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* MXM3 16 */ + >; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_D_OUT */ + IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x21 /* MXM3 196 */ + /* Apalis DAP1_RESET */ + IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x21 /* MXM3 198 */ + /* Apalis DAP1_BIT_CLK */ + IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x21 /* MXM3 200 */ + /* Apalis DAP1_D_IN */ + IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x21 /* MXM3 202 */ + /* Apalis DAP1_SYNC */ + IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x21 /* MXM3 204 */ + >; + }; + + /* Apalis GPIO1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = < + IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x21 /* MXM3 1 */ + >; + }; + + /* Apalis GPIO2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = < + IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x21 /* MXM3 3 */ + >; + }; + + /* Apalis GPIO3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = < + IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x21 /* MXM3 5 */ + >; + }; + + /* Apalis GPIO4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = < + IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* MXM3 7 */ + >; + }; + + /* Apalis GPIO5 */ + pinctrl_gpio5: gpio5grp { + fsl,pins = < + IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x21 /* MXM3 11 */ + >; + }; + + /* Apalis GPIO6 */ + pinctrl_gpio6: gpio6grp { + fsl,pins = < + IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x21 /* MXM3 13 */ + >; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7grp { + fsl,pins = < + IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x21 /* MXM3 15 */ + >; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8grp { + fsl,pins = < + IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x21 /* MXM3 17 */ + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000021 /* MXM3 211 */ + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 /* MXM3 209 */ + >; + }; + + /* Apalis I2C2 (DDC) */ + pinctrl_i2c0_mipi_lvds1: mipilvds1i2c0grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* MXM3 205 */ + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* MXM3 207 */ + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX8QXP_CSI_EN_ADMA_I2C3_SCL 0xc6000020 /* MXM3 203 */ + IMX8QXP_CSI_RESET_ADMA_I2C3_SDA 0xc6000020 /* MXM3 201 */ + >; + }; + + /* Apalis MMC1_ */ + pinctrl_mmc1_gpios: mmc1gpiosgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x21 /* MXM3 148 */ + IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x21 /* MXM3 158 */ + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x21 /* MXM3 156 */ + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x21 /* MXM3 152 */ + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_usdhc2_gpio: mmc1gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* MXM3 164 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { + fsl,pins = < + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* MXM3 164 */ + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* MXM3 154 */ + IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* MXM3 150 */ + IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* MXM3 160 */ + IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* MXM3 162 */ + IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* MXM3 144 */ + IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* MXM3 146 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* Apalis Parallel Camera */ + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 /* MXM3 187 */ + IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 /* MXM3 185 */ + IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 /* MXM3 183 */ + IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 /* MXM3 181 */ + IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 /* MXM3 179 */ + IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 /* MXM3 177 */ + IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 /* MXM3 175 */ + IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 /* MXM3 173 */ + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 /* MXM3 193 */ + IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 /* MXM3 191 */ + IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 /* MXM3 197 */ + IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 /* MXM3 195 */ + >; + }; + + /* Apalis Parallel RGB LCD Interface */ + pinctrl_hog0: hog0grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* MXM3 243 */ + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* MXM3 245 */ + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* MXM3 247 */ + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* MXM3 249 */ + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* MXM3 255 */ + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* MXM3 257 */ + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* MXM3 259 */ + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* MXM3 261 */ + IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* MXM3 263 */ + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* MXM3 265 */ + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* MXM3 273 */ + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* MXM3 275 */ + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* MXM3 277 */ + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* MXM3 279 */ + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* MXM3 281 */ + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* MXM3 283 */ + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* MXM3 291 */ + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* MXM3 293 */ + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* MXM3 295 */ + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* MXM3 297 */ + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* MXM3 299 */ + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* MXM3 301 */ + >; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* MXM3 2 */ + >; + }; + + /* Apalis PWM2 */ + pinctrl_pwm_mipi_lvds0: pwmmipilvds0grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x60 /* MXM3 4 */ + >; + }; + + /* Apalis PWM_ */ + pinctrl_pwm_gpios: gpiospwmgrp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x21 /* MXM3 6 */ + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x21 /* MXM3 8 */ + >; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0x21 /* MXM3 35 */ + >; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x06000040 /* MXM3 227 */ + IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x06000040 /* MXM3 223 */ + IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x06000040 /* MXM3 225 */ + IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x06000040 /* MXM3 221 */ + >; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* MXM3 233 */ + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* MXM3 229 */ + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* MXM3 231 */ + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* MXM3 235 */ + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 /* MXM3 118 */ + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 /* MXM3 112 */ + >; + }; + + /* Apalis UART1_ */ + pinctrl_qspi0a_gpios: qspi0agpiosgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x21 /* MXM3 114 */ + IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x21 /* MXM3 116 */ + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* MXM3 126 */ + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* MXM3 132 */ + IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* MXM3 128 */ + IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* MXM3 130 */ + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* MXM3 134 */ + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* MXM3 136 */ + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX 0x06000020 /* MXM3 138 */ + IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX 0x06000020 /* MXM3 140 */ + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x21 /* MXM3 84 */ + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x04000020 /* MXM3 96 */ + >; + }; + + /* Apalis USBO1_EN */ + pinctrl_usbo1_en: usbo1en { + fsl,pins = < + /* Apalis USBO1_EN */ + IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x21 /* MXM3 274 */ + >; + }; + + /* Apalis USBO1 */ + pinctrl_usbo1oc: usbo1oc { + fsl,pins = < + /* Apalis USBO1_OC# */ + IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x04000020 /* MXM3 262 */ + >; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0x06680021 /* MXM3 37 */ + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 /* Use pads in 3.3V mode */ + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 /* Use pads in 3.3V mode */ + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 + /* On-module ETH_RESET# */ + IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x21 + /* On-module ETH_INT# */ + IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 0x21 + >; + }; + + /* On-module GPIO expanders */ + pinctrl_i2c_exp1_int: i2cexp1int { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x21 + >; + }; + + pinctrl_i2c_exp2_int: i2cexp2int { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x21 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c0: i2c0csi0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0xc6000020 /* MXM3 140 */ + IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0xc6000020 /* MXM3 142 */ + >; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + >; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: gpioresetmocigrp { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x11 + >; + }; + + pinctrl_wifi_sclk: wifigrp { + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 /* WiFi Sleep clock */ + >; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>; +}; + +/* Apalis SPI2 */ +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; +}; + +/* Apalis UART2 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART3 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART4 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&lsio_gpio0 { + gpio-line-names = "", + "MXM3_293", + "MXM3_295", + "MXM3_297", + "MXM3_299", + "MXM3_301", + "MXM3_273", + "MXM3_275", + "MXM3_277", + "MXM3_279", + "MXM3_281", + "MXM3_283", + "MXM3_255", + "MXM3_257", + "MXM3_259", + "MXM3_261", + "MXM3_247", + "", + "", + "MXM3_245", + "MXM3_243", + "MXM3_112", + "MXM3_118", + "", + "MXM3_265", + "MXM3_196", + "MXM3_200", + "MXM3_202", + "MXM3_204", + "MXM3_310", + "MXM3_312", + "MXM3_318"; +}; + +&lsio_gpio1 { + gpio-line-names = "MXM3_235", + "MXM3_233", + "MXM3_231", + "MXM3_229", + "MXM3_221", + "MXM3_223", + "MXM3_225", + "MXM3_316", + "MXM3_227", + "MXM3_307", + "MXM3_305", + "MXM3_194", + "", + "MXM3_311", + "MXM3_309", + "MXM3_128", + "MXM3_130", + "MXM3_12", + "MXM3_14", + "MXM3_16", + "MXM3_18", + "MXM3_132", + "MXM3_126", + "MXM3_134", + "MXM3_136", + "MXM3_35", + "MXM3_37", + "MXM3_4", + "MXM3_6", + "MXM3_207", + "MXM3_205", + "MXM3_239"; +}; + +&lsio_gpio2 { + gpio-line-names = "MXM3_8", + "", + "", + "MXM3_140"; +}; + +&lsio_gpio3 { + gpio-line-names = "MXM3_191", + "MXM3_193", + "MXM3_203", + "MXM3_201", + "", + "", + "", + "", + "", + "MXM3_96", + "MXM3_110", + "MXM3_114", + "MXM3_116", + "MXM3_286", + "MXM3_158", + "MXM3_198", + "MXM3_274", + "MXM3_11", + "MXM3_13", + "MXM3_15", + "MXM3_17", + "MXM3_1", + "MXM3_3", + "MXM3_5", + "MXM3_7"; +}; + +&lsio_gpio4 { + gpio-line-names = "", + "", + "", + "MXM3_211", + "MXM3_84", + "MXM3_262", + "MXM3_209", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_152", + "MXM3_148", + "MXM3_156", + "MXM3_164", + "MXM3_154", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_77", + "MXM3_79", + "MXM3_65"; + + reset { + gpio-hog; + gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + output-high; + }; +}; + +&lsio_gpio5 { + gpio-line-names = "MXM3_67", + "MXM3_71", + "MXM3_73", + "MXM3_113", + "MXM3_115", + "MXM3_119", + "MXM3_121", + "MXM3_125", + "MXM3_127", + "MXM3_131", + "MXM3_59", + "MXM3_61"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; +}; + +&mipi0_dsi_host { + pwr-delay = <10>; +}; + +&mipi1_dsi_host { + pwr-delay = <10>; +}; + +/* Apalis PCIE1 */ +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + bus-range = <0x00 0xff>; + ext_osc = <0>; + fsl,max-link-speed = <2>; + reserved-region = <&rpmsg_reserved>; + /* + * Workaround: Handle reset as a gpio-hog in &lsio_gpio4 + * reset-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + */ + vpcie-supply = <®_pcie_switch>; +}; + +/* Apalis PWM2 */ +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + #pwm-cells = <3>; +}; + +/* Apalis BKL1_PWM */ +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "okay"; +}; + +/* On-module I2S */ +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* Manage on-module USB WiFi */ +&usb3phynop1 { + status = "okay"; + reset-on-resume; +}; + +/* + * Apalis USB 3.0 Host. Serves USB 3.0 4-port hub on module and + * USB 3.0 ports on-board + */ +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d040000>; + core_type = <1>; +}; + +&vpu_encoder { + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts new file mode 100644 index 000000000000..06eb4f9e929d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on Aster Board"; + compatible = "toradex,colibri-imx8x-aster", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog2>; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-dsihdmi-eval-v3.dts new file mode 100644 index 000000000000..7cfdadb02b57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-dsihdmi-eval-v3.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with LT8912 MIPI-DSI 2 HDMI bridge"; + compatible = "toradex,colibri-imx8x-dsihdmi-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; + +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + /* DSI/LVDS Hot Plug Detect on FFC (X2) */ + pinctrl_gpio_hpd: gpio-hpd { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20 /* SODIMM 138 */ + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts new file mode 100644 index 000000000000..0824887773c9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx8x-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..302356d1e33e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2020 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + /* fixed crystal dedicated to mcp25xx */ + clk16m: clock-16mhz-fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + panel_dpi: panel-dpi { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + * logictechno,lt161010-2nhc: Cap. Touch Display 7" Parallel + * logictechno,lt161010-2nhr: Res. Touch Display 7" Paralle + * logictechno,lt170410-2whc: Cap. Touch Display 10.1" LVDS + * tpk,f07a-0102: Capacitive Multi-Touch Display Fusion 7" + * tpk,f10a-0102: Capacitive Multi-Touch Display Fusion 10" + */ + compatible = "panel-dpi"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "bgr666"; + status = "disabled"; + + panel-timing { + /* Default VESA VGA display timings */ + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + pixelclk-active = <0>; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + status = "okay"; +}; + +/* Colibri PWM_A */ +&adma_pwm { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +/* Colibri SPI */ +&lpspi2 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + status = "okay"; + }; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "disabled"; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +&lsio_gpio3 { + /* + * Add GPIO3_10 as a wakeup source: + * Pin: 157 SC_P_QSPI0A_DATA1 (SODIMM_45) + * Type: 6 SC_PAD_WAKEUP_RISE_EDGE + * Line: 10 GPIO3_IO10 + */ + pad-wakeup = <IMX8QXP_QSPI0A_DATA1 6 10>; + pad-wakeup-num = <1>; + }; + +/* Colibri PWM_B */ +&pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&pwm2 { + status = "okay"; +}; + +/* USB PHY for &usbotg3 */ +&usb3phynop1 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB PHY for &usbotg1 */ +&usbphy1 { + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_lpcg { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-dual-eval-v3.dts new file mode 100644 index 000000000000..84ee70779f81 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-dual-eval-v3.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "imx8qxp-colibri.dtsi" +#include "imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with dual channel lvds"; + compatible = "toradex,colibri-imx8x-lvds-dual-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; + +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-single-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-single-eval-v3.dts new file mode 100644 index 000000000000..4dbc5f378dd0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-single-eval-v3.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "imx8qxp-colibri.dtsi" +#include "imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with single channel lvds"; + compatible = "toradex,colibri-imx8x-lvds-single-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_touch: touchgrp { + fsl,pins = < + IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x06000040 /* SODIMM 28 */ + IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x06000020 /* SODIMM 30 */ + >; + }; + + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi new file mode 100644 index 000000000000..97a5fc44fd57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -0,0 +1,1302 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2020 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "imx8qxp.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX Module"; + compatible = "toradex,colibri-imx8x", + "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "disabled"; + }; + + chosen { + bootargs = "console=ttyLP3,115200"; + stdout-path = &lpuart3; + }; + + /* Colibri Parallel RGB */ + display_lcdif: display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + }; + + pcie_refclk: pcie-clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_refclk_gate: pcie-ref-clock { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clocks = <&pcie_refclk>; + enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_vref_1v8: regulator-module-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8qxp-sgtl5000"; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000_a>; + clocks = <&mclkout0_lpcg 0>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + }; + + vdd_3v3_vga: regulator-vga-avcc { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVCC_VGA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + status = "okay"; + vref-supply = <®_module_vref_1v8>; +}; + +/* Colibri PWM_A */ +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_a>; + #pwm-cells = <3>; +}; + +&cameradev { + status = "disabled"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +&enet0_lpcg { + clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_ref_50mhz_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; +}; + +/* Colibri Ethernet */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +/* Colibri optional CAN on UART_B RTS/CTS */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on PS2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on UART_A TXD/RXD */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_module_3v3>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&hsio_refb_clk { + status = "disabled"; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + /* + * There is a shared clock between SGTL5000 and on-module USB hub, + * so it is a good way to handle pinmuxing for this clock on a parent + * device i2c0 + */ + pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; + status = "okay"; + + /* GPIO expander */ + gpio_expander_43: gpio-expander@43 { + compatible = "fcs,fxl6408"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x43>; + inital_io_dir = <0xff>; + inital_output = <0x05>; + gpio-line-names = "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_WLAN", + "PWR_EN_+V3.3_WiFi_N", "PCIe_REF_CLK_EN", + "USB_RESET_N", "USB_BYPASS_N", "Wi-Fi_PDn", + "Wi-Fi_WKUP_BT"; + }; + + sgtl5000_a: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + reg = <0xa>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_module_vref_1v8>; + }; + + /* USB3503A */ + usb3803@8 { + compatible = "smsc,usb3803"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "refclk"; + disabled-ports = <2>; + initial-mode = <1>; + intn-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>; + non-removable-devices = <1>; + reg = <0x8>; + reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; + }; +}; + +/* MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; +}; + +/* On-module MIPI CSI I2C accessible on FFC (X3) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; +}; + +/* Colibri I2C */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>, + <&pinctrl_ext_io0>; + + colibri-imx8qxp { + /* Colibri Analogue Inputs */ + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ + IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ + IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ + >; + }; + + pinctrl_can_int: can-int-grp { + fsl,pins = < + IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ + >; + }; + + pinctrl_csi_ctl: csictlgrp { + fsl,pins = < + IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ + IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ + >; + }; + + /* Colibri UART_B */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ + IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ + IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ + >; + }; + + /* Colibri UART_C */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ + >; + }; + + /* Colibri UART_A */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ + >; + }; + + /* Colibri UART_A Control */ + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ + IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ + >; + }; + + /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 + >; + }; + + pinctrl_fec1_sleep: fec1-sleep-grp { + fsl,pins = < + IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 + IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 + IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 + IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 + IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 + IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 + IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 + IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 + IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 + IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 + >; + }; + + /* Colibri LCD Back-Light GPIO */ + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ + IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ + IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ + IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ + IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ + IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ + IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ + IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ + IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ + IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ + IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ + IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ + IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ + IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ + >; + }; + + pinctrl_hog2: hog2grp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ + IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ + >; + }; + + /* + * This pin is used in the SCFW as a UART. Using it from + * Linux would require rewritting the SCFW board file. + */ + pinctrl_hog_scfw: hogscfwgrp { + fsl,pins = < + IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ + >; + }; + + /* On Module I2C */ + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + >; + }; + + /* Colibri I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ + IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ + >; + }; + + /* Colibri optional CAN on UART_B RTS/CTS */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ + >; + }; + + /* Colibri optional CAN on PS2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ + >; + }; + + /* Colibri optional CAN on UART_A TXD/RXD */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ + >; + }; + + /* On module wifi module */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ + >; + }; + + /* Colibri PWM_A */ + pinctrl_pwm_a: pwma { + /* both pins are connected together, reserve the unused CSI_D05 */ + fsl,pins = < + IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ + IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ + >; + }; + + /* Colibri PWM_B */ + pinctrl_pwm_b: pwmb { + fsl,pins = < + IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ + >; + }; + + /* Colibri PWM_C */ + pinctrl_pwm_c: pwmc { + fsl,pins = < + IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ + >; + }; + + /* Colibri PWM_D */ + pinctrl_pwm_d: pwmd { + /* both pins are connected together, reserve the unused CSI_D04 */ + fsl,pins = < + IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ + IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ + >; + }; + + /* On-module I2S */ + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + /* Colibri Audio Analogue Microphone GND */ + pinctrl_sgtl5000: sgtl5000 { + fsl,pins = < + /* MIC GND EN */ + IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 + >; + }; + + /* On-module SGTL5000 clock */ + pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { + fsl,pins = < + IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module USB interrupt */ + pinctrl_usb3503a: usb3503a-grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 + >; + }; + + /* Colibri USB Client Cable Detect */ + pinctrl_usbc_det: usbc-det { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ + >; + }; + + pinctrl_ext_io0: ext-io0 { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ + >; + }; + + /* Colibri Parallel RGB LCD Interface */ + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40 /* SODIMM 44 */ + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40 /* SODIMM 44 */ + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ + IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ + IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ + >; + }; + + /* USB Host Power Enable */ + pinctrl_usbh1_reg: usbh1-reg { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Colibri SDCard CardDetect */ + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ + >; + }; + + /* Colibri SDCard */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ + >; + }; + + /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ + >; + }; + + /* Colibri SPI */ + pinctrl_lpspi2: lpspi2 { + fsl,pins = < + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + }; +}; + +&isi_0 { + interface = <2 0 2>; + /** + * interface = <Input MIPI_VCx Output> + * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI + * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + * Output: 0-DC0, 1-DC1, 2-MEM + */ +}; + +&isi_1 { + interface = <6 0 2>; + parallel_csi; +}; + +/* Colibri SPI */ +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; +}; + +/* Colibri UART_B */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Colibri UART_C */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Colibri UART_A */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; +}; + +&lsio_gpio0 { + gpio-line-names = "", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_68", + "", + "", + "SODIMM_82", + "SODIMM_56", + "SODIMM_28", + "SODIMM_30", + "", + "SODIMM_61", + "SODIMM_103", + "", + "", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_100"; + status = "okay"; +}; + +&lsio_gpio1 { + gpio-line-names = "SODIMM_86", + "SODIMM_92", + "SODIMM_90", + "SODIMM_88", + "", + "", + "", + "SODIMM_59", + "", + "SODIMM_6", + "SODIMM_8", + "", + "", + "SODIMM_2", + "SODIMM_4", + "SODIMM_34", + "SODIMM_32", + "SODIMM_63", + "SODIMM_55", + "SODIMM_33", + "SODIMM_35", + "SODIMM_36", + "SODIMM_38", + "SODIMM_21", + "SODIMM_19", + "SODIMM_140", + "SODIMM_142", + "SODIMM_196", + "SODIMM_194", + "SODIMM_186", + "SODIMM_188", + "SODIMM_138"; + status = "okay"; +}; + +&lsio_gpio2 { + gpio-line-names = "SODIMM_23", + "", + "", + "SODIMM_144"; + status = "okay"; +}; + +&lsio_gpio3 { + gpio-line-names = "SODIMM_96", + "SODIMM_75", + "SODIMM_37", + "SODIMM_29", + "", + "", + "", + "", + "", + "SODIMM_43", + "SODIMM_45", + "SODIMM_69", + "SODIMM_71", + "SODIMM_73", + "SODIMM_77", + "SODIMM_89", + "SODIMM_93", + "SODIMM_95", + "SODIMM_99", + "SODIMM_105", + "SODIMM_107", + "SODIMM_98", + "SODIMM_102", + "SODIMM_104", + "SODIMM_106"; + status = "okay"; +}; + +&lsio_gpio4 { + gpio-line-names = "", + "", + "", + "SODIMM_129", + "SODIMM_133", + "SODIMM_127", + "SODIMM_131", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_44", + "", + "SODIMM_76", + "SODIMM_31", + "SODIMM_47", + "SODIMM_190", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; + status = "okay"; +}; + +&lsio_gpio5 { + gpio-line-names = "", + "SODIMM_57", + "SODIMM_65", + "SODIMM_85", + "", + "", + "", + "", + "SODIMM_135", + "SODIMM_137", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184"; + status = "okay"; +}; + +/* MIPI CSI accessible via FFC (X3) */ +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; +}; + +&mipi0_dsi_host { + pwr-delay = <10>; +}; + +&mipi1_dsi_host { + pwr-delay = <10>; +}; + +/* On-module PCIe for wifi */ +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&pcie_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per", + "pcie_ext"; + + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + fsl,max-link-speed = <1>; + hard-wired = <1>; + disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>; + reserved-region = <&rpmsg_reserved>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_b>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_C */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_c>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_D */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_d>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "okay"; +}; + +/* On-module I2S */ +&sai0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + disable-wp; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d040000>; + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + status = "okay"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; + diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 12309e8a6237..882429442ae0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -23,46 +23,16 @@ CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y +CONFIG_BPF_SYSCALL=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y -CONFIG_ARCH_AGILEX=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_ALPINE=y -CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y -CONFIG_ARCH_BRCMSTB=y -CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_LG1K=y -CONFIG_ARCH_HISI=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MESON=y -CONFIG_ARCH_MVEBU=y CONFIG_ARCH_MXC=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_RENESAS=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y -CONFIG_SOC_S32V234=y -CONFIG_ARCH_SEATTLE=y -CONFIG_ARCH_STRATIX10=y -CONFIG_ARCH_SYNQUACER=y -CONFIG_ARCH_TEGRA=y -CONFIG_ARCH_SPRD=y -CONFIG_ARCH_THUNDER=y -CONFIG_ARCH_THUNDER2=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_XGENE=y -CONFIG_ARCH_ZX=y -CONFIG_ARCH_ZYNQMP=y CONFIG_ARM64_VA_BITS_48=y CONFIG_SCHED_MC=y CONFIG_NUMA=y @@ -70,7 +40,7 @@ CONFIG_SECCOMP=y CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y CONFIG_XEN=y -CONFIG_COMPAT=y +CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_RANDOMIZE_BASE=y CONFIG_PM_DEBUG=y CONFIG_PM_TEST_SUSPEND=y @@ -80,25 +50,20 @@ CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_IMX_CPUFREQ_DT=y -CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -CONFIG_ARM_TEGRA186_CPUFREQ=y -CONFIG_QORIQ_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_RASPBERRYPI_FIRMWARE=y -CONFIG_INTEL_STRATIX10_SERVICE=y CONFIG_EFI_CAPSULE_LOADER=y CONFIG_IMX_DSP=y CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y +CONFIG_IMX_SECO_MU=y CONFIG_ACPI=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y @@ -113,15 +78,18 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_SHA512_ARM64_CE=m CONFIG_CRYPTO_SHA3_ARM64=m CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_SM4_ARM64_CE=m CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_NHPOLY1305_NEON=m CONFIG_CRYPTO_AES_ARM64_BS=m CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_KSM=y CONFIG_MEMORY_FAILURE=y @@ -155,19 +123,26 @@ CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y CONFIG_LLC2=y -CONFIG_TSN=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_CBS=y +CONFIG_NET_SCH_TAPRIO=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y CONFIG_NET_SWITCHDEV=y -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m CONFIG_BPF_JIT=y +CONFIG_NET_PKTGEN=y CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m CONFIG_CAN_FLEXCAN=m -CONFIG_BT=y +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP25XXFD=m +CONFIG_BT=m CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y @@ -179,53 +154,40 @@ CONFIG_BT_HIDP=y CONFIG_BT_LEDS=y # CONFIG_BT_DEBUGFS is not set CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIVHCI=y -CONFIG_CFG80211=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_CFG80211=m CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m CONFIG_PCI=y CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCI_IOV=y CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_AARDVARK=y -CONFIG_PCI_TEGRA=y -CONFIG_PCIE_RCAR=y CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_XGENE=y -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCI_IMX6=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_KIRIN=y -CONFIG_PCIE_HISI_STB=y -CONFIG_PCIE_TEGRA194=m -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_HISILICON_LPC=y +CONFIG_BRCMSTB_GISB_ARB=y CONFIG_SIMPLE_PM_BUS=y -CONFIG_FSL_MC_BUS=y -CONFIG_FSL_MC_UAPI_SUPPORT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -240,19 +202,17 @@ CONFIG_MTD_DATAFLASH=y CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_GPMI_NAND=y -CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=m CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=y -CONFIG_SENSORS_FXOS8700=y -CONFIG_SENSORS_FXAS2100X=y +CONFIG_SENSORS_FXOS8700=m +CONFIG_SENSORS_FXAS2100X=m CONFIG_SRAM=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=m @@ -264,18 +224,12 @@ CONFIG_SCSI_HISI_SAS_PCI=y CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=m -CONFIG_SCSI_UFS_HISI=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_IMX=y CONFIG_AHCI_CEVA=y -CONFIG_AHCI_MVEBU=y -CONFIG_AHCI_XGENE=y -CONFIG_AHCI_QORIQ=y CONFIG_SATA_SIL24=y -CONFIG_SATA_RCAR=y CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_MD=y @@ -289,216 +243,164 @@ CONFIG_MACVTAP=m CONFIG_TUN=y CONFIG_VETH=m CONFIG_VIRTIO_NET=y -CONFIG_AMD_XGBE=y -CONFIG_NET_XGENE=y -CONFIG_ATL1C=m -CONFIG_BNX2X=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y CONFIG_FEC=y -CONFIG_FSL_SDK_DPAA_ETH=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_ENETC=y -CONFIG_FSL_ENETC_VF=y -CONFIG_FSL_ENETC_MDIO=y -CONFIG_ENETC_TSN=y -CONFIG_HIX5HD2_GMAC=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -CONFIG_HNS3_ENET=y -CONFIG_E1000=y -CONFIG_E1000E=y -CONFIG_IGB=y -CONFIG_IGBVF=y -CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_SKY2=y +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_SKY2=m CONFIG_MLX4_EN=m CONFIG_MLX5_CORE=m CONFIG_MLX5_CORE_EN=y -CONFIG_MSCC_OCELOT_SWITCH=y -CONFIG_QCOM_EMAC=m -CONFIG_RAVB=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_SNI_AVE=y -CONFIG_SNI_NETSEC=y -CONFIG_STMMAC_ETH=m +CONFIG_SMC91X=m +CONFIG_SMSC911X=m +CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_AQUANTIA_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_INPHI_PHY=y +CONFIG_AT803X_PHY=m +CONFIG_INPHI_PHY=m CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MESON_GXL_PHY=m CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_NXP_TJA11XX_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_VITESSE_PHY=y +CONFIG_MICROSEMI_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_PPP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_PPP_ASYNC=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m CONFIG_USB_NET_DM9601=m CONFIG_USB_NET_SR9800=m CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m -CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_PCIE=y -CONFIG_HOSTAP=y -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_NXP is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IVSHMEM_NET=m +CONFIG_INPUT_MATRIXKMAP=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_SNVS_PWRKEY=y CONFIG_KEYBOARD_IMX_SC_PWRKEY=y -CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m CONFIG_INPUT_MISC=y -CONFIG_INPUT_PM8941_PWRKEY=y -CONFIG_INPUT_HISI_POWERKEY=y -CONFIG_INPUT_MPL3115=y -CONFIG_INPUT_ISL29023=y +CONFIG_INPUT_MPL3115=m +CONFIG_INPUT_ISL29023=m # CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_AMBAKMI=m CONFIG_LEGACY_PTY_COUNT=16 CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_BCM2835AUX=y CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_OMAP=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_UNIPHIER=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIAL_TEGRA_TCU=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_QCOM_GENI=y -CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_DEV_BUS=y CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_BCM2835=m CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_GPIO=m CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y -CONFIG_I2C_MESON=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_PXA=y -CONFIG_I2C_QCOM_GENI=m -CONFIG_I2C_QUP=y CONFIG_I2C_RK3X=y CONFIG_I2C_RPBUS=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_I2C_TEGRA=y -CONFIG_I2C_UNIPHIER_F=y -CONFIG_I2C_RCAR=y -CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_XEN_I2C_BACKEND=y +CONFIG_I2C_SLAVE=y CONFIG_SPI=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SPI_BCM2835=m -CONFIG_SPI_BCM2835AUX=m CONFIG_SPI_FSL_LPSPI=y CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y -CONFIG_SPI_FSL_DSPI=y -CONFIG_SPI_MESON_SPICC=m -CONFIG_SPI_MESON_SPIFC=m -CONFIG_SPI_ORION=y +CONFIG_SPI_FSL_SPI=y CONFIG_SPI_PL022=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_QUP=y -CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SUN6I=y CONFIG_SPI_SPIDEV=y CONFIG_SPI_SLAVE=y CONFIG_SPI_SLAVE_TIME=y CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPMI=y +CONFIG_PPS_CLIENT_LDISC=y +CONFIG_PPS_CLIENT_GPIO=y +CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_IPQ8074=y -CONFIG_PINCTRL_MSM8916=y -CONFIG_PINCTRL_S32V234=y -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_QCS404=y -CONFIG_PINCTRL_QDF2XXX=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_PINCTRL_SDM845=y -CONFIG_PINCTRL_SM8150=y +CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_MB86S7X=y -CONFIG_GPIO_MPC8XXX=y CONFIG_GPIO_PL061=y -CONFIG_GPIO_RCAR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XGENE_SB=y +CONFIG_GPIO_FXL6408=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_MAX77620=y CONFIG_POWER_AVS=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_BRCMSTB=y CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_BQ27XXX=m +CONFIG_SENSORS_ADT7410=m CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT3x=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TMP102=m CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y @@ -506,68 +408,31 @@ CONFIG_THERMAL_EMULATION=y CONFIG_IMX_SC_THERMAL=y CONFIG_DEVICE_THERMAL=y CONFIG_IMX8MM_THERMAL=y -CONFIG_QORIQ_THERMAL=y -CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_ARMADA_THERMAL=y -CONFIG_BCM2835_THERMAL=m -CONFIG_BRCMSTB_THERMAL=m -CONFIG_EXYNOS_THERMAL=y -CONFIG_TEGRA_BPMP_THERMAL=m -CONFIG_QCOM_TSENS=y -CONFIG_UNIPHIER_THERMAL=y CONFIG_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y CONFIG_DW_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=m CONFIG_IMX2_WDT=y CONFIG_IMX_SC_WDT=y -CONFIG_MESON_GXBB_WATCHDOG=m -CONFIG_MESON_WATCHDOG=m -CONFIG_RENESAS_WDT=y -CONFIG_UNIPHIER_WATCHDOG=y -CONFIG_BCM2835_WDT=y -CONFIG_MFD_ALTERA_SYSMGR=y -CONFIG_MFD_BD9571MWV=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_EXYNOS_LPASS=m +CONFIG_XEN_WDT=y CONFIG_MFD_IMX_AUDIOMIX=y CONFIG_MFD_HI6421_PMIC=y -CONFIG_MFD_HI655X_PMIC=y CONFIG_MFD_MAX77620=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y -CONFIG_MFD_SEC_CORE=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_PCA9450=y +CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y CONFIG_REGULATOR_BD718XX=y -CONFIG_REGULATOR_BD9571MWV=y -CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI6421V530=y -CONFIG_REGULATOR_HI655X=y -CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_PCA9450=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_RPMH=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y -CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_REGULATOR_RK808=y -CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y CONFIG_RC_DEVICES=y -CONFIG_IR_MESON=m -CONFIG_IR_SUNXI=m CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y @@ -582,83 +447,75 @@ CONFIG_VIDEO_MX8_CAPTURE=y CONFIG_VIDEO_MXC_CAPTURE=y CONFIG_VIDEO_MXC_CSI_CAMERA=y CONFIG_MXC_MIPI_CSI=y -CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y -CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -CONFIG_VIDEO_RENESAS_FCP=m -CONFIG_VIDEO_RENESAS_VSP1=m -CONFIG_VIDEO_OV5640=y +CONFIG_VIDEO_OV5640=m CONFIG_IMX_DPU_CORE=y CONFIG_IMX_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I2C_NXP_TDA9950=m CONFIG_DRM_MALI_DISPLAY=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS5433_DECON=y -CONFIG_DRM_EXYNOS7_DECON=y -CONFIG_DRM_EXYNOS_DSI=y -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_EXYNOS_MIC=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m -CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m +CONFIG_DRM_VGEM=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_RAYDIUM_RM67191=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_DUMB_VGA_DAC=m +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_LVDS_ENCODER=y +CONFIG_DRM_LONTIUM_LT8912=y CONFIG_DRM_SII902X=m CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_CDNS_MHDP=y +CONFIG_DRM_CDNS_HDMI=y +CONFIG_DRM_CDNS_DP=y +CONFIG_DRM_CDNS_AUDIO=y CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_ITE_IT6263=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_IMX_SEC_DSIM=y -CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_CDNS_MHDP=m CONFIG_DRM_IMX_DCSS=y -CONFIG_DRM_VC4=m CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_HISI_KIRIN=m CONFIG_DRM_MXSFB=y -CONFIG_DRM_MESON=m -CONFIG_DRM_PL111=m -CONFIG_DRM_LIMA=m -CONFIG_DRM_PANFROST=m -CONFIG_FB_ARMCLCD=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_TILEBLITTING=y CONFIG_FB_EFI=y CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=y CONFIG_SND=y -CONFIG_SND_HDA_TEGRA=m -CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y -CONFIG_SND_BCM2835_SOC_I2S=m -CONFIG_SND_SOC_FSL_EASRC=y CONFIG_SND_SOC_FSL_DAI=m +CONFIG_SND_SOC_FSL_EASRC=y +CONFIG_SND_SOC_FSL_AUD2HTX=y CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_IMX_AK4458=y CONFIG_SND_SOC_IMX_AK5558=y @@ -673,62 +530,75 @@ CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_AUDMIX=y CONFIG_SND_SOC_IMX_PDM_MIC=y CONFIG_SND_SOC_IMX_DSP=y -CONFIG_SND_SOC_IMX_CDNHDMI=y -CONFIG_SND_MESON_AXG_SOUND_CARD=m -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_SAMSUNG=y -CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_IMX_CDNHDMI=m +CONFIG_SND_SOC_IMX_XCVR=y CONFIG_SND_SOC_SOF_TOPLEVEL=y CONFIG_SND_SOC_SOF_OF=m CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y -CONFIG_SND_SUN4I_SPDIF=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SOF_IMX8_SUPPORT=m +CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=m +CONFIG_SND_SOC_BT_SCO=y +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_WM8904=m CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_EZKEY=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m CONFIG_I2C_HID=m CONFIG_USB=y CONFIG_USB_OTG=y +CONFIG_USB_OTG_WHITELIST=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_EXYNOS=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_EXYNOS=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_HCD_TEST_MODE=y CONFIG_USB_ACM=m +CONFIG_USB_WDM=m CONFIG_USB_STORAGE=y CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB_DWC3=y CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_TEST=m CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_HUB_USB251XB=y CONFIG_USB_HSIC_USB3503=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=m -CONFIG_USB_RENESAS_USB3=m -CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS=m CONFIG_USB_CONFIGFS_SERIAL=y CONFIG_USB_CONFIGFS_ACM=y CONFIG_USB_CONFIGFS_OBEX=y @@ -749,6 +619,7 @@ CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_ZERO=m CONFIG_USB_AUDIO=m CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m CONFIG_USB_MASS_STORAGE=m CONFIG_USB_G_SERIAL=m CONFIG_TYPEC=y @@ -765,20 +636,12 @@ CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_TEGRA=y CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_MESON_GX=y -CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_SPI=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_UNIPHIER=y CONFIG_MMC_DW=y CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_HI3798CV200=y CONFIG_MMC_DW_K3=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SUNXI=y -CONFIG_MMC_BCM2835=y CONFIG_MMC_SDHCI_XENON=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -792,194 +655,103 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_EDAC=y CONFIG_EDAC_GHES=y +CONFIG_EDAC_SYNOPSYS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_PCF2127=y CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_CROS_EC=y -CONFIG_RTC_DRV_S3C=y CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_RTC_DRV_ARMADA38X=y -CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_SNVS=y CONFIG_RTC_DRV_IMX_SC=y -CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y -CONFIG_DMA_BCM2835=m -CONFIG_DMA_SUN6I=m +CONFIG_BCM_SBA_RAID=m CONFIG_FSL_EDMA=y CONFIG_FSL_EDMA_V3=y -CONFIG_IMX_SDMA=y -CONFIG_K3_DMA=y -CONFIG_MV_XOR=y +CONFIG_IMX_SDMA=m CONFIG_MV_XOR_V2=y CONFIG_MXS_DMA=y CONFIG_PL330_DMA=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_HIDMA=y -CONFIG_RCAR_DMAC=y -CONFIG_RENESAS_USB_DMAC=m CONFIG_DMATEST=y CONFIG_UIO=y CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_IVSHMEM=y CONFIG_VFIO=y CONFIG_VFIO_PCI=y -CONFIG_VFIO_FSL_MC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y CONFIG_XEN_GNTDEV=y CONFIG_XEN_GRANT_DEV_ALLOC=y CONFIG_STAGING=y +CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_IMX_CAPTURE=y CONFIG_ION=y CONFIG_ION_SYSTEM_HEAP=y CONFIG_ION_CMA_HEAP=y -CONFIG_FSL_DPAA2=y -CONFIG_FSL_DPAA2_ETHSW=y -CONFIG_FSL_DPAA2_MAC=y CONFIG_FSL_SDK_DPA=y CONFIG_FSL_PPFE=y CONFIG_FSL_PPFE_UTIL_DISABLED=y -CONFIG_MFD_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_VERSATILE=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y -CONFIG_CLK_RASPBERRYPI=m CONFIG_CLK_IMX8MM=y CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y -CONFIG_TI_SCI_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_A53PLL=y -CONFIG_QCOM_CLK_APCS_MSM8916=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_QCOM_CLK_RPMH=y -CONFIG_IPQ_GCC_8074=y -CONFIG_MSM_GCC_8916=y -CONFIG_MSM_GCC_8994=y -CONFIG_MSM_MMCC_8996=y -CONFIG_MSM_GCC_8998=y -CONFIG_QCS_GCC_404=y -CONFIG_SDM_GCC_845=y -CONFIG_SM_GCC_8150=y CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y -CONFIG_BCM2835_MBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_V3=y -CONFIG_QCOM_IOMMU=y CONFIG_REMOTEPROC=y -CONFIG_QCOM_Q6V5_MSS=m -CONFIG_QCOM_Q6V5_PAS=m -CONFIG_QCOM_SYSMON=m +CONFIG_IMX_REMOTEPROC=y CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=m -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_RASPBERRYPI_POWER=y -CONFIG_FSL_MC_DPIO=y +CONFIG_SOC_BRCMSTB=y CONFIG_FSL_QIXIS=y CONFIG_IMX_SCU_SOC=y -CONFIG_QCOM_GENI_SE=y -CONFIG_QCOM_GLINK_SSR=m -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_QCOM_SMP2P=y -CONFIG_QCOM_SMSM=y -CONFIG_ARCH_R8A774A1=y -CONFIG_ARCH_R8A774C0=y -CONFIG_ARCH_R8A7795=y -CONFIG_ARCH_R8A7796=y -CONFIG_ARCH_R8A77965=y -CONFIG_ARCH_R8A77970=y -CONFIG_ARCH_R8A77980=y -CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77995=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_K3_AM6_SOC=y -CONFIG_ARCH_K3_J721E_SOC=y -CONFIG_TI_SCI_PM_DOMAINS=y +CONFIG_SECVIO_SC=y +CONFIG_SOC_TI=y +CONFIG_EXTCON_GPIO=y CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_IIO=y -CONFIG_EXYNOS_ADC=y +CONFIG_BMC150_ACCEL=m +CONFIG_IIO_ST_ACCEL_3AXIS=m CONFIG_IMX8QXP_ADC=y -CONFIG_ROCKCHIP_SARADC=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_IIO_CROS_EC_BARO=m +CONFIG_MAX1363=y +CONFIG_TI_ADS1015=y +CONFIG_BMG160=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_ISL29125=m +CONFIG_SI1145=m +CONFIG_VEML6070=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_MS5611_SPI=m CONFIG_PWM=y -CONFIG_PWM_BCM2835=m -CONFIG_PWM_CROS_EC=m CONFIG_PWM_IMX27=y -CONFIG_PWM_MESON=m -CONFIG_PWM_RCAR=m -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SAMSUNG=y -CONFIG_PWM_SUN4I=m -CONFIG_PWM_TEGRA=m -CONFIG_RESET_TI_SCI=y -CONFIG_PHY_XGENE=y -CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y CONFIG_PHY_MIXEL_MIPI_DPHY=y -CONFIG_PHY_HI6220_USB=y -CONFIG_PHY_HISTB_COMBPHY=y -CONFIG_PHY_HISI_INNO_USB2=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PHY_QCOM_QMP=m -CONFIG_PHY_QCOM_QUSB2=m -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_RCAR_GEN3_PCIE=y -CONFIG_PHY_RCAR_GEN3_USB2=y -CONFIG_PHY_RCAR_GEN3_USB3=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_PCIE=m -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_UNIPHIER_USB2=y -CONFIG_PHY_UNIPHIER_USB3=y -CONFIG_PHY_TEGRA_XUSB=y CONFIG_FSL_IMX8_DDR_PMU=y -CONFIG_HISI_PMU=y -CONFIG_QCOM_L2_PMU=y -CONFIG_QCOM_L3_PMU=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_QCOM_QFPROM=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_UNIPHIER_EFUSE=y -CONFIG_MESON_EFUSE=m CONFIG_FPGA=y -CONFIG_FPGA_MGR_STRATIX10_SOC=m CONFIG_FPGA_BRIDGE=m CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_FPGA_REGION=m @@ -988,11 +760,13 @@ CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_MMIO=y CONFIG_MXC_SIM=y +CONFIG_MXC_SIMv2=y CONFIG_MXC_EMVSIM=y CONFIG_MXC_MLB150=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_FANOTIFY=y @@ -1003,52 +777,84 @@ CONFIG_FUSE_FS=m CONFIG_CUSE=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS_POSIX_ACL=y CONFIG_HUGETLBFS=y CONFIG_EFIVAR_FS=y CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y -CONFIG_SQUASHFS=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y +CONFIG_CIFS=m +CONFIG_9P_FS=m +CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y CONFIG_SECURITY=y CONFIG_CRYPTO_USER=y CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_TLS=m CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_STREEBOG=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y +# CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_INDIRECT_PIO=y +CONFIG_CRC_CCITT=y CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y @@ -1058,3 +864,6 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_MEMTEST=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM4X=y |