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-rw-r--r--arch/arm/include/asm/mvf_edma_regs.h65
-rw-r--r--arch/arm/include/asm/mvf_switch.h90
-rw-r--r--arch/arm/mach-mvf/board-twr_vf600.c52
-rw-r--r--arch/arm/mach-mvf/clock.c2
-rw-r--r--arch/arm/mach-mvf/irq.c4
-rw-r--r--arch/arm/mach-mvf/l2switch.c119
-rw-r--r--arch/arm/plat-mxc/include/mach/mvf.h4
7 files changed, 138 insertions, 198 deletions
diff --git a/arch/arm/include/asm/mvf_edma_regs.h b/arch/arm/include/asm/mvf_edma_regs.h
index d5d2f253df07..b87d47ee9bd7 100644
--- a/arch/arm/include/asm/mvf_edma_regs.h
+++ b/arch/arm/include/asm/mvf_edma_regs.h
@@ -86,46 +86,43 @@
/* Register read/write macros */
/* offset 0x0000_0000 - 0x0000_00ff main dma control area */
-#define MVF_EDMA_CR(base) MVF_REG32((long)(base) + 0x00000000)
-#define MVF_EDMA_ES(base) MVF_REG32((long)(base) + 0x00000004)
-//#define MVF_EDMA_ERQH(base) MVF_REG32((long)(base) + 0x00000008)
-#define MVF_EDMA_ERQ(base) MVF_REG32((long)(base) + 0x0000000C)
-//#define MVF_EDMA_EEIH(base) MVF_REG32((long)(base) + 0x00000010)
-#define MVF_EDMA_EEI(base) MVF_REG32((long)(base) + 0x00000014)
-#define MVF_EDMA_SERQ(base) MVF_REG08((long)(base) + 0x00000008)
-#define MVF_EDMA_CERQ(base) MVF_REG08((long)(base) + 0x00000019)
-#define MVF_EDMA_SEEI(base) MVF_REG08((long)(base) + 0x0000001A)
-#define MVF_EDMA_CEEI(base) MVF_REG08((long)(base) + 0x0000001B)
-#define MVF_EDMA_CINT(base) MVF_REG08((long)(base) + 0x0000001C)
-#define MVF_EDMA_CERR(base) MVF_REG08((long)(base) + 0x0000001D)
-#define MVF_EDMA_SSRT(base) MVF_REG08((long)(base) + 0x0000001E)
-#define MVF_EDMA_CDNE(base) MVF_REG08((long)(base) + 0x0000001F)
-//#define MVF_EDMA_INTH(base) MVF_REG32((long)(base) + 0x00000020)
-#define MVF_EDMA_INT(base) MVF_REG32((long)(base) + 0x00000024)
-//#define MVF_EDMA_ERRH(base) MVF_REG32((long)(base) + 0x00000028)
-#define MVF_EDMA_ERR(base) MVF_REG32((long)(base) + 0x0000002C)
-//#define MVF_EDMA_RSH(base) MVF_REG32((long)(base) + 0x00000030)
-#define MVF_EDMA_RS(base) MVF_REG32((long)(base) + 0x00000034)
+#define MVF_EDMA_CR(base) MVF_REG32((long)((long)(base) + 0x00000000))
+#define MVF_EDMA_ES(base) MVF_REG32((long)((long)(base) + 0x00000004))
+#define MVF_EDMA_ERQ(base) MVF_REG32((long)((long)(base) + 0x0000000C))
+#define MVF_EDMA_EEI(base) MVF_REG32((long)((long)(base) + 0x00000014))
+
+#define MVF_EDMA_CEEI(base) MVF_REG08((long)((long)(base) + 0x00000018))
+#define MVF_EDMA_SEEI(base) MVF_REG08((long)((long)(base) + 0x00000019))
+#define MVF_EDMA_CERQ(base) MVF_REG08((long)((long)(base) + 0x0000001a))
+#define MVF_EDMA_SERQ(base) MVF_REG08((long)((long)(base) + 0x0000001b))
+#define MVF_EDMA_CDNE(base) MVF_REG08((long)((long)(base) + 0x0000001c))
+#define MVF_EDMA_SSRT(base) MVF_REG08((long)((long)(base) + 0x0000001d))
+#define MVF_EDMA_CERR(base) MVF_REG08((long)((long)(base) + 0x0000001e))
+#define MVF_EDMA_CINT(base) MVF_REG08((long)((long)(base) + 0x0000001f))
+
+#define MVF_EDMA_INT(base) MVF_REG32((long)((long)(base) + 0x00000024))
+#define MVF_EDMA_ERR(base) MVF_REG32((long)((long)(base) + 0x0000002C))
+#define MVF_EDMA_RS(base) MVF_REG32((long)((long)(base) + 0x00000034))
/* Parameterized register read/write macros for multiple registers */
/* offset 0x0000_0100 - 0x0000_011f dma channel priority area */
-#define MVF_EDMA_DCHPRI(base,x) MVF_REG08((long)(base) + 0x00000100 +((x)*0x001))
+#define MVF_EDMA_DCHPRI(base,x) MVF_REG08((long)((long)(base) + 0x00000100 +((x)*0x001)))
/* offset 0x0000_1000 - 0x0000_13ff tcd area */
-#define MVF_EDMA_TCD_SADDR(base,x) MVF_REG32((long)(base) + 0x00001000 +((x)*0x020))
-#define MVF_EDMA_TCD_ATTR(base,x) MVF_REG16((long)(base) + 0x00001004 +((x)*0x020))
-#define MVF_EDMA_TCD_SOFF(base,x) MVF_REG16((long)(base) + 0x00001006 +((x)*0x020))
-#define MVF_EDMA_TCD_NBYTES(base,x) MVF_REG32((long)(base) + 0x00001008 +((x)*0x020))
-#define MVF_EDMA_TCD_SLAST(base,x) MVF_REG32((long)(base) + 0x0000100C +((x)*0x020))
-#define MVF_EDMA_TCD_DADDR(base,x) MVF_REG32((long)(base) + 0x00001010 +((x)*0x020))
-#define MVF_EDMA_TCD_CITER_ELINK(base,x) MVF_REG16((long)(base) + 0x00001014 +((x)*0x020))
-#define MVF_EDMA_TCD_CITER(base, x) MVF_REG16((long)(base) + 0x00001014 +((x)*0x020))
-#define MVF_EDMA_TCD_DOFF(base,x) MVF_REG16((long)(base) + 0x00001016 +((x)*0x020))
-#define MVF_EDMA_TCD_DLAST_SGA(base, x) MVF_REG32((long)(base) + 0x00001018 +((x)*0x020))
-#define MVF_EDMA_TCD_BITER_ELINK(base,x) MVF_REG16((long)(base) + 0x0000101C +((x)*0x020))
-#define MVF_EDMA_TCD_BITER(base, x) MVF_REG16((long)(base) + 0x0000101C +((x)*0x020))
-#define MVF_EDMA_TCD_CSR(base,x) MVF_REG16((long)(base) + 0x0000101e +((x)*0x020))
+#define MVF_EDMA_TCD_SADDR(base,x) MVF_REG32((long)((long)(base) + 0x00001000 +((x)*0x020)))
+#define MVF_EDMA_TCD_SOFF(base,x) MVF_REG16((long)((long)(base) + 0x00001004 +((x)*0x020)))
+#define MVF_EDMA_TCD_ATTR(base,x) MVF_REG16((long)((long)(base) + 0x00001006 +((x)*0x020)))
+#define MVF_EDMA_TCD_NBYTES(base,x) MVF_REG32((long)((long)(base) + 0x00001008 +((x)*0x020)))
+#define MVF_EDMA_TCD_SLAST(base,x) MVF_REG32((long)((long)(base) + 0x0000100C +((x)*0x020)))
+#define MVF_EDMA_TCD_DADDR(base,x) MVF_REG32((long)((long)(base) + 0x00001010 +((x)*0x020)))
+#define MVF_EDMA_TCD_DOFF(base,x) MVF_REG16((long)((long)(base) + 0x00001014 +((x)*0x020)))
+#define MVF_EDMA_TCD_CITER_ELINK(base,x) MVF_REG16((long)((long)(base) + 0x00001016 +((x)*0x020)))
+#define MVF_EDMA_TCD_CITER(base, x) MVF_REG16((long)((long)(base) + 0x00001016 +((x)*0x020)))
+#define MVF_EDMA_TCD_DLAST_SGA(base, x) MVF_REG32((long)((long)(base) + 0x00001018 +((x)*0x020)))
+#define MVF_EDMA_TCD_CSR(base,x) MVF_REG16((long)((long)(base) + 0x0000101c +((x)*0x020)))
+#define MVF_EDMA_TCD_BITER_ELINK(base,x) MVF_REG16((long)((long)(base) + 0x0000101e +((x)*0x020)))
+#define MVF_EDMA_TCD_BITER(base, x) MVF_REG16((long)((long)(base) + 0x0000101e +((x)*0x020)))
/* Bit definitions and macros for CR */
#define MVF_EDMA_CR_EDBG (0x00000002)
diff --git a/arch/arm/include/asm/mvf_switch.h b/arch/arm/include/asm/mvf_switch.h
index a9ddbfcd1635..d8d41c3c2f9f 100644
--- a/arch/arm/include/asm/mvf_switch.h
+++ b/arch/arm/include/asm/mvf_switch.h
@@ -49,7 +49,8 @@
#define SWITCH_EPORT_NUMBER 2
-#define MVF_MII_SWITCH_SPEED 0x09
+// 2.5MHz + HOLD time
+#define MVF_MII_SWITCH_SPEED ((0x09<<1)|((uint)0x100))
// register offset for fec
@@ -107,99 +108,87 @@ typedef struct l2switch {
unsigned long ESW_SCRATCH;
unsigned long ESW_PER;
unsigned long reserved0[1];
+ // 0x10
unsigned long ESW_VLANV;
unsigned long ESW_DBCR;
unsigned long ESW_DMCR;
unsigned long ESW_BKLR;
+ // 0x20
unsigned long ESW_BMPC;
unsigned long ESW_MODE;
unsigned long ESW_VIMSEL;
unsigned long ESW_VOMSEL;
+ // 0x30
unsigned long ESW_VIMEN;
unsigned long ESW_VID;
- /*from 0x38 0x3C*/
unsigned long esw_reserved0[2];
- unsigned long ESW_MCR;/*0x40*/
+
+ // 0x40
+ unsigned long ESW_MCR;
unsigned long ESW_EGMAP;
unsigned long ESW_INGMAP;
unsigned long ESW_INGSAL;
+
+ // 0x50
unsigned long ESW_INGSAH;
unsigned long ESW_INGDAL;
unsigned long ESW_INGDAH;
unsigned long ESW_ENGSAL;
+
+ // 0x60
unsigned long ESW_ENGSAH;
unsigned long ESW_ENGDAL;
unsigned long ESW_ENGDAH;
- unsigned long ESW_MCVAL;/*0x6C*/
+ unsigned long ESW_MCVAL;
/*from 0x70--0x7C*/
unsigned long esw_reserved1[4];
- unsigned long ESW_MMSR;/*0x80*/
+
+ // 0x80
+ unsigned long ESW_MMSR;
unsigned long ESW_LMT;
unsigned long ESW_LFC;
unsigned long ESW_PCSR;
+
+ // 0x90
unsigned long ESW_IOSR;
- unsigned long ESW_QWT;/*0x94*/
- unsigned long esw_reserved2[1];/*0x98*/
- unsigned long ESW_P0BCT;/*0x9C*/
+ unsigned long ESW_QWT;
+ unsigned long esw_reserved2[1];
+ unsigned long ESW_P0BCT;
+
+ // 0xa0
/*from 0xA0-0xB8*/
unsigned long esw_reserved3[7];
- unsigned long ESW_P0FFEN;/*0xBC*/
- /*MCF_ESW_PSNP(x) 0xFC0DC0C0+((x-1)*0x004))) 0xC0-0xDC*/
- /*#define MCF_ESW_PSNP(x) \
- (*(volatile unsigned long*)(0xFC0DC0C0+((x-1)*0x004)))*/
+ unsigned long ESW_P0FFEN;
+
+ // 0xc0-0xdf
unsigned long ESW_PSNP[8];
- /*MCF_ESW_IPSNP(x) 0xFC0DC0E0+((x-1)*0x004) 0xE0-0xFC*/
- /*#define MCF_ESW_IPSNP(x) \
- (*(volatile unsigned long*)(0xFC0DC0E0+((x-1)*0x004)))*/
+
+ // 0xe0-0xff
unsigned long ESW_IPSNP[8];
- /*port0-port2 VLAN Priority resolution map 0xFC0D_C100-C108*/
- /*#define MCF_ESW_PVRES(x) \
- (*(volatile unsigned long*)(0xFC0DC100+((x)*0x004)))*/
+
+ // 0x100-0x13f
unsigned long ESW_PVRES[3];
- /*from 0x10C-0x13C*/
unsigned long esw_reserved4[13];
- unsigned long ESW_IPRES;/*0x140*/
- /*from 0x144-0x17C*/
+
+ // 0x140
+ unsigned long ESW_IPRES;
unsigned long esw_reserved5[15];
- /*port0-port2 Priority Configuration 0xFC0D_C180-C188*/
- /*#define MCF_ESW_PRES(x) \
- (*(volatile unsigned long*)(0xFC0DC180+((x)*0x004)))*/
unsigned long ESW_PRES[3];
- /*from 0x18C-0x1FC*/
unsigned long esw_reserved6[29];
- /*port0-port2 VLAN ID 0xFC0D_C200-C208*/
- /*#define MCF_ESW_PID(x) \
- (*(volatile unsigned long*)(0xFC0DC200+((x)*0x004)))*/
unsigned long ESW_PID[3];
- /*from 0x20C-0x27C*/
unsigned long esw_reserved7[29];
- /*port0-port2 VLAN domain resolution entry 0xFC0D_C280-C2FC*/
- /*#define MCF_ESW_VRES(x) \
- (*(volatile unsigned long*)(0xFC0DC280+((x)*0x004)))*/
unsigned long ESW_VRES[32];
- unsigned long ESW_DISCN;/*0x300*/
+ unsigned long ESW_DISCN;
unsigned long ESW_DISCB;
unsigned long ESW_NDISCN;
- unsigned long ESW_NDISCB;/*0xFC0DC30C*/
- /*per port statistics 0xFC0DC310_C33C*/
- /*#define MCF_ESW_POQC(x) \
- (*(volatile unsigned long*)(0xFC0DC310+((x)*0x010)))
- #define MCF_ESW_PMVID(x) \
- (*(volatile unsigned long*)(0xFC0DC314+((x)*0x010)))
- #define MCF_ESW_PMVTAG(x) \
- (*(volatile unsigned long*)(0xFC0DC318+((x)*0x010)))
- #define MCF_ESW_PBL(x) \
- (*(volatile unsigned long*)(0xFC0DC31C+((x)*0x010)))
- */
+ unsigned long ESW_NDISCB;
esw_port_statistics_status port_statistics_status[3];
- /*from 0x340-0x400*/
unsigned long esw_reserved8[48];
- /*0xFC0DC400---0xFC0DC418*/
/*unsigned long MCF_ESW_ISR;*/
unsigned long switch_ievent; /* Interrupt event reg */
/*unsigned long MCF_ESW_IMR;*/
@@ -214,10 +203,8 @@ typedef struct l2switch {
unsigned long fec_r_des_active; /* Receive descriptor reg */
/*unsigned long MCF_ESW_TDAR;*/
unsigned long fec_x_des_active; /* Transmit descriptor reg */
- /*from 0x420-0x4FC*/
unsigned long esw_reserved9[57];
- /*0xFC0DC500---0xFC0DC508*/
unsigned long ESW_LREC0;
unsigned long ESW_LREC1;
unsigned long ESW_LSR;
@@ -234,12 +221,13 @@ typedef struct l2switchaddrtable {
#define MCF_FEC_RCR_PROM (0x00000008)
-#define MCF_FEC_RCR_RMII_MODE (0x00000100)
+#define MCF_FEC_RCR_RMII_MODE (0x00000104)
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x00003FFF)<<16)
#define MCF_FEC_RCR_CRC_FWD (0x00004000)
#define MCF_FEC_TCR_FDEN (0x00000004)
#define MCF_FEC_ECR_ETHER_EN (0x00000002)
#define MCF_FEC_ECR_ENA_1588 (0x00000010)
+#define MCF_FEC_ECR_SWAP (0x00000100)
typedef struct _eswIOCTL_PORT_CONF {
int port;
@@ -607,10 +595,14 @@ struct switch_enet_private {
/* Timer for Aging */
struct timer_list timer_aging;
int learning_irqhandle_enable;
+
+ dma_addr_t bd_dma;
+
};
struct switch_platform_private {
struct platform_device *pdev;
+ struct clk *fec0,*fec1,*l2sw;
unsigned long quirks;
int num_slots; /* Slots on controller */
diff --git a/arch/arm/mach-mvf/board-twr_vf600.c b/arch/arm/mach-mvf/board-twr_vf600.c
index bd5d7ea67ec7..6c7ac64b3470 100644
--- a/arch/arm/mach-mvf/board-twr_vf600.c
+++ b/arch/arm/mach-mvf/board-twr_vf600.c
@@ -215,10 +215,10 @@ static struct fec_platform_data fec_data __initdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
-static struct resource edma_resources[] = {
+static struct resource edma_resources0[] = {
[0] = {
.start = MVF_DMA0_BASE_ADDR,
- .end = MVF_DMA0_BASE_ADDR + 0x2000,
+ .end = MVF_DMA0_BASE_ADDR + 0x2000-1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -230,34 +230,41 @@ static struct resource edma_resources[] = {
.start = MXC_INT_DMA0_ERROR,
.end = MXC_INT_DMA0_ERROR,
.flags = IORESOURCE_IRQ,
- }
-#if 0
- [3] = {
+ },
+};
+
+static struct platform_device edma_device0 = {
+ .name = "mvf-edma",
+ .id = 0,
+ .num_resources = 3,
+ .resource = edma_resources0,
+};
+
+static struct resource edma_resources1[] = {
+ [0] = {
.start = MVF_DMA1_BASE_ADDR,
.end = MVF_DMA1_BASE_ADDR + 0x2000,
.flags = IORESOURCE_MEM,
},
- [4] = {
+ [1] = {
.start = MXC_INT_DMA1,
.end = MXC_INT_DMA1,
.flags = IORESOURCE_IRQ,
- }
- [5] = {
+ },
+ [2] = {
.start = MXC_INT_DMA1_ERROR,
.end = MXC_INT_DMA1_ERROR,
.flags = IORESOURCE_IRQ,
- }
-#endif
+ },
};
-static struct platform_device edma_device = {
+static struct platform_device edma_device1 = {
.name = "mvf-edma",
- .id = 0,
+ .id = 1,
.num_resources = 3,
- .resource = edma_resources,
+ .resource = edma_resources1,
};
-
//
// Timer resources
//
@@ -265,7 +272,7 @@ static struct platform_device edma_device = {
static struct resource pit_resources[] = {
[0] = {
.start = MVF_PIT_BASE_ADDR,
- .end = MVF_PIT_BASE_ADDR + 0x1000,
+ .end = MVF_PIT_BASE_ADDR + 0x1000-1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -281,12 +288,12 @@ static struct platform_device pit_device = {
.num_resources = 2,
.resource = pit_resources,
};
-
+#if 1
// ftm 0
static struct resource ftm0_resources[] = {
[0] = {
.start = MVF_FTM0_BASE_ADDR,
- .end = MVF_FTM0_BASE_ADDR + 0x1000,
+ .end = MVF_FTM0_BASE_ADDR + 0x1000-1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -302,12 +309,13 @@ static struct platform_device ftm0_device = {
.num_resources = 2,
.resource = ftm0_resources,
};
-
+#endif
+#if 1
// ftm 1
static struct resource ftm1_resources[] = {
[0] = {
.start = MVF_FTM1_BASE_ADDR,
- .end = MVF_FTM1_BASE_ADDR + 0x1000,
+ .end = MVF_FTM1_BASE_ADDR + 0x1000-1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -323,12 +331,13 @@ static struct platform_device ftm1_device = {
.num_resources = 2,
.resource = ftm1_resources,
};
+#endif
// pit
static struct resource lpt_resources[] = {
[0] = {
.start = MVF_LPTMR_BASE_ADDR,
- .end = MVF_LPTMR_BASE_ADDR + 0x1000,
+ .end = MVF_LPTMR_BASE_ADDR + 0x1000-1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -417,7 +426,8 @@ static void __init twr_vf600_init(void)
printk("TWR_VF600: Adding lcdif\n");
mvf_add_lcdif(&lcdif_data);
- platform_device_register(&edma_device);
+ platform_device_register(&edma_device0);
+ platform_device_register(&edma_device1);
platform_device_register(&pit_device);
platform_device_register(&ftm0_device);
platform_device_register(&ftm1_device);
diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c
index aa680c7e854c..cd7e95fc749a 100644
--- a/arch/arm/mach-mvf/clock.c
+++ b/arch/arm/mach-mvf/clock.c
@@ -4209,7 +4209,7 @@ int __init mvf_clocks_init(unsigned long sirc, unsigned long firc,
3 << MXC_CCM_CCGRx_CG9_OFFSET |
3 << MXC_CCM_CCGRx_CG12_OFFSET |
3 << MXC_CCM_CCGRx_CG13_OFFSET |
- 3 << MXC_CCM_CCGRx_CG15_OFFSET,
+ 0 << MXC_CCM_CCGRx_CG15_OFFSET, //disable OpenVG clock
MXC_CCM_CCGR8);
__raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET |
3 << MXC_CCM_CCGRx_CG1_OFFSET |
diff --git a/arch/arm/mach-mvf/irq.c b/arch/arm/mach-mvf/irq.c
index ac0a07240512..c67aceeaf74d 100644
--- a/arch/arm/mach-mvf/irq.c
+++ b/arch/arm/mach-mvf/irq.c
@@ -56,12 +56,16 @@ void mvf_init_irq(void)
struct irq_desc *desc;
unsigned int i;
void __iomem *mscm_base = MVF_IO_ADDRESS(MVF_MSCM_BASE_ADDR);
+ void __iomem *ddrmc_base = MVF_IO_ADDRESS(MVF_DDRMC_BASE_ADDR);
/* Interrupt Ruter Shared Peripheral */
for ( i = 0;i < 112;i++) {
__raw_writew(0x01,mscm_base + 0x880 + (i<<1));
}
+ /* mask DDR Interrupt */
+ __raw_writel(0x1FFFFFFF, ddrmc_base + 0x148);
+
/* start offset if global timer irq id, which is 27.
* ID table:
* Global timer, PPI -> ID27
diff --git a/arch/arm/mach-mvf/l2switch.c b/arch/arm/mach-mvf/l2switch.c
index 06599fb8cd04..f07f49f4e5be 100644
--- a/arch/arm/mach-mvf/l2switch.c
+++ b/arch/arm/mach-mvf/l2switch.c
@@ -36,6 +36,8 @@
#include <asm/traps.h>
#include <asm/mvf_switch.h>
+#include <mach/hardware.h>
+#include <asm/mach/arch.h>
#if (defined(CONFIG_SOC_IMX28) || defined(CONFIG_ARCH_MX6)) || defined(CONFIG_ARCH_MVF) \
&& defined(CONFIG_FEC_1588)
@@ -44,15 +46,14 @@
// base address
-#define FEC_ETH0 0x400D0000
-#define FEC_ETH1 0x400D1000
-#define L2SWITCH_1 0x400E8000
-
-#pragma message "need fix!!!!! L2SWITCH_ATBL"
-#define L2SWITCH_ATBL 0x400F0000
+//#define FEC_ETH0 0x400D0000
+//#define FEC_ETH1 0x400D1000
+//#define L2SWITCH_1 0x400E8000
+#define L2SWITCH_ATBL 0x400EC000
static unsigned char switch_mac_default[] = {
- 0x00, 0x04, 0x9F, 0x00, 0xB3, 0x49,
+// 0x00, 0x04, 0x9F, 0x00, 0xB3, 0x49,
+ 0xae, 0xc6, 0x09, 0x97, 0x21, 0x01,
};
static unsigned char switch_mac_addr[6];
@@ -67,60 +68,21 @@ static void switch_request_intrs(struct net_device *dev,
char *name;
unsigned short irq;
} *idp, id[] = {
- /*{ "esw_isr(EBERR)", 38 },*/
- { "esw_isr(RxBuffer)", 39 },
- { "esw_isr(RxFrame)", 40 },
- { "esw_isr(TxBuffer)", 41 },
- { "esw_isr(TxFrame)", 42 },
- { "esw_isr(QM)", 43 },
- { "esw_isr(P0OutputDiscard)", 44 },
- { "esw_isr(P1OutputDiscard)", 45 },
- { "esw_isr(P2OutputDiscard)", 46 },
- { "esw_isr(LearningRecord)", 47 },
+ { "esw_isr", MXC_INT_ENET_SWITCH},
{ NULL },
};
fep = netdev_priv(dev);
/*intrruption L2 ethernet SWITCH */
- b = 64 + 64 + 64;
/* Setup interrupt handlers. */
for (idp = id; idp->name; idp++) {
- if (request_irq(b+idp->irq,
- switch_net_irq_handler, IRQF_DISABLED,
- idp->name, irq_privatedata) != 0)
+ if (request_irq(idp->irq,
+ switch_net_irq_handler, 0,idp->name, irq_privatedata) != 0)
printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n",
- idp->name, b+idp->irq);
+ idp->name, idp->irq);
+ printk(KERN_INFO "L2 Switch: %s IRQ(%d) installed.!\n", idp->name, idp->irq);
}
-
- /* Configure RMII */
-// #if 0
-// // set in u-boot
-// MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC &
-// MCF_GPIO_PAR_FEC_FEC_MASK) |
-// MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL;
-//
-// MCF_GPIO_PAR_FEC =
-// (MCF_GPIO_PAR_FEC &
-// MCF_GPIO_PAR_FEC_FEC_MASK) |
-// MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL;
-//
-// MCF_GPIO_SRCR_FEC = 0x0F;
-//
-// MCF_GPIO_PAR_SIMP0H =
-// (MCF_GPIO_PAR_SIMP0H &
-// MCF_GPIO_PAR_SIMP0H_DAT_MASK) |
-// MCF_GPIO_PAR_SIMP0H_DAT_GPIO;
-//
-// MCF_GPIO_PDDR_G =
-// (MCF_GPIO_PDDR_G &
-// MCF_GPIO_PDDR_G4_MASK) |
-// MCF_GPIO_PDDR_G4_OUTPUT;
-//
-// MCF_GPIO_PODR_G =
-// (MCF_GPIO_PODR_G &
-// MCF_GPIO_PODR_G4_MASK);
-// #endif
}
static void switch_set_mii(struct net_device *dev)
@@ -128,32 +90,6 @@ static void switch_set_mii(struct net_device *dev)
struct switch_enet_private *fep = netdev_priv(dev);
volatile switch_t *fecp;
-// #if 0
-// fecp = fep->hwp;
-//
-// MCF_FEC_RCR0 = (MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE |
-// MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD);
-// MCF_FEC_RCR1 = (MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE |
-// MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD);
-// /* TCR */
-// MCF_FEC_TCR0 = MCF_FEC_TCR_FDEN;
-// MCF_FEC_TCR1 = MCF_FEC_TCR_FDEN;
-// /* ECR */
-// #ifdef ENHANCE_BUFFER
-// MCF_FEC_ECR0 = MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588;
-// MCF_FEC_ECR1 = MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588;
-// #else /*legac buffer*/
-// MCF_FEC_ECR0 = MCF_FEC_ECR_ETHER_EN;
-// MCF_FEC_ECR1 = MCF_FEC_ECR_ETHER_EN;
-// #endif
-// /*
-// * Set MII speed to 2.5 MHz
-// */
-// MCF_FEC_MSCR0 = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
-// MCF_FEC_MSCR1 = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
-// #endif
-//
-
writel((MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD), fep->fec[0] + FEC_R_CNTRL);
writel((MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD), fep->fec[1] + FEC_R_CNTRL);
@@ -161,11 +97,11 @@ static void switch_set_mii(struct net_device *dev)
writel(MCF_FEC_TCR_FDEN, fep->fec[1] + FEC_X_CNTRL);
#ifdef CONFIG_ENHANCED_BD
- writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588, fep->fec[0] + FEC_ECNTRL);
- writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588, fep->fec[1] + FEC_ECNTRL);
+ writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588 |MCF_FEC_ECR_SWAP, fep->fec[0] + FEC_ECNTRL);
+ writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588 |MCF_FEC_ECR_SWAP, fep->fec[1] + FEC_ECNTRL);
#else
- writel(MCF_FEC_ECR_ETHER_EN , fep->fec[0] + FEC_ECNTRL);
- writel(MCF_FEC_ECR_ETHER_EN , fep->fec[1] + FEC_ECNTRL);
+ writel(MCF_FEC_ECR_ETHER_EN |MCF_FEC_ECR_SWAP, fep->fec[0] + FEC_ECNTRL);
+ writel(MCF_FEC_ECR_ETHER_EN |MCF_FEC_ECR_SWAP, fep->fec[1] + FEC_ECNTRL);
#endif
writel( MVF_MII_SWITCH_SPEED, fep->fec[0] + FEC_MII_SPEED);
writel( MVF_MII_SWITCH_SPEED, fep->fec[1] + FEC_MII_SPEED);
@@ -241,13 +177,13 @@ static void switch_platform_flush_cache(void)
* Define the fixed address of the FEC hardware.
*/
static unsigned int switch_platform_hw[] = {
- L2SWITCH_1,
+ MVF_ETH_L2_SW_BASE_ADDR,
L2SWITCH_ATBL,
};
static unsigned int fec_platform_hw[] = {
- FEC_ETH0,
- FEC_ETH1,
+ MVF_ENET0_IEEE1588_BASE_ADDR,
+ MVF_ENET1_IEEE1588_BASE_ADDR,
};
static struct mvf_switch_platform_data mvf_switch_data = {
@@ -268,18 +204,18 @@ static struct mvf_switch_platform_data mvf_switch_data = {
// non-used-structure
static struct resource l2switch_resources[] = {
[0] = {
- .start = 0xFC0DC000,
- .end = 0xFC0DC508,
+ .start = MVF_ETH_L2_SW_BASE_ADDR,
+ .end = MVF_ETH_L2_SW_BASE_ADDR+0x1000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = (64 + 64 + 64 + 38),
- .end = (64 + 64 + 64 + 48),
+ .start = MXC_INT_ENET_SWITCH,
+ .end = MXC_INT_ENET_SWITCH,
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = 0xFC0E0000,
- .end = 0xFC0E3FFC,
+ .start = AIPS1_OFF_BASE_ADDR + 0x4F000,
+ .end = AIPS1_OFF_BASE_ADDR + 0x4F000 + 0x1000 - 1,
.flags = IORESOURCE_MEM,
},
};
@@ -314,12 +250,13 @@ static int __init param_switch_addr_setup(char *str)
{
char *end;
int i;
-
+#if 0
for (i = 0; i < 6; i++) {
switch_mac_addr[i] = str ? simple_strtoul(str, &end, 16) : 0;
if (str)
str = (*end ) ? end + 1 : end;
}
+#endif
return 0;
}
__setup("switchaddr=", param_switch_addr_setup);
diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h
index ee8ebf8a69ad..8c5aaad02d70 100644
--- a/arch/arm/plat-mxc/include/mach/mvf.h
+++ b/arch/arm/plat-mxc/include/mach/mvf.h
@@ -393,8 +393,8 @@
#define MXC_INT_GPIOB 140
#define MXC_INT_GPIOC 141
#define MXC_INT_GPIOD 142
-#define MXC_INT_GPIOE 153
-#define MXC_INT_END 153
+#define MXC_INT_GPIOE 143
+#define MXC_INT_END 143
#define MVF_INT_UART0 MXC_INT_UART0
#define MVF_INT_UART1 MXC_INT_UART1
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-14 19:36:43 +0000