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-rw-r--r--arch/m68k/platform/5272/Makefile18
-rw-r--r--arch/m68k/platform/5272/config.c176
-rw-r--r--arch/m68k/platform/5272/gpio.c81
-rw-r--r--arch/m68k/platform/5272/intc.c187
4 files changed, 462 insertions, 0 deletions
diff --git a/arch/m68k/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile
new file mode 100644
index 000000000000..34110fc14301
--- /dev/null
+++ b/arch/m68k/platform/5272/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this, which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o intc.o
+
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/5272/config.c
new file mode 100644
index 000000000000..65bb582734e1
--- /dev/null
+++ b/arch/m68k/platform/5272/config.c
@@ -0,0 +1,176 @@
+/***************************************************************************/
+
+/*
+ * linux/arch/m68knommu/platform/5272/config.c
+ *
+ * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+
+/***************************************************************************/
+
+/*
+ * Some platforms need software versions of the GPIO data registers.
+ */
+unsigned short ppdata;
+unsigned char ledbank = 0xff;
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5272_uart_platform[] = {
+ {
+ .mapbase = MCF_MBAR + MCFUART_BASE1,
+ .irq = MCF_IRQ_UART1,
+ },
+ {
+ .mapbase = MCF_MBAR + MCFUART_BASE2,
+ .irq = MCF_IRQ_UART2,
+ },
+ { },
+};
+
+static struct platform_device m5272_uart = {
+ .name = "mcfuart",
+ .id = 0,
+ .dev.platform_data = m5272_uart_platform,
+};
+
+static struct resource m5272_fec_resources[] = {
+ {
+ .start = MCF_MBAR + 0x840,
+ .end = MCF_MBAR + 0x840 + 0x1cf,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MCF_IRQ_ERX,
+ .end = MCF_IRQ_ERX,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MCF_IRQ_ETX,
+ .end = MCF_IRQ_ETX,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MCF_IRQ_ENTC,
+ .end = MCF_IRQ_ENTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m5272_fec = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m5272_fec_resources),
+ .resource = m5272_fec_resources,
+};
+
+static struct platform_device *m5272_devices[] __initdata = {
+ &m5272_uart,
+ &m5272_fec,
+};
+
+/***************************************************************************/
+
+static void __init m5272_uart_init_line(int line, int irq)
+{
+ u32 v;
+
+ if ((line >= 0) && (line < 2)) {
+ /* Enable the output lines for the serial ports */
+ v = readl(MCF_MBAR + MCFSIM_PBCNT);
+ v = (v & ~0x000000ff) | 0x00000055;
+ writel(v, MCF_MBAR + MCFSIM_PBCNT);
+
+ v = readl(MCF_MBAR + MCFSIM_PDCNT);
+ v = (v & ~0x000003fc) | 0x000002a8;
+ writel(v, MCF_MBAR + MCFSIM_PDCNT);
+ }
+}
+
+static void __init m5272_uarts_init(void)
+{
+ const int nrlines = ARRAY_SIZE(m5272_uart_platform);
+ int line;
+
+ for (line = 0; (line < nrlines); line++)
+ m5272_uart_init_line(line, m5272_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void m5272_cpu_reset(void)
+{
+ local_irq_disable();
+ /* Set watchdog to reset, and enabled */
+ __raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
+ __raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
+ __raw_writew(0, MCF_MBAR + MCFSIM_WCR);
+ for (;;)
+ /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+#if defined (CONFIG_MOD5272)
+ volatile unsigned char *pivrp;
+
+ /* Set base of device vectors to be 64 */
+ pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
+ *pivrp = 0x40;
+#endif
+
+#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
+ /* Copy command line from FLASH to local buffer... */
+ memcpy(commandp, (char *) 0xf0004000, size);
+ commandp[size-1] = 0;
+#elif defined(CONFIG_CANCam)
+ /* Copy command line from FLASH to local buffer... */
+ memcpy(commandp, (char *) 0xf0010000, size);
+ commandp[size-1] = 0;
+#endif
+
+ mach_reset = m5272_cpu_reset;
+}
+
+/***************************************************************************/
+
+/*
+ * Some 5272 based boards have the FEC ethernet diectly connected to
+ * an ethernet switch. In this case we need to use the fixed phy type,
+ * and we need to declare it early in boot.
+ */
+static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
+ .link = 1,
+ .speed = 100,
+ .duplex = 0,
+};
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+ m5272_uarts_init();
+ fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
+ platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
+ return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c
new file mode 100644
index 000000000000..57ac10a5d7f7
--- /dev/null
+++ b/arch/m68k/platform/5272/gpio.c
@@ -0,0 +1,81 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+ {
+ .gpio_chip = {
+ .label = "PA",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value,
+ .ngpio = 16,
+ },
+ .pddr = (void __iomem *) MCFSIM_PADDR,
+ .podr = (void __iomem *) MCFSIM_PADAT,
+ .ppdr = (void __iomem *) MCFSIM_PADAT,
+ },
+ {
+ .gpio_chip = {
+ .label = "PB",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value,
+ .base = 16,
+ .ngpio = 16,
+ },
+ .pddr = (void __iomem *) MCFSIM_PBDDR,
+ .podr = (void __iomem *) MCFSIM_PBDAT,
+ .ppdr = (void __iomem *) MCFSIM_PBDAT,
+ },
+ {
+ .gpio_chip = {
+ .label = "PC",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value,
+ .base = 32,
+ .ngpio = 16,
+ },
+ .pddr = (void __iomem *) MCFSIM_PCDDR,
+ .podr = (void __iomem *) MCFSIM_PCDAT,
+ .ppdr = (void __iomem *) MCFSIM_PCDAT,
+ },
+};
+
+static int __init mcf_gpio_init(void)
+{
+ unsigned i = 0;
+ while (i < ARRAY_SIZE(mcf_gpio_chips))
+ (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+ return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c
new file mode 100644
index 000000000000..969ff0a467c6
--- /dev/null
+++ b/arch/m68k/platform/5272/intc.c
@@ -0,0 +1,187 @@
+/*
+ * intc.c -- interrupt controller or ColdFire 5272 SoC
+ *
+ * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/traps.h>
+
+/*
+ * The 5272 ColdFire interrupt controller is nothing like any other
+ * ColdFire interrupt controller - it truly is completely different.
+ * Given its age it is unlikely to be used on any other ColdFire CPU.
+ */
+
+/*
+ * The masking and priproty setting of interrupts on the 5272 is done
+ * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
+ * loose mapping of vector number to register and internal bits, but
+ * a table is the easiest and quickest way to map them.
+ *
+ * Note that the external interrupts are edge triggered (unlike the
+ * internal interrupt sources which are level triggered). Which means
+ * they also need acknowledgeing via acknowledge bits.
+ */
+struct irqmap {
+ unsigned char icr;
+ unsigned char index;
+ unsigned char ack;
+};
+
+static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
+ /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
+ /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
+ /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
+ /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
+ /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
+ /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
+ /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
+ /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
+ /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
+ /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
+ /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
+ /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
+ /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
+ /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
+ /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
+ /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
+ /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
+ /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
+ /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
+ /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
+ /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
+ /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
+ /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
+ /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
+ /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
+ /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
+ /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
+ /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
+ /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
+};
+
+/*
+ * The act of masking the interrupt also has a side effect of 'ack'ing
+ * an interrupt on this irq (for the external irqs). So this mask function
+ * is also an ack_mask function.
+ */
+static void intc_irq_mask(struct irq_data *d)
+{
+ unsigned int irq = d->irq;
+
+ if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+ u32 v;
+ irq -= MCFINT_VECBASE;
+ v = 0x8 << intc_irqmap[irq].index;
+ writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+ }
+}
+
+static void intc_irq_unmask(struct irq_data *d)
+{
+ unsigned int irq = d->irq;
+
+ if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+ u32 v;
+ irq -= MCFINT_VECBASE;
+ v = 0xd << intc_irqmap[irq].index;
+ writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+ }
+}
+
+static void intc_irq_ack(struct irq_data *d)
+{
+ unsigned int irq = d->irq;
+
+ /* Only external interrupts are acked */
+ if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+ irq -= MCFINT_VECBASE;
+ if (intc_irqmap[irq].ack) {
+ u32 v;
+ v = readl(MCF_MBAR + intc_irqmap[irq].icr);
+ v &= (0x7 << intc_irqmap[irq].index);
+ v |= (0x8 << intc_irqmap[irq].index);
+ writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+ }
+ }
+}
+
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ unsigned int irq = d->irq;
+
+ if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+ irq -= MCFINT_VECBASE;
+ if (intc_irqmap[irq].ack) {
+ u32 v;
+ v = readl(MCF_MBAR + MCFSIM_PITR);
+ if (type == IRQ_TYPE_EDGE_FALLING)
+ v &= ~(0x1 << (32 - irq));
+ else
+ v |= (0x1 << (32 - irq));
+ writel(v, MCF_MBAR + MCFSIM_PITR);
+ }
+ }
+ return 0;
+}
+
+/*
+ * Simple flow handler to deal with the external edge triggered interrupts.
+ * We need to be careful with the masking/acking due to the side effects
+ * of masking an interrupt.
+ */
+static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
+{
+ get_irq_desc_chip(desc)->irq_ack(&desc->irq_data);
+ handle_simple_irq(irq, desc);
+}
+
+static struct irq_chip intc_irq_chip = {
+ .name = "CF-INTC",
+ .irq_mask = intc_irq_mask,
+ .irq_unmask = intc_irq_unmask,
+ .irq_mask_ack = intc_irq_mask,
+ .irq_ack = intc_irq_ack,
+ .irq_set_type = intc_irq_set_type,
+};
+
+void __init init_IRQ(void)
+{
+ int irq, edge;
+
+ init_vectors();
+
+ /* Mask all interrupt sources */
+ writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
+ writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
+ writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
+ writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
+
+ for (irq = 0; (irq < NR_IRQS); irq++) {
+ set_irq_chip(irq, &intc_irq_chip);
+ edge = 0;
+ if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
+ edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
+ if (edge) {
+ set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
+ set_irq_handler(irq, intc_external_irq);
+ } else {
+ set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+ set_irq_handler(irq, handle_level_irq);
+ }
+ }
+}
+
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-11 21:07:22 +0000