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path: root/drivers/serial/tegra_hsuart.c
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Diffstat (limited to 'drivers/serial/tegra_hsuart.c')
-rw-r--r--drivers/serial/tegra_hsuart.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c
index 3709162e67dd..078e2965fafc 100644
--- a/drivers/serial/tegra_hsuart.c
+++ b/drivers/serial/tegra_hsuart.c
@@ -1076,14 +1076,20 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t,
unsigned long fin_rate = rate;
int final_index = -1;
int count;
+ unsigned long error_2perc;
pdata = u->dev->platform_data;
if (!pdata || !pdata->parent_clk_count)
return fin_rate;
+ error_2perc = (rate / 50);
+
for (count = 0; count < pdata->parent_clk_count; ++count) {
parent_rate = pdata->parent_clk_list[count].fixed_clk_rate;
+ if (parent_rate < rate)
+ continue;
+
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
divider = clk_div71_get_divider(parent_rate, rate);
@@ -1097,8 +1103,12 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t,
final_index = count;
fin_err = err_rate;
fin_rate = new_rate;
+ if (fin_err < error_2perc)
+ break;
}
}
+ if (fin_err < error_2perc)
+ break;
}
#endif
/* Get the divisor by uart controller dll/dlm */
@@ -1113,8 +1123,12 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t,
final_index = count;
fin_err = err_rate;
fin_rate = parent_rate;
+ if (fin_err < error_2perc)
+ break;
}
}
+ if (fin_err < error_2perc)
+ break;
}
}