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path: root/drivers/staging/brcm80211/util/siutils.c
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Diffstat (limited to 'drivers/staging/brcm80211/util/siutils.c')
-rw-r--r--drivers/staging/brcm80211/util/siutils.c96
1 files changed, 48 insertions, 48 deletions
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index 9a2e2c0f77be..1357302ffb87 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -180,19 +180,19 @@ static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
/* get chipcommon chipstatus */
if (sii->pub.ccrev >= 11)
- sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
+ sii->pub.chipst = R_REG(&cc->chipstatus);
/* get chipcommon capabilites */
- sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
+ sii->pub.cccaps = R_REG(&cc->capabilities);
/* get chipcommon extended capabilities */
#ifndef BRCM_FULLMAC
if (sii->pub.ccrev >= 35)
- sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
+ sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
#endif
/* get pmu rev and caps */
if (sii->pub.cccaps & CC_CAP_PMU) {
- sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
+ sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
}
@@ -404,7 +404,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
* If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
* some way of recognizing them needs to be added here.
*/
- w = R_REG(osh, &cc->chipid);
+ w = R_REG(&cc->chipid);
sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
/* Might as wll fill in chip id rev & pkg */
sih->chip = w & CID_ID_MASK;
@@ -455,8 +455,8 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
if (sii->pub.ccrev >= 20) {
#endif
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- W_REG(osh, &cc->gpiopullup, 0);
- W_REG(osh, &cc->gpiopulldown, 0);
+ W_REG(&cc->gpiopullup, 0);
+ W_REG(&cc->gpiopulldown, 0);
sb_setcoreidx(sih, origidx);
#ifdef BRCM_FULLMAC
}
@@ -555,7 +555,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
* If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
* some way of recognizing them needs to be added here.
*/
- w = R_REG(osh, &cc->chipid);
+ w = R_REG(&cc->chipid);
sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
/* Might as wll fill in chip id rev & pkg */
sih->chip = w & CID_ID_MASK;
@@ -595,10 +595,10 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
uint clkdiv;
- clkdiv = R_REG(osh, &cc->clkdiv);
+ clkdiv = R_REG(&cc->clkdiv);
/* otp_clk_div is even number, 120/14 < 9mhz */
clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
- W_REG(osh, &cc->clkdiv, clkdiv);
+ W_REG(&cc->clkdiv, clkdiv);
SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
}
udelay(10);
@@ -618,8 +618,8 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
/* === NVRAM, clock is ready === */
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- W_REG(osh, &cc->gpiopullup, 0);
- W_REG(osh, &cc->gpiopulldown, 0);
+ W_REG(&cc->gpiopullup, 0);
+ W_REG(&cc->gpiopulldown, 0);
si_setcoreidx(sih, origidx);
/* PMU specific initializations */
@@ -1095,7 +1095,7 @@ static uint si_slowclk_src(si_info_t *sii)
return SCC_SS_XTAL;
} else if (sii->pub.ccrev < 10) {
cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);
- return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK;
+ return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
} else /* Insta-clock */
return SCC_SS_XTAL;
}
@@ -1109,7 +1109,7 @@ static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
/* shouldn't be here unless we've established the chip has dynamic clk control */
- ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
+ ASSERT(R_REG(&cc->capabilities) & CC_CAP_PWR_CTL);
slowclk = si_slowclk_src(sii);
if (sii->pub.ccrev < 6) {
@@ -1121,7 +1121,7 @@ static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
: (XTALMINFREQ / 32);
} else if (sii->pub.ccrev < 10) {
div = 4 *
- (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >>
+ (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
SCC_CD_SHIFT) + 1);
if (slowclk == SCC_SS_LPO)
return max_freq ? LPOMAXFREQ : LPOMINFREQ;
@@ -1135,7 +1135,7 @@ static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
ASSERT(0);
} else {
/* Chipc rev 10 is InstaClock */
- div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
+ div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
div = 4 * (div + 1);
return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
}
@@ -1165,8 +1165,8 @@ static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
- W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
- W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
+ W_REG(&cc->pll_on_delay, pll_on_delay);
+ W_REG(&cc->fref_sel_delay, fref_sel_delay);
}
/* initialize power control delay registers */
@@ -1196,7 +1196,7 @@ void si_clkctl_init(si_t *sih)
/* set all Instaclk chip ILP to 1 MHz */
if (sih->ccrev >= 10)
- SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
+ SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
(ILP_DIV_1MHZ << SYCC_CD_SHIFT));
si_clkctl_setdelay(sii, (void *)cc);
@@ -1243,7 +1243,7 @@ u16 si_clkctl_fast_pwrup_delay(si_t *sih)
ASSERT(cc != NULL);
slowminfreq = si_slowclk_freq(sii, false, cc);
- fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) +
+ fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
(slowminfreq - 1)) / slowminfreq;
done:
@@ -1394,20 +1394,20 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
if (sii->pub.ccrev < 10) {
/* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
si_clkctl_xtal(&sii->pub, XTAL, ON);
- SET_REG(sii->osh, &cc->slow_clk_ctl,
+ SET_REG(&cc->slow_clk_ctl,
(SCC_XC | SCC_FS | SCC_IP), SCC_IP);
} else if (sii->pub.ccrev < 20) {
- OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR);
+ OR_REG(&cc->system_clk_ctl, SYCC_HR);
} else {
- OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT);
+ OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
}
/* wait for the PLL */
if (PMUCTL_ENAB(&sii->pub)) {
u32 htavail = CCS_HTAVAIL;
- SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail)
+ SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
== 0), PMU_MAX_TRANSITION_DLY);
- ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
+ ASSERT(R_REG(&cc->clk_ctl_st) & htavail);
} else {
udelay(PLL_DELAY);
}
@@ -1415,20 +1415,20 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
case CLK_DYNAMIC: /* enable dynamic clock control */
if (sii->pub.ccrev < 10) {
- scc = R_REG(sii->osh, &cc->slow_clk_ctl);
+ scc = R_REG(&cc->slow_clk_ctl);
scc &= ~(SCC_FS | SCC_IP | SCC_XC);
if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
scc |= SCC_XC;
- W_REG(sii->osh, &cc->slow_clk_ctl, scc);
+ W_REG(&cc->slow_clk_ctl, scc);
/* for dynamic control, we have to release our xtal_pu "force on" */
if (scc & SCC_XC)
si_clkctl_xtal(&sii->pub, XTAL, OFF);
} else if (sii->pub.ccrev < 20) {
/* Instaclock */
- AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR);
+ AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
} else {
- AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT);
+ AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
}
break;
@@ -1583,8 +1583,8 @@ void si_sdio_init(si_t *sih)
SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));
/* enable backplane error and core interrupts */
- W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT);
- W_REG(sii->osh, &sdpregs->sbintmask,
+ W_REG(&sdpregs->hostintmask, I_SBINT);
+ W_REG(&sdpregs->sbintmask,
(I_SB_SERR | I_SB_RESPERR | (1 << idx)));
/* switch back to previous core */
@@ -1697,15 +1697,15 @@ void si_pci_setup(si_t *sih, uint coremask)
}
if (PCI(sii)) {
- OR_REG(sii->osh, &pciregs->sbtopci2,
+ OR_REG(&pciregs->sbtopci2,
(SBTOPCI_PREF | SBTOPCI_BURST));
if (sii->pub.buscorerev >= 11) {
- OR_REG(sii->osh, &pciregs->sbtopci2,
+ OR_REG(&pciregs->sbtopci2,
SBTOPCI_RC_READMULTI);
- w = R_REG(sii->osh, &pciregs->clkrun);
- W_REG(sii->osh, &pciregs->clkrun,
+ w = R_REG(&pciregs->clkrun);
+ W_REG(&pciregs->clkrun,
(w | PCI_CLKRUN_DSBL));
- w = R_REG(sii->osh, &pciregs->clkrun);
+ w = R_REG(&pciregs->clkrun);
}
/* switch back to previous core */
@@ -1747,12 +1747,12 @@ int si_pci_fixcfg(si_t *sih)
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
}
pciidx = si_coreidx(&sii->pub);
- val16 = R_REG(sii->osh, reg16);
+ val16 = R_REG(reg16);
if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
val16 =
(u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
~SRSH_PI_MASK);
- W_REG(sii->osh, reg16, val16);
+ W_REG(reg16, val16);
}
/* restore the original index */
@@ -1793,8 +1793,8 @@ socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
- W_REG(sii->osh, &regs->bankidx, bankidx);
- bankinfo = R_REG(sii->osh, &regs->bankinfo);
+ W_REG(&regs->bankidx, bankidx);
+ bankinfo = R_REG(&regs->bankinfo);
banksize =
SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
return banksize;
@@ -1829,7 +1829,7 @@ u32 si_socram_size(si_t *sih)
if (!wasup)
si_core_reset(sih, 0, 0);
corerev = si_corerev(sih);
- coreinfo = R_REG(sii->osh, &regs->coreinfo);
+ coreinfo = R_REG(&regs->coreinfo);
/* Calculate size from coreinfo based on rev */
if (corerev == 0)
@@ -1877,22 +1877,22 @@ void si_chipcontrl_epa4331(si_t *sih, bool on)
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- val = R_REG(sii->osh, &cc->chipcontrol);
+ val = R_REG(&cc->chipcontrol);
if (on) {
if (sih->chippkg == 9 || sih->chippkg == 0xb) {
/* Ext PA Controls for 4331 12x9 Package */
- W_REG(sii->osh, &cc->chipcontrol, val |
+ W_REG(&cc->chipcontrol, val |
(CCTRL4331_EXTPA_EN |
CCTRL4331_EXTPA_ON_GPIO2_5));
} else {
/* Ext PA Controls for 4331 12x12 Package */
- W_REG(sii->osh, &cc->chipcontrol,
+ W_REG(&cc->chipcontrol,
val | (CCTRL4331_EXTPA_EN));
}
} else {
val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
- W_REG(sii->osh, &cc->chipcontrol, val);
+ W_REG(&cc->chipcontrol, val);
}
si_setcoreidx(sih, origidx);
@@ -1911,8 +1911,8 @@ void si_epa_4313war(si_t *sih)
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
/* EPA Fix */
- W_REG(sii->osh, &cc->gpiocontrol,
- R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
+ W_REG(&cc->gpiocontrol,
+ R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
si_setcoreidx(sih, origidx);
}
@@ -1950,7 +1950,7 @@ bool si_is_sprom_available(si_t *sih)
sii = SI_INFO(sih);
origidx = sii->curidx;
cc = si_setcoreidx(sih, SI_CC_IDX);
- sromctrl = R_REG(sii->osh, &cc->sromcontrol);
+ sromctrl = R_REG(&cc->sromcontrol);
si_setcoreidx(sih, origidx);
return sromctrl & SRC_PRESENT;
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-24 01:59:12 +0000