diff options
Diffstat (limited to 'drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h')
| -rw-r--r-- | drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h | 50 |
1 files changed, 15 insertions, 35 deletions
diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h index 38122dbf877a..60a278136bdf 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h @@ -19,25 +19,12 @@ #ifndef CFGDEFS_ #define CFGDEFS_ -/* Maximum length of module search path. */ -#define CFG_MAXSEARCHPATHLEN 255 - -/* Maximum length of general paths. */ -#define CFG_MAXPATH 255 - /* Host Resources: */ #define CFG_MAXMEMREGISTERS 9 -#define CFG_MAXIOPORTS 20 -#define CFG_MAXIRQS 7 -#define CFG_MAXDMACHANNELS 7 /* IRQ flag */ #define CFG_IRQSHARED 0x01 /* IRQ can be shared */ -/* DSP Resources: */ -#define CFG_DSPMAXMEMTYPES 10 -#define CFG_DEFAULT_NUM_WINDOWS 1 /* We support only one window. */ - /* A platform-related device handle: */ struct cfg_devnode; @@ -47,35 +34,28 @@ struct cfg_devnode; struct cfg_hostres { u32 num_mem_windows; /* Set to default */ /* This is the base.memory */ - u32 dw_mem_base[CFG_MAXMEMREGISTERS]; /* shm virtual address */ - u32 dw_mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */ - u32 dw_mem_phys[CFG_MAXMEMREGISTERS]; /* shm Physical address */ + u32 mem_base[CFG_MAXMEMREGISTERS]; /* shm virtual address */ + u32 mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */ + u32 mem_phys[CFG_MAXMEMREGISTERS]; /* shm Physical address */ u8 birq_registers; /* IRQ Number */ u8 birq_attrib; /* IRQ Attribute */ - u32 dw_offset_for_monitor; /* The Shared memory starts from - * dw_mem_base + this offset */ + u32 offset_for_monitor; /* The Shared memory starts from + * mem_base + this offset */ /* * Info needed by NODE for allocating channels to communicate with RMS: - * dw_chnl_offset: Offset of RMS channels. Lower channels are + * chnl_offset: Offset of RMS channels. Lower channels are * reserved. - * dw_chnl_buf_size: Size of channel buffer to send to RMS - * dw_num_chnls: Total number of channels + * chnl_buf_size: Size of channel buffer to send to RMS + * num_chnls: Total number of channels * (including reserved). */ - u32 dw_chnl_offset; - u32 dw_chnl_buf_size; - u32 dw_num_chnls; - void __iomem *dw_per_base; - u32 dw_per_pm_base; - u32 dw_core_pm_base; - void __iomem *dw_dmmu_base; - void __iomem *dw_sys_ctrl_base; -}; - -struct cfg_dspmemdesc { - u32 mem_type; /* Type of memory. */ - u32 ul_min; /* Minimum amount of memory of this type. */ - u32 ul_max; /* Maximum amount of memory of this type. */ + u32 chnl_offset; + u32 chnl_buf_size; + u32 num_chnls; + void __iomem *per_base; + u32 per_pm_base; + u32 core_pm_base; + void __iomem *dmmu_base; }; #endif /* CFGDEFS_ */ |