diff options
Diffstat (limited to 'drivers/usb/gadget/fsl_usb2_udc.h')
| -rw-r--r-- | drivers/usb/gadget/fsl_usb2_udc.h | 219 |
1 files changed, 198 insertions, 21 deletions
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h index 1d51be83fda8..814214f1c648 100644 --- a/drivers/usb/gadget/fsl_usb2_udc.h +++ b/drivers/usb/gadget/fsl_usb2_udc.h @@ -9,6 +9,7 @@ #define USB_MAX_CTRL_PAYLOAD 64 #define USB_DR_SYS_OFFSET 0x400 +#ifdef CONFIG_ARCH_TEGRA_2x_SOC /* USB DR device mode registers (Little Endian) */ struct usb_dr_device { /* Capability register */ @@ -82,8 +83,106 @@ struct usb_dr_host { u32 endptcomplete; /* Endpoint Complete Register */ u32 endptctrl[6]; /* Endpoint Control Registers */ }; +#else +/* Tegra3 support. + * Following changes have been done in tegra3 USB regs: + * 1. Registers usbcmd to portsc1 have been shifted up by 16 bytes. + * 2. Registers otgsc and usbmode have been shifted down by 80 bytes. + * 3. hostpc1devlc register has been added at offset 0x1b4(436). + * 4. Registers endptsetupstat to endptctrl have shifted down by 92 bytes. + */ + +/* USB DR device mode registers (Little Endian) */ +struct usb_dr_device { + /* Capability register */ + u8 res1[256]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u8 res2[20]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u8 res3[8]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u8 res4[4]; + u32 deviceaddr; /* Device Address */ + u32 endpointlistaddr; /* Endpoint List Address Register */ + u8 res5[4]; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u8 res6[24]; + u32 configflag; /* Configure Flag Register */ + u32 portsc1; /* Port 1 Status and Control Register */ + u8 res7[60]; + u32 hostpc1devlc; /* Usb LPM Behavior and Control Register */ + u8 res8[60]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u8 res9[12]; + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[6]; /* Endpoint Control Registers */ +}; + + /* USB DR host mode registers (Little Endian) */ +struct usb_dr_host { + /* Capability register */ + u8 res1[256]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u8 res2[20]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u8 res3[8]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u8 res4[4]; + u32 periodiclistbase; /* Periodic Frame List Base Address Register */ + u32 asynclistaddr; /* Current Asynchronous List Address Register */ + u8 res5[4]; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u8 res6[24]; + u32 configflag; /* Configure Flag Register */ + u32 portsc1; /* Port 1 Status and Control Register */ + u8 res7[60]; + u32 hostpc1devlc; /* Usb LPM Behavior and Control Register */ + u8 res8[60]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u8 res9[12]; + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[6]; /* Endpoint Control Registers */ +}; +#endif // ifdef CONFIG_ARCH_TEGRA_2x_SOC /* non-EHCI USB system interface registers (Big Endian) */ +#ifdef CONFIG_ARCH_TEGRA +struct usb_sys_interface { + u32 suspend_ctrl; + u32 vbus_sensors; + u32 vbus_wakeup; + u32 vbus_alt_status; + u32 legacy_ctrl; +}; +#else struct usb_sys_interface { u32 snoop1; u32 snoop2; @@ -93,6 +192,7 @@ struct usb_sys_interface { u8 res[236]; u32 control; /* General Purpose Control Register */ }; +#endif /* ep0 transfer state */ #define WAIT_FOR_SETUP 0 @@ -198,11 +298,59 @@ struct usb_sys_interface { #define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000 #define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000 #define PORTSCX_PHY_LOW_POWER_SPD 0x00800000 + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC #define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000 #define PORTSCX_PORT_SPEED_MASK 0x0C000000 #define PORTSCX_PORT_WIDTH 0x10000000 #define PORTSCX_PHY_TYPE_SEL 0xC0000000 +/* bit 27-26 are port speed */ +#define PORTSCX_PORT_SPEED_FULL 0x00000000 +#define PORTSCX_PORT_SPEED_LOW 0x04000000 +#define PORTSCX_PORT_SPEED_HIGH 0x08000000 +#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 +#define PORTSCX_SPEED_BIT_POS 26 + +/* bit 28 is parallel transceiver width for UTMI interface */ +#define PORTSCX_PTW 0x10000000 +#define PORTSCX_PTW_8BIT 0x00000000 +#define PORTSCX_PTW_16BIT 0x10000000 + +/* bit 31-30 are port transceiver select */ +#define PORTSCX_PTS_UTMI 0x00000000 +#define PORTSCX_PTS_ULPI 0x80000000 +#define PORTSCX_PTS_FSLS 0xC0000000 +#define PORTSCX_PTS_BIT_POS 30 +#else +/* In tegra3 the following fields have moved to new HOSTPC1_DEVLC reg and + * their offsets have changed. + * Keeping the name of bit masks same as before (PORTSCX_*) to have + * minimum changes to code */ +#define PORTSCX_PORT_FORCE_FULL_SPEED 0x00800000 +#define PORTSCX_PORT_SPEED_MASK 0x06000000 +#define PORTSCX_PORT_WIDTH 0x08000000 +#define PORTSCX_PHY_TYPE_SEL 0xE0000000 + +/* bit 26-25 are port speed */ +#define PORTSCX_PORT_SPEED_FULL 0x00000000 +#define PORTSCX_PORT_SPEED_LOW 0x02000000 +#define PORTSCX_PORT_SPEED_HIGH 0x04000000 +#define PORTSCX_PORT_SPEED_UNDEF 0x06000000 +#define PORTSCX_SPEED_BIT_POS 25 + +/* bit 27 is parallel transceiver width for UTMI interface */ +#define PORTSCX_PTW 0x08000000 +#define PORTSCX_PTW_8BIT 0x00000000 +#define PORTSCX_PTW_16BIT 0x08000000 + +/* bit 31-29 are port transceiver select */ +#define PORTSCX_PTS_UTMI 0x00000000 +#define PORTSCX_PTS_ULPI 0x40000000 +#define PORTSCX_PTS_FSLS 0x60000000 +#define PORTSCX_PTS_BIT_POS 29 +#endif + /* bit 11-10 are line status */ #define PORTSCX_LINE_STATUS_SE0 0x00000000 #define PORTSCX_LINE_STATUS_JSTATE 0x00000400 @@ -226,24 +374,6 @@ struct usb_sys_interface { #define PORTSCX_PTC_FORCE_EN 0x00050000 #define PORTSCX_PTC_BIT_POS 16 -/* bit 27-26 are port speed */ -#define PORTSCX_PORT_SPEED_FULL 0x00000000 -#define PORTSCX_PORT_SPEED_LOW 0x04000000 -#define PORTSCX_PORT_SPEED_HIGH 0x08000000 -#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 -#define PORTSCX_SPEED_BIT_POS 26 - -/* bit 28 is parallel transceiver width for UTMI interface */ -#define PORTSCX_PTW 0x10000000 -#define PORTSCX_PTW_8BIT 0x00000000 -#define PORTSCX_PTW_16BIT 0x10000000 - -/* bit 31-30 are port transceiver select */ -#define PORTSCX_PTS_UTMI 0x00000000 -#define PORTSCX_PTS_ULPI 0x80000000 -#define PORTSCX_PTS_FSLS 0xC0000000 -#define PORTSCX_PTS_BIT_POS 30 - /* otgsc Register Bit Masks */ #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 #define OTGSC_CTRL_VUSB_CHARGE 0x00000002 @@ -420,12 +550,25 @@ struct ep_td_struct { DTD_STATUS_DATA_BUFF_ERR | \ DTD_STATUS_TRANSACTION_ERR) /* Alignment requirements; must be a power of two */ +#if defined(CONFIG_ARCH_TEGRA) +#define DTD_ALIGNMENT 0x80 +#else #define DTD_ALIGNMENT 0x20 +#endif #define QH_ALIGNMENT 2048 +#define QH_OFFSET 0x1000 /* Controller dma boundary */ #define UDC_DMA_BOUNDARY 0x1000 +#define USB_SYS_VBUS_ASESSION_INT_EN 0x10000 +#define USB_SYS_VBUS_ASESSION_CHANGED 0x20000 +#define USB_SYS_VBUS_ASESSION 0x40000 +#define USB_SYS_VBUS_WAKEUP_ENABLE 0x40000000 +#define USB_SYS_VBUS_WAKEUP_INT_ENABLE 0x100 +#define USB_SYS_VBUS_WAKEUP_INT_STATUS 0x200 +#define USB_SYS_VBUS_STATUS 0x400 +#define USB_SYS_ID_PIN_STATUS (0x4) /*-------------------------------------------------------------------------*/ /* ### driver private data @@ -476,8 +619,8 @@ struct fsl_udc { unsigned vbus_active:1; unsigned stopped:1; unsigned remote_wakeup:1; - unsigned already_stopped:1; unsigned big_endian_desc:1; + unsigned selfpowered:1; struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ struct fsl_req *status_req; /* ep0 status request */ @@ -488,13 +631,18 @@ struct fsl_udc { dma_addr_t ep_qh_dma; /* dma address of QH */ u32 max_pipes; /* Device max pipes */ - u32 bus_reset; /* Device is bus resetting */ u32 resume_state; /* USB state to resume */ u32 usb_state; /* USB current state */ u32 ep0_state; /* Endpoint zero state */ u32 ep0_dir; /* Endpoint zero direction: can be USB_DIR_IN or USB_DIR_OUT */ u8 device_address; /* Device USB address */ + struct delayed_work work; /* delayed work for charger detection */ + struct regulator *vbus_regulator; /* regulator for drawing VBUS */ + u32 current_limit; + struct work_struct charger_work; /* work for setting regulator current limit */ + struct work_struct boost_cpufreq_work; /* work for boosting cpu frequency */ + struct work_struct irq_work; /* irq work for controlling the usb power*/ }; /*-------------------------------------------------------------------------*/ @@ -570,10 +718,17 @@ static void dump_msg(const char *label, const u8 * buf, unsigned int length) #define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) struct platform_device; -#ifdef CONFIG_ARCH_MXC +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_TEGRA) int fsl_udc_clk_init(struct platform_device *pdev); void fsl_udc_clk_finalize(struct platform_device *pdev); void fsl_udc_clk_release(void); +void fsl_udc_clk_suspend(bool is_dpd); +void fsl_udc_clk_resume(bool is_dpd); +void fsl_udc_clk_enable(void); +void fsl_udc_clk_disable(void); +bool fsl_udc_charger_detect(void); +void fsl_udc_dtd_prepare(void); +void fsl_udc_ep_barrier(void); #else static inline int fsl_udc_clk_init(struct platform_device *pdev) { @@ -585,6 +740,28 @@ static inline void fsl_udc_clk_finalize(struct platform_device *pdev) static inline void fsl_udc_clk_release(void) { } +static inline void fsl_udc_clk_suspend(bool is_dpd) +{ +} +static inline void fsl_udc_clk_resume(bool is_dpd) +{ +} +void fsl_udc_clk_enable(void) +{ +} +void fsl_udc_clk_disable(void) +{ +} +static inline bool fsl_udc_charger_detect(void) +{ + return false; +} +void fsl_udc_dtd_prepare(void) +{ +} +void fsl_udc_ep_barrier(void) +{ +} #endif #endif |