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path: root/drivers/video/tegra/dc/bandwidth.c
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Diffstat (limited to 'drivers/video/tegra/dc/bandwidth.c')
-rw-r--r--drivers/video/tegra/dc/bandwidth.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/video/tegra/dc/bandwidth.c b/drivers/video/tegra/dc/bandwidth.c
index ed5bf6e06948..5d0e5ee68bd6 100644
--- a/drivers/video/tegra/dc/bandwidth.c
+++ b/drivers/video/tegra/dc/bandwidth.c
@@ -32,8 +32,7 @@ static int use_dynamic_emc = 1;
module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
-/* uses the larger of w->bandwidth or w->new_bandwidth, and copies
- * w->new_bandwidth into w->bandwidth */
+/* uses the larger of w->bandwidth or w->new_bandwidth */
static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
struct tegra_dc_win *w)
{
@@ -73,8 +72,6 @@ static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
if (w->idx == 1)
tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
#endif
-
- w->bandwidth = w->new_bandwidth;
}
static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
@@ -220,12 +217,13 @@ void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
* dc->new_emc_clk_rate into dc->emc_clk_rate.
* calling this function both before and after a flip is sufficient to select
* the best possible frequency and latency allowance.
+ * set use_new to true to force dc->new_emc_clk_rate programming.
*/
-void tegra_dc_program_bandwidth(struct tegra_dc *dc)
+void tegra_dc_program_bandwidth(struct tegra_dc *dc, bool use_new)
{
unsigned i;
- if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
+ if (use_new || dc->emc_clk_rate != dc->new_emc_clk_rate) {
/* going from 0 to non-zero */
if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk))
clk_enable(dc->emc_clk);
@@ -242,8 +240,10 @@ void tegra_dc_program_bandwidth(struct tegra_dc *dc)
for (i = 0; i < DC_N_WINDOWS; i++) {
struct tegra_dc_win *w = &dc->windows[i];
- if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
+ if ((use_new || w->bandwidth != w->new_bandwidth) &&
+ w->new_bandwidth != 0)
tegra_dc_set_latency_allowance(dc, w);
+ w->bandwidth = w->new_bandwidth;
trace_printk("%s:win%u bandwidth=%d\n", dc->ndev->name, w->idx,
w->bandwidth);
}