diff options
Diffstat (limited to 'drivers/video/tegra/host/gr3d/gr3d_t30.c')
| -rw-r--r-- | drivers/video/tegra/host/gr3d/gr3d_t30.c | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.c b/drivers/video/tegra/host/gr3d/gr3d_t30.c index c35fea2f3ac2..664708c7fc80 100644 --- a/drivers/video/tegra/host/gr3d/gr3d_t30.c +++ b/drivers/video/tegra/host/gr3d/gr3d_t30.c @@ -125,6 +125,16 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma) nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0), NVHOST_OPCODE_NOOP); + /* invalidate the FDC to prevent cache-coherency issues across GPUs + note that we assume FDC_CONTROL_0 is left in the reset state by all + contexts. the invalidate bit will clear itself, so the register + should be unchanged after this */ + nvhost_cdma_push(cdma, + nvhost_opcode_imm(AR3D_FDC_CONTROL_0, + AR3D_FDC_CONTROL_0_RESET_VAL + | AR3D_FDC_CONTROL_0_INVALIDATE), + NVHOST_OPCODE_NOOP); + /* set register set 0 and 1 register read memory output addresses, and send their reads to memory */ @@ -132,7 +142,7 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma) nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 2), nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1)); nvhost_cdma_push(cdma, - nvhost_opcode_nonincr(0x904, 1), + nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1), ctx->restore_phys + restore_set1_offset * 4); nvhost_cdma_push(cdma, @@ -150,7 +160,7 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma) p->save_phys); } -static void __init save_begin_v1(struct host1x_hwctx_handler *p, u32 *ptr) +static void save_begin_v1(struct host1x_hwctx_handler *p, u32 *ptr) { ptr[0] = nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_DATA, RESTORE_BEGIN_SIZE); @@ -158,7 +168,7 @@ static void __init save_begin_v1(struct host1x_hwctx_handler *p, u32 *ptr) ptr += RESTORE_BEGIN_SIZE; } -static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count) +static void save_direct_v1(u32 *ptr, u32 start_reg, u32 count) { ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, AR3D_DW_MEMORY_OUTPUT_DATA, 1); @@ -172,7 +182,7 @@ static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count) ptr[3] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count); } -static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset, +static void save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset, u32 data_reg, u32 count) { ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0); @@ -189,7 +199,7 @@ static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset, ptr[5] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count); } -static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr) +static void save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr) { /* write end of restore buffer */ ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, @@ -224,7 +234,7 @@ static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr) -static void __init setup_save_regs(struct save_info *info, +static void setup_save_regs(struct save_info *info, const struct hwctx_reginfo *regs, unsigned int nr_regs) { @@ -282,7 +292,7 @@ static void __init setup_save_regs(struct save_info *info, info->restore_count = restore_count; } -static void __init switch_gpu(struct save_info *info, +static void switch_gpu(struct save_info *info, unsigned int save_src_set, u32 save_dest_sets, u32 restore_dest_sets) @@ -303,7 +313,7 @@ static void __init switch_gpu(struct save_info *info, info->restore_count += 1; } -static void __init setup_save(struct host1x_hwctx_handler *p, u32 *ptr) +static void setup_save(struct host1x_hwctx_handler *p, u32 *ptr) { struct save_info info = { ptr, @@ -399,7 +409,7 @@ struct nvhost_hwctx_handler *nvhost_gr3d_t30_ctxhandler_init( p->save_buf = mem_op().alloc(memmgr, p->save_size * 4, 32, mem_mgr_flag_write_combine); - if (IS_ERR(p->save_buf)) { + if (IS_ERR_OR_NULL(p->save_buf)) { p->save_buf = NULL; return NULL; } |