diff options
Diffstat (limited to 'include')
70 files changed, 6013 insertions, 160 deletions
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index db22d136ad08..ff4d370a4e89 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -473,7 +473,7 @@ #ifdef CONFIG_CONSTRUCTORS #define KERNEL_CTORS() . = ALIGN(8); \ VMLINUX_SYMBOL(__ctors_start) = .; \ - *(.ctors) \ + *(CONFIG_GCOV_CTORS) \ VMLINUX_SYMBOL(__ctors_end) = .; #else #define KERNEL_CTORS() diff --git a/include/drm/drm_fixed.h b/include/drm/drm_fixed.h index 4a08a664ff1f..0ead502e17d2 100644 --- a/include/drm/drm_fixed.h +++ b/include/drm/drm_fixed.h @@ -37,6 +37,7 @@ typedef union dfixed { #define dfixed_init(A) { .full = dfixed_const((A)) } #define dfixed_init_half(A) { .full = dfixed_const_half((A)) } #define dfixed_trunc(A) ((A).full >> 12) +#define dfixed_frac(A) ((A).full & ((1 << 12) - 1)) static inline u32 dfixed_floor(fixed20_12 A) { diff --git a/include/linux/adt7461.h b/include/linux/adt7461.h new file mode 100644 index 000000000000..7307395ba7c8 --- /dev/null +++ b/include/linux/adt7461.h @@ -0,0 +1,41 @@ +/* + * include/linux/adt8461.h + * + * ADT7461, temperature monitoring device from ON Semiconductors + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_ADT7461_H +#define _LINUX_ADT7461_H + +#include <linux/types.h> + +struct adt7461_platform_data { + bool supported_hwrev; + bool ext_range; + bool therm2; + u8 conv_rate; + u8 offset; + u8 hysteresis; + u8 shutdown_ext_limit; + u8 shutdown_local_limit; + u8 throttling_ext_limit; + void (*alarm_fn)(bool raised); +}; + +#endif /* _LINUX_ADT7461_H */ diff --git a/include/linux/bq27x00.h b/include/linux/bq27x00.h new file mode 100644 index 000000000000..b95cd2035238 --- /dev/null +++ b/include/linux/bq27x00.h @@ -0,0 +1,30 @@ +/* + * include/linux/bq27x00.h + * + * BQ27x00 battery driver + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_BQ27x00_H +#define _LINUX_BQ27x00_H + +struct bq27x00_platform_data { + int ac_persent_gpio; +}; + +#endif /* _LINUX_BQ27x00_H */ diff --git a/include/linux/fb.h b/include/linux/fb.h index f0532fca9cff..bb565a4c2e1c 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -231,6 +231,15 @@ struct fb_bitfield { #define FB_FLAG_PIXEL_REPEAT 256 /* + * Stereo modes + */ +#define FB_VMODE_STEREO_NONE 0x00000000 /* not stereo */ +#define FB_VMODE_STEREO_FRAME_PACK 0x01000000 /* frame packing */ +#define FB_VMODE_STEREO_TOP_BOTTOM 0x02000000 /* top-bottom */ +#define FB_VMODE_STEREO_LEFT_RIGHT 0x04000000 /* left-right */ +#define FB_VMODE_STEREO_MASK 0xFF000000 + +/* * Display rotation support */ #define FB_ROTATE_UR 0 diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index fffdf00f87b9..1962102d132e 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -58,6 +58,13 @@ enum fsl_usb2_phy_modes { FSL_USB2_PHY_SERIAL, }; +enum fsl_usb2_phy_types { + FSL_USB2_PHY_TYPE_UTMIP = 1, + FSL_USB2_PHY_TYPE_ULPI = 2, + FSL_USB2_PHY_TYPE_HSIC = 3, + FSL_USB2_PHY_TYPE_ICUSB = 4, +}; + struct clk; struct platform_device; @@ -72,7 +79,6 @@ struct fsl_usb2_platform_data { void (*exit)(struct platform_device *); void __iomem *regs; /* ioremap'd register base */ struct clk *clk; - unsigned power_budget; /* hcd->power_budget */ unsigned big_endian_mmio:1; unsigned big_endian_desc:1; unsigned es:1; /* need USBMODE:ES */ @@ -95,6 +101,9 @@ struct fsl_usb2_platform_data { u32 pm_configured_flag; u32 pm_portsc; u32 pm_usbgenctrl; + + void *phy_config; + enum fsl_usb2_phy_types usb_phy_type; }; /* Flags in fsl_usb2_mph_platform_data */ diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h index b5ca4b2c08ec..d944b2ee3d3b 100644 --- a/include/linux/gpio_keys.h +++ b/include/linux/gpio_keys.h @@ -23,6 +23,7 @@ struct gpio_keys_platform_data { int (*enable)(struct device *dev); void (*disable)(struct device *dev); const char *name; /* input device name */ + int (*wakeup_key)(void); }; #endif diff --git a/include/linux/gpio_scrollwheel.h b/include/linux/gpio_scrollwheel.h new file mode 100644 index 000000000000..33d17a0199ea --- /dev/null +++ b/include/linux/gpio_scrollwheel.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2010, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _GPIO_SCROLLWHEEL_H +#define _GPIO_SCROLLWHEEL_H + +#define GPIO_SCROLLWHEEL_PIN_ONOFF 0 +#define GPIO_SCROLLWHEEL_PIN_PRESS 1 +#define GPIO_SCROLLWHEEL_PIN_ROT1 2 +#define GPIO_SCROLLWHEEL_PIN_ROT2 3 +#define GPIO_SCROLLWHEEL_PIN_MAX 4 + +struct gpio_scrollwheel_button { + /* Configuration parameters */ + int pinaction; /* GPIO_SCROLLWHEEL_PIN_* */ + int gpio; + char *desc; + int active_low; + int debounce_interval; /* debounce ticks interval in msecs */ +}; + +struct gpio_scrollwheel_platform_data { + struct gpio_scrollwheel_button *buttons; + int nbuttons; + unsigned int rep:1; /* enable input subsystem auto repeat */ + int (*enable)(struct device *dev); + void (*disable)(struct device *dev); +}; + +#endif + diff --git a/include/linux/i2c-slave.h b/include/linux/i2c-slave.h new file mode 100755 index 000000000000..34df64f73f6f --- /dev/null +++ b/include/linux/i2c-slave.h @@ -0,0 +1,259 @@ +/* + * i2c-slave.h - definitions for the i2c-slave-bus interface + * + * Copyright (c) 2009-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/* ------------------------------------------------------------------------- */ + +#ifndef _LINUX_I2C_SLAVE_H +#define _LINUX_I2C_SLAVE_H + +#include <linux/types.h> +#ifdef __KERNEL__ +/* --- General options ------------------------------------------------ */ + +struct i2c_client; +struct i2c_slave_algorithm; +struct i2c_slave_adapter; +#if defined(CONFIG_I2C_SLAVE) && defined(CONFIG_I2C) + +/** + * i2c_slave_send - Sends data to master. When master issues a read cycle, the + * data is sent by the slave. + * This function copies the client data into the slave tx buffer and return to + * client. This is not a blocking call. Data will be sent to master later once + * slave got the master-ready cycle transfer. + * if there is no sufficient space to write the client buffer, it will return + * error. it will not write partial data. + * @client: Handle to i2c-slave client. + * @buf: Data that will be written to the master + * @count: How many bytes to write. + * + * Returns negative errno, or else the number of bytes written. + */ +extern int i2c_slave_send(struct i2c_client *client, const char *buf, + int count); + +/** + * i2c_slave_get_tx_status - Get amount of data available in tx buffer. If there + * is still data in tx buffer then wait for given time to transfer complete + * for a give timeout. + * @client: Handle to i2c-slave client. + * @timeout_ms: Time to wait for transfer to complete. + * + * Returns negative errno, or else the number of bytes remaining in tx buffer. + */ +extern int i2c_slave_get_tx_status(struct i2c_client *client, int timeout_ms); + +/** + * i2c_slave_recv - Receive data from master. The data received from master is + * stored on slave rx buffer. When this api will be called, the data will be + * copied from the slave rx buffer to client buffer. If requested amount (count) + * of data is not available then it will wait for either min_count to be receive + * or timeout whatever first. + * + * if timeout_ms = 0, then wait for min_count data to be read. + * if timoue_ms non zero then wait for the data till timeout happen. + * @client: Handle to i2c-slave client. + * @buf: Data that will be read from the master + * @count: How many bytes to read. + * @min_count: Block till read min_count of data. + * @timeout_ms: Time to wait for read to be complete. + * + * Returns negative errno, or else the number of bytes read. + */ +extern int i2c_slave_recv(struct i2c_client *client, char *buf, int count, + int min_count, int timeout_ms); + +/** + * i2c_slave_start - Start the i2c slave to receive/transmit data. + * After this i2c controller starts responding master. + * The dummy-char will send to master if there is no data to send on slave tx + * buffer. + * @client: Handle to i2c-slave client. + * @dummy_char: Data which will be send to master if there is no data to be send + * in slave tx buffer. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_slave_start(struct i2c_client *client, unsigned char dummy_char); + +/** + * i2c_slave_stop - Stop slave to receive/transmit data. + * After this i2c controller stops responding master. + * @client: Handle to i2c-slave client. + * @is_buffer_clear: Reset the tx and rx slave buffer or not. + */ +extern void i2c_slave_stop(struct i2c_client *client, int is_buffer_clear); + +/** + * i2c_slave_flush_buffer - Flush the receive and transmit buffer. + * @client: Handle to i2c-slave client. + * @is_flush_tx_buffer: Reset the tx slave buffer or not. + * @is_flush_rx_buffer: Reset the rx slave buffer or not. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_slave_flush_buffer(struct i2c_client *client, + int is_flush_tx_buffer, int is_flush_rx_buffer); + +/** + * i2c_slave_get_nack_cycle - Get the number of master read cycle on which + * dummy char sent. This is the way to find that how much cycle slave sent the + * NACK packet. + * + * @client: Handle to i2c-slave client. + * @is_cout_reset: Reset the nack count or not. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_slave_get_nack_cycle(struct i2c_client *client, + int is_cout_reset); + + +/** + * i2c_add_slave_adapter - Add slave adapter. + * + * @slv_adap: Slave adapter. + * @force_nr: Adapter number. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_add_slave_adapter(struct i2c_slave_adapter *slv_adap, + bool force_nr); + +/** + * i2c_del_slave_adapter - Delete slave adapter. + * + * @slv_adap: Slave adapter. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_del_slave_adapter(struct i2c_slave_adapter *slv_adap); + +#endif /* I2C_SLAVE */ + +/* + * i2c_slave_adapter is the structure used to identify a physical i2c bus along + * with the access algorithms necessary to access it. + */ +struct i2c_slave_adapter { + struct module *owner; + unsigned int id; + unsigned int class; /* classes to allow probing for */ + /* the algorithm to access the i2c-slave bus */ + const struct i2c_slave_algorithm *slv_algo; + void *algo_data; + void *parent_data; + + /* data fields that are valid for all devices */ + u8 level; /* nesting level for lockdep */ + struct mutex bus_lock; + + int timeout; /* in jiffies */ + int retries; + struct device *dev; /* the adapter device */ + struct device *parent_dev; /* the adapter device */ + + int nr; + char name[48]; + struct completion dev_released; +}; + +static inline void *i2c_get_slave_adapdata(const struct i2c_slave_adapter *dev) +{ + return dev_get_drvdata(dev->dev); +} + +static inline void i2c_set_slave_adapdata(struct i2c_slave_adapter *dev, + void *data) +{ + dev_set_drvdata(dev->dev, data); +} + +/* + * The following struct are for those who like to implement new i2c slave + * bus drivers: + * i2c_slave_algorithm is the interface to a class of hardware solutions which + * can be addressed using the same bus algorithms. + */ +struct i2c_slave_algorithm { + /* Start the slave to receive/transmit data. + * The dummy-char will send to master if there is no data to send on + * slave tx buffer. + */ + int (*slave_start)(struct i2c_slave_adapter *slv_adap, int addr, + int is_ten_bit_addr, unsigned char dummy_char); + + /* Stop slave to receive/transmit data. + * Required information to reset the slave rx and tx buffer to reset + * or not. + */ + void (*slave_stop)(struct i2c_slave_adapter *slv_adap, + int is_buffer_clear); + + /* + * Send data to master. The data will be copied on the slave tx buffer + * and will send to master once master initiates the master-read cycle. + * Function will return immediately once the buffer copied into slave + * tx buffer. + * Client will not wait till data is sent to master. + * This function will not copy data partially. If sufficient space is + * not available, it will return error. + */ + int (*slave_send)(struct i2c_slave_adapter *slv_adap, const char *buf, + int count); + + /* + * Get amount of data available in tx buffer. If there is still data in + * tx buffer wait for given time to get slave tx buffer emptied. + * returns number of data available in slave tx buffer. + */ + int (*slave_get_tx_status)(struct i2c_slave_adapter *slv_adap, + int timeout_ms); + + /* + * Receive data to master. The data received from master is stored on + * slave rx buffer. When this api will be called, the data will be + * coped from the slave rx buffer to client buffer. If requested (count) + * data is not available then it will wait for either min_count to be + * receive or timeout whatever first. + * + * if timeout_ms = 0, then wait for min_count data to be read. + * if timoue_ms non zero then wait for the data till timeout happen. + * returns number of bytes read as positive integer otherwise error. + */ + int (*slave_recv)(struct i2c_slave_adapter *slv_adap, char *buf, + int count, int min_count, int timeout_ms); + + /* Flush the receive and transmit buffer. + */ + int (*slave_flush_buffer)(struct i2c_slave_adapter *slv_adap, + int is_flush_tx_buffer, int is_flush_rx_buffer); + + /* Get the number of dummy char cycle. + * Get the number of master read cycle on which dummy character has + * been sent. + * This can be treat as NACK cycle from slave side. + * Pass option whether count need to be reset or not. + */ + int (*slave_get_nack_cycle)(struct i2c_slave_adapter *slv_adap, + int is_cout_reset); +}; +#endif /* __KERNEL__ */ +#endif /* _LINUX_I2C_SLAVE_H */ diff --git a/include/linux/i2c-tegra.h b/include/linux/i2c-tegra.h index 6123502b8ddd..90dcddc52f29 100644 --- a/include/linux/i2c-tegra.h +++ b/include/linux/i2c-tegra.h @@ -4,6 +4,8 @@ * Copyright (C) 2010 Google, Inc. * Author: Colin Cross <ccross@android.com> * + * Copyright (C) 2010-2011 NVIDIA Corporation + * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. @@ -29,6 +31,22 @@ struct tegra_i2c_platform_data { int bus_mux_len[TEGRA_I2C_MAX_BUS]; unsigned long bus_clk_rate[TEGRA_I2C_MAX_BUS]; bool is_dvc; + bool is_clkon_always; + int retries; + int timeout; /* in jiffies */ + u16 slave_addr; + int scl_gpio[TEGRA_I2C_MAX_BUS]; + int sda_gpio[TEGRA_I2C_MAX_BUS]; + int (*arb_recovery)(int scl_gpio, int sda_gpio); +}; + +struct tegra_i2c_slave_platform_data { + int adapter_nr; + const struct tegra_pingroup_config *pinmux; + int bus_mux_len; + unsigned long bus_clk_rate; + int max_rx_buffer_size; + int max_tx_buffer_size; }; #endif /* _LINUX_I2C_TEGRA_H */ diff --git a/include/linux/i2c.h b/include/linux/i2c.h index a6c652ef516d..0bd9ea2b62ea 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -540,6 +540,7 @@ struct i2c_msg { #define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000 #define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */ #define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */ +#define I2C_FUNC_I2C_SLAVE_SUPPORT 0x10000000 /* i2c slave support */ #define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \ I2C_FUNC_SMBUS_WRITE_BYTE) diff --git a/include/linux/i2c/atmel_mxt_ts.h b/include/linux/i2c/atmel_mxt_ts.h index f027f7a63511..29550c11f6dd 100644 --- a/include/linux/i2c/atmel_mxt_ts.h +++ b/include/linux/i2c/atmel_mxt_ts.h @@ -2,6 +2,8 @@ * Atmel maXTouch Touchscreen driver * * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Copyright (C) 2011 Atmel Corporation + * Copyright (C) 2011 NVIDIA Corporation * Author: Joonyoung Shim <jy0922.shim@samsung.com> * * This program is free software; you can redistribute it and/or modify it @@ -15,6 +17,16 @@ #include <linux/types.h> +/* + * Atmel I2C addresses + */ +#define MXT224_I2C_ADDR1 0x4A +#define MXT224_I2C_ADDR2 0x4B +#define MXT1386_I2C_ADDR1 0x4C +#define MXT1386_I2C_ADDR2 0x4D +#define MXT1386_I2C_ADDR3 0x5A +#define MXT1386_I2C_ADDR4 0x5B + /* Orient */ #define MXT_NORMAL 0x0 #define MXT_DIAGONAL 0x1 @@ -39,6 +51,10 @@ struct mxt_platform_data { unsigned int voltage; unsigned char orient; unsigned long irqflags; + u8(*read_chg) (void); + unsigned long config_crc; + unsigned int actv_cycle_time; + unsigned int idle_cycle_time; }; #endif /* __LINUX_ATMEL_MXT_TS_H */ diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 114c0f6fc63d..bb92f0b13288 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -82,6 +82,10 @@ #define TWL_MODULE_RTC TWL4030_MODULE_RTC #define TWL_MODULE_PWM TWL4030_MODULE_PWM0 +#define TWL6030_MODULE_CHARGER TWL4030_MODULE_MAIN_CHARGE +#define TWL6025_MODULE_CHARGER 0x18 + +#define TWL6030_MODULE_GASGAUGE 0x0B #define TWL6030_MODULE_ID0 0x0D #define TWL6030_MODULE_ID1 0x0E #define TWL6030_MODULE_ID2 0x0F @@ -108,6 +112,7 @@ #define GASGAUGE_INTR_OFFSET 17 #define USBOTG_INTR_OFFSET 4 #define CHARGER_INTR_OFFSET 2 +#define GPADCSW_INTR_OFFSET 1 #define RSV_INTR_OFFSET 0 /* INT register offsets */ @@ -172,6 +177,14 @@ TWL_CLASS_IS(4030, TWL4030_CLASS_ID) TWL_CLASS_IS(6030, TWL6030_CLASS_ID) #define TWL6025_SUBCLASS BIT(4) /* TWL6025 has changed registers */ +#define MPU80031_SUBCLASS BIT(5) /* MPU80031 has changed registers */ + +/* So we can recover the features in other parts of twl stack */ +unsigned int twl_features(void); + +/* so we can get at the EPROM SMPS OFFSET/MULT stuff */ +u8 twl_get_smps_offset(void); +u8 twl_get_smps_mult(void); /* * Read and write single 8-bit registers @@ -179,6 +192,8 @@ TWL_CLASS_IS(6030, TWL6030_CLASS_ID) int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg); int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg); +void twl_reg_dump(int module, int start, int end); + /* * Read and write several 8-bit registers at once. * @@ -215,6 +230,10 @@ static inline int twl6030_mmc_card_detect(struct device *dev, int slot) return -EIO; } #endif + +int twl6030_set_usb_charge_enable(int enable); +int twl6030_set_usb_in_current(int currentmA); + /*----------------------------------------------------------------------*/ /* @@ -552,11 +571,27 @@ static inline int twl6030_mmc_card_detect(struct device *dev, int slot) struct twl4030_clock_init_data { bool ck32k_lowpwr_enable; + bool clk32_active_state_on; }; struct twl4030_bci_platform_data { int *battery_tmp_tbl; - unsigned int tblsize; + unsigned int battery_tmp_tblsize; + int *battery_volt_tbl; + unsigned int battery_volt_tblsize; + unsigned int monitoring_interval; + + unsigned int max_charger_currentmA; + unsigned int max_charger_voltagemV; + unsigned int termination_currentmA; + + unsigned int max_bat_voltagemV; + unsigned int low_bat_voltagemV; + + /* twl6025 */ + unsigned int use_hw_charger; + unsigned int use_eeprom_config; + unsigned int power_path; }; /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ @@ -621,6 +656,7 @@ struct twl4030_usb_data { int (*phy_set_clock)(struct device *dev, int on); /* suspend/resume of phy */ int (*phy_suspend)(struct device *dev, int suspend); + int (*board_control_power)(struct device *dev, int on); }; struct twl4030_ins { @@ -696,6 +732,10 @@ struct twl4030_audio_data { struct twl4030_platform_data { unsigned irq_base, irq_end; + + /* Callback for boar regulator initialisation */ + int (*init)(void); + struct twl4030_clock_init_data *clock; struct twl4030_bci_platform_data *bci; struct twl4030_gpio_platform_data *gpio; @@ -822,6 +862,22 @@ static inline int twl4030charger_usb_en(int enable) { return 0; } #define TWL6030_REG_VDAC 45 #define TWL6030_REG_VUSB 46 +/* These are renamed in 6025 but same registers */ +#define TWL6025_REG_LDO2 48 +#define TWL6025_REG_LDO4 49 +#define TWL6025_REG_LDO3 50 +#define TWL6025_REG_LDO5 51 +#define TWL6025_REG_LDO1 52 +#define TWL6025_REG_LDO7 53 +#define TWL6025_REG_LDO6 54 +#define TWL6025_REG_LDOLN 55 +#define TWL6025_REG_LDOUSB 56 + +/* 6025 DCDC supplies */ +#define TWL6025_REG_SMPS3 57 +#define TWL6025_REG_SMPS4 58 +#define TWL6025_REG_VIO 59 + /* INTERNAL LDOs */ #define TWL6030_REG_VRTC 47 #define TWL6030_REG_CLK32KG 48 diff --git a/include/linux/ina219.h b/include/linux/ina219.h new file mode 100644 index 000000000000..c27fa26c5759 --- /dev/null +++ b/include/linux/ina219.h @@ -0,0 +1,34 @@ +/* + * linux/include/linux/ina219.h + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _INA219_H +#define _INA219_H + +#include <linux/types.h> + +struct ina219_platform_data { + u8 divisor; /*divisor needed to get current value */ + u32 calibration_data; + u32 power_lsb; + char rail_name[20]; +}; + +#endif /* _LINUX_INA219_H */ + diff --git a/include/linux/interrupt_keys.h b/include/linux/interrupt_keys.h new file mode 100755 index 000000000000..8be6e9a6b0a0 --- /dev/null +++ b/include/linux/interrupt_keys.h @@ -0,0 +1,47 @@ +/* + * include/linux/interrupt_keys.h + * + * Key driver for keys directly connected to intrrupt lines. + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _INTERRUPT_KEYS_H +#define _INTERRUPT_KEYS_H + +struct interrupt_keys_button { + /* Configuration parameters */ + int code; /* input event code (KEY_*, SW_*) */ + int irq; + int active_low; + char *desc; + int type; /* input event type (EV_KEY, EV_SW) */ + int wakeup; /* configure the interrupt source as a wake-up + * source */ + int debounce_interval; /* debounce ticks interval in msecs */ + bool can_disable; +}; + +struct interrupt_keys_platform_data { + struct interrupt_keys_button *int_buttons; + int nbuttons; + unsigned int rep:1; /* enable input subsystem auto repeat */ + int (*enable)(struct device *dev); + void (*disable)(struct device *dev); +}; + +#endif diff --git a/include/linux/mfd/max77663-core.h b/include/linux/mfd/max77663-core.h new file mode 100644 index 000000000000..1edaf7aaaf4d --- /dev/null +++ b/include/linux/mfd/max77663-core.h @@ -0,0 +1,173 @@ +/* + * include/linux/mfd/max77663-core.h + * + * Copyright 2011 Maxim Integrated Products, Inc. + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + */ + +#ifndef __LINUX_MFD_MAX77663_CORE_H__ +#define __LINUX_MFD_MAX77663_CORE_H__ + +#include <linux/irq.h> +#include <linux/mfd/core.h> + +/* + * Interrupts + */ +enum { + MAX77663_IRQ_LBT_LB, /* Low-Battery */ + MAX77663_IRQ_LBT_THERM_ALRM1, /* Thermal alarm status, > 120C */ + MAX77663_IRQ_LBT_THERM_ALRM2, /* Thermal alarm status, > 140C */ + + MAX77663_IRQ_GPIO0, /* GPIO0 edge detection */ + MAX77663_IRQ_GPIO1, /* GPIO1 edge detection */ + MAX77663_IRQ_GPIO2, /* GPIO2 edge detection */ + MAX77663_IRQ_GPIO3, /* GPIO3 edge detection */ + MAX77663_IRQ_GPIO4, /* GPIO4 edge detection */ + MAX77663_IRQ_GPIO5, /* GPIO5 edge detection */ + MAX77663_IRQ_GPIO6, /* GPIO6 edge detection */ + MAX77663_IRQ_GPIO7, /* GPIO7 edge detection */ + + MAX77663_IRQ_ONOFF_HRDPOWRN, /* Hard power off warnning */ + MAX77663_IRQ_ONOFF_EN0_1SEC, /* EN0 active for 1s */ + MAX77663_IRQ_ONOFF_EN0_FALLING, /* EN0 falling */ + MAX77663_IRQ_ONOFF_EN0_RISING, /* EN0 rising */ + MAX77663_IRQ_ONOFF_LID_FALLING, /* LID falling */ + MAX77663_IRQ_ONOFF_LID_RISING, /* LID rising */ + MAX77663_IRQ_ONOFF_ACOK_FALLING,/* ACOK falling */ + MAX77663_IRQ_ONOFF_ACOK_RISING, /* ACOK rising */ + + MAX77663_IRQ_RTC, /* RTC */ + MAX77663_IRQ_SD_PF, /* SD power fail */ + MAX77663_IRQ_LDO_PF, /* LDO power fail */ + MAX77663_IRQ_32K, /* 32kHz oscillator */ + MAX77663_IRQ_NVER, /* Non-Volatile Event Recorder */ + + MAX77663_IRQ_NR, +}; + +/* + *GPIOs + */ +enum { + MAX77663_GPIO0, + MAX77663_GPIO1, + MAX77663_GPIO2, + MAX77663_GPIO3, + MAX77663_GPIO4, + MAX77663_GPIO5, + MAX77663_GPIO6, + MAX77663_GPIO7, + + MAX77663_GPIO_NR, +}; + +/* Direction */ +enum max77663_gpio_dir { + GPIO_DIR_DEF, + GPIO_DIR_IN, + GPIO_DIR_OUT, +}; + +/* Data output */ +enum max77663_gpio_data_out { + GPIO_DOUT_DEF, + GPIO_DOUT_HIGH, + GPIO_DOUT_LOW, +}; + +/* Output drive */ +enum max77663_gpio_out_drv { + GPIO_OUT_DRV_DEF, + GPIO_OUT_DRV_PUSH_PULL, + GPIO_OUT_DRV_OPEN_DRAIN, +}; + +/* Pull-up */ +enum max77663_gpio_pull_up { + GPIO_PU_DEF, + GPIO_PU_ENABLE, + GPIO_PU_DISABLE, +}; + +/* Pull-down */ +enum max77663_gpio_pull_down { + GPIO_PD_DEF, + GPIO_PD_ENABLE, + GPIO_PD_DISABLE, +}; + +/* Alternate */ +enum max77663_gpio_alt { + GPIO_ALT_DEF, + GPIO_ALT_ENABLE, + GPIO_ALT_DISABLE, +}; + +struct max77663_gpio_config { + int gpio; /* gpio number */ + enum max77663_gpio_dir dir; + enum max77663_gpio_data_out dout; + enum max77663_gpio_out_drv out_drv; + enum max77663_gpio_pull_up pull_up; + enum max77663_gpio_pull_down pull_down; + enum max77663_gpio_alt alternate; +}; + +struct max77663_platform_data { + int irq_base; + int gpio_base; + + int num_gpio_cfgs; + struct max77663_gpio_config *gpio_cfgs; + + int num_subdevs; + struct mfd_cell *sub_devices; +}; + +#if defined(CONFIG_MFD_MAX77663) +int max77663_read(struct device *dev, u8 addr, void *values, u32 len, + bool is_rtc); +int max77663_write(struct device *dev, u8 addr, void *values, u32 len, + bool is_rtc); +int max77663_set_bits(struct device *dev, u8 addr, u8 mask, u8 value, + bool is_rtc); +int max77663_power_off(void); +int max77663_gpio_set_alternate(int gpio, int alternate); +#else +static inline int max77663_read(struct device *dev, u8 addr, void *values, + u32 len, bool is_rtc) +{ + return 0; +} + +static inline int max77663_write(struct device *dev, u8 addr, void *values, + u32 len, bool is_rtc) +{ + return 0; +} + +static inline int max77663_set_bits(struct device *dev, u8 addr, u8 mask, + u8 value, bool is_rtc) +{ + return 0; +} + +static inline int max77663_power_off(void) +{ + return 0; +} + +static inline int max77663_gpio_set_alternate(int gpio, int alternate) +{ + return 0; +} +#endif /* defined(CONFIG_MFD_MAX77663) */ + +#endif /* __LINUX_MFD_MAX77663_CORE_H__ */ diff --git a/include/linux/mfd/max8907c.h b/include/linux/mfd/max8907c.h new file mode 100644 index 000000000000..76dbdcc03046 --- /dev/null +++ b/include/linux/mfd/max8907c.h @@ -0,0 +1,259 @@ +/* linux/mfd/max8907c.h + * + * Functions to access MAX8907C power management chip. + * + * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_MAX8907C_H +#define __LINUX_MFD_MAX8907C_H + +/* MAX8907C register map */ +#define MAX8907C_REG_SYSENSEL 0x00 +#define MAX8907C_REG_ON_OFF_IRQ1 0x01 +#define MAX8907C_REG_ON_OFF_IRQ1_MASK 0x02 +#define MAX8907C_REG_ON_OFF_STAT 0x03 +#define MAX8907C_REG_SDCTL1 0x04 +#define MAX8907C_REG_SDSEQCNT1 0x05 +#define MAX8907C_REG_SDV1 0x06 +#define MAX8907C_REG_SDCTL2 0x07 +#define MAX8907C_REG_SDSEQCNT2 0x08 +#define MAX8907C_REG_SDV2 0x09 +#define MAX8907C_REG_SDCTL3 0x0A +#define MAX8907C_REG_SDSEQCNT3 0x0B +#define MAX8907C_REG_SDV3 0x0C +#define MAX8907C_REG_ON_OFF_IRQ2 0x0D +#define MAX8907C_REG_ON_OFF_IRQ2_MASK 0x0E +#define MAX8907C_REG_RESET_CNFG 0x0F +#define MAX8907C_REG_LDOCTL16 0x10 +#define MAX8907C_REG_LDOSEQCNT16 0x11 +#define MAX8907C_REG_LDO16VOUT 0x12 +#define MAX8907C_REG_SDBYSEQCNT 0x13 +#define MAX8907C_REG_LDOCTL17 0x14 +#define MAX8907C_REG_LDOSEQCNT17 0x15 +#define MAX8907C_REG_LDO17VOUT 0x16 +#define MAX8907C_REG_LDOCTL1 0x18 +#define MAX8907C_REG_LDOSEQCNT1 0x19 +#define MAX8907C_REG_LDO1VOUT 0x1A +#define MAX8907C_REG_LDOCTL2 0x1C +#define MAX8907C_REG_LDOSEQCNT2 0x1D +#define MAX8907C_REG_LDO2VOUT 0x1E +#define MAX8907C_REG_LDOCTL3 0x20 +#define MAX8907C_REG_LDOSEQCNT3 0x21 +#define MAX8907C_REG_LDO3VOUT 0x22 +#define MAX8907C_REG_LDOCTL4 0x24 +#define MAX8907C_REG_LDOSEQCNT4 0x25 +#define MAX8907C_REG_LDO4VOUT 0x26 +#define MAX8907C_REG_LDOCTL5 0x28 +#define MAX8907C_REG_LDOSEQCNT5 0x29 +#define MAX8907C_REG_LDO5VOUT 0x2A +#define MAX8907C_REG_LDOCTL6 0x2C +#define MAX8907C_REG_LDOSEQCNT6 0x2D +#define MAX8907C_REG_LDO6VOUT 0x2E +#define MAX8907C_REG_LDOCTL7 0x30 +#define MAX8907C_REG_LDOSEQCNT7 0x31 +#define MAX8907C_REG_LDO7VOUT 0x32 +#define MAX8907C_REG_LDOCTL8 0x34 +#define MAX8907C_REG_LDOSEQCNT8 0x35 +#define MAX8907C_REG_LDO8VOUT 0x36 +#define MAX8907C_REG_LDOCTL9 0x38 +#define MAX8907C_REG_LDOSEQCNT9 0x39 +#define MAX8907C_REG_LDO9VOUT 0x3A +#define MAX8907C_REG_LDOCTL10 0x3C +#define MAX8907C_REG_LDOSEQCNT10 0x3D +#define MAX8907C_REG_LDO10VOUT 0x3E +#define MAX8907C_REG_LDOCTL11 0x40 +#define MAX8907C_REG_LDOSEQCNT11 0x41 +#define MAX8907C_REG_LDO11VOUT 0x42 +#define MAX8907C_REG_LDOCTL12 0x44 +#define MAX8907C_REG_LDOSEQCNT12 0x45 +#define MAX8907C_REG_LDO12VOUT 0x46 +#define MAX8907C_REG_LDOCTL13 0x48 +#define MAX8907C_REG_LDOSEQCNT13 0x49 +#define MAX8907C_REG_LDO13VOUT 0x4A +#define MAX8907C_REG_LDOCTL14 0x4C +#define MAX8907C_REG_LDOSEQCNT14 0x4D +#define MAX8907C_REG_LDO14VOUT 0x4E +#define MAX8907C_REG_LDOCTL15 0x50 +#define MAX8907C_REG_LDOSEQCNT15 0x51 +#define MAX8907C_REG_LDO15VOUT 0x52 +#define MAX8907C_REG_OUT5VEN 0x54 +#define MAX8907C_REG_OUT5VSEQ 0x55 +#define MAX8907C_REG_OUT33VEN 0x58 +#define MAX8907C_REG_OUT33VSEQ 0x59 +#define MAX8907C_REG_LDOCTL19 0x5C +#define MAX8907C_REG_LDOSEQCNT19 0x5D +#define MAX8907C_REG_LDO19VOUT 0x5E +#define MAX8907C_REG_LBCNFG 0x60 +#define MAX8907C_REG_SEQ1CNFG 0x64 +#define MAX8907C_REG_SEQ2CNFG 0x65 +#define MAX8907C_REG_SEQ3CNFG 0x66 +#define MAX8907C_REG_SEQ4CNFG 0x67 +#define MAX8907C_REG_SEQ5CNFG 0x68 +#define MAX8907C_REG_SEQ6CNFG 0x69 +#define MAX8907C_REG_SEQ7CNFG 0x6A +#define MAX8907C_REG_LDOCTL18 0x72 +#define MAX8907C_REG_LDOSEQCNT18 0x73 +#define MAX8907C_REG_LDO18VOUT 0x74 +#define MAX8907C_REG_BBAT_CNFG 0x78 +#define MAX8907C_REG_CHG_CNTL1 0x7C +#define MAX8907C_REG_CHG_CNTL2 0x7D +#define MAX8907C_REG_CHG_IRQ1 0x7E +#define MAX8907C_REG_CHG_IRQ2 0x7F +#define MAX8907C_REG_CHG_IRQ1_MASK 0x80 +#define MAX8907C_REG_CHG_IRQ2_MASK 0x81 +#define MAX8907C_REG_CHG_STAT 0x82 +#define MAX8907C_REG_WLED_MODE_CNTL 0x84 +#define MAX8907C_REG_ILED_CNTL 0x84 +#define MAX8907C_REG_II1RR 0x8E +#define MAX8907C_REG_II2RR 0x8F +#define MAX8907C_REG_LDOCTL20 0x9C +#define MAX8907C_REG_LDOSEQCNT20 0x9D +#define MAX8907C_REG_LDO20VOUT 0x9E + +/* RTC register */ +#define MAX8907C_REG_RTC_SEC 0x00 +#define MAX8907C_REG_RTC_MIN 0x01 +#define MAX8907C_REG_RTC_HOURS 0x02 +#define MAX8907C_REG_RTC_WEEKDAY 0x03 +#define MAX8907C_REG_RTC_DATE 0x04 +#define MAX8907C_REG_RTC_MONTH 0x05 +#define MAX8907C_REG_RTC_YEAR1 0x06 +#define MAX8907C_REG_RTC_YEAR2 0x07 +#define MAX8907C_REG_ALARM0_SEC 0x08 +#define MAX8907C_REG_ALARM0_MIN 0x09 +#define MAX8907C_REG_ALARM0_HOURS 0x0A +#define MAX8907C_REG_ALARM0_WEEKDAY 0x0B +#define MAX8907C_REG_ALARM0_DATE 0x0C +#define MAX8907C_REG_ALARM0_MONTH 0x0D +#define MAX8907C_REG_ALARM0_YEAR1 0x0E +#define MAX8907C_REG_ALARM0_YEAR2 0x0F +#define MAX8907C_REG_ALARM1_SEC 0x10 +#define MAX8907C_REG_ALARM1_MIN 0x11 +#define MAX8907C_REG_ALARM1_HOURS 0x12 +#define MAX8907C_REG_ALARM1_WEEKDAY 0x13 +#define MAX8907C_REG_ALARM1_DATE 0x14 +#define MAX8907C_REG_ALARM1_MONTH 0x15 +#define MAX8907C_REG_ALARM1_YEAR1 0x16 +#define MAX8907C_REG_ALARM1_YEAR2 0x17 +#define MAX8907C_REG_ALARM0_CNTL 0x18 +#define MAX8907C_REG_ALARM1_CNTL 0x19 +#define MAX8907C_REG_RTC_STATUS 0x1A +#define MAX8907C_REG_RTC_CNTL 0x1B +#define MAX8907C_REG_RTC_IRQ 0x1C +#define MAX8907C_REG_RTC_IRQ_MASK 0x1D +#define MAX8907C_REG_MPL_CNTL 0x1E + +/* ADC and Touch Screen Controller register map */ + +#define MAX8907C_CTL 0 +#define MAX8907C_SEQCNT 1 +#define MAX8907C_VOUT 2 + +/* mask bit fields */ +#define MAX8907C_MASK_LDO_SEQ 0x1C +#define MAX8907C_MASK_LDO_EN 0x01 +#define MAX8907C_MASK_VBBATTCV 0x03 +#define MAX8907C_MASK_OUT5V_VINEN 0x10 +#define MAX8907C_MASK_OUT5V_ENSRC 0x0E +#define MAX8907C_MASK_OUT5V_EN 0x01 + +/* Power off bit in RESET_CNFG reg */ +#define MAX8907C_MASK_POWER_OFF 0x40 + +#define MAX8907C_MASK_PWR_EN 0x80 +#define MAX8907C_MASK_CTL_SEQ 0x1C + +#define MAX8907C_PWR_EN 0x80 +#define MAX8907C_CTL_SEQ 0x04 + +#define MAX8907C_SD_SEQ1 0x02 +#define MAX8907C_SD_SEQ2 0x06 + +#define MAX8907C_DELAY_CNT0 0x00 + +#define MAX8907C_POWER_UP_DELAY_CNT1 0x10 +#define MAX8907C_POWER_UP_DELAY_CNT12 0xC0 + +#define MAX8907C_POWER_DOWN_DELAY_CNT12 0x0C + +#define RTC_I2C_ADDR 0x68 + +/* + * MAX8907B revision requires s/w WAR to connect PWREN input to + * sequencer 2 because of the bug in the silicon. + */ +#define MAX8907B_II2RR_PWREN_WAR (0x12) + +/* Defines common for all supplies PWREN sequencer selection */ +#define MAX8907B_SEQSEL_PWREN_LXX 1 /* SEQ2 (PWREN) */ + +/* IRQ definitions */ +enum { + MAX8907C_IRQ_VCHG_DC_OVP, + MAX8907C_IRQ_VCHG_DC_F, + MAX8907C_IRQ_VCHG_DC_R, + MAX8907C_IRQ_VCHG_THM_OK_R, + MAX8907C_IRQ_VCHG_THM_OK_F, + MAX8907C_IRQ_VCHG_MBATTLOW_F, + MAX8907C_IRQ_VCHG_MBATTLOW_R, + MAX8907C_IRQ_VCHG_RST, + MAX8907C_IRQ_VCHG_DONE, + MAX8907C_IRQ_VCHG_TOPOFF, + MAX8907C_IRQ_VCHG_TMR_FAULT, + MAX8907C_IRQ_GPM_RSTIN, + MAX8907C_IRQ_GPM_MPL, + MAX8907C_IRQ_GPM_SW_3SEC, + MAX8907C_IRQ_GPM_EXTON_F, + MAX8907C_IRQ_GPM_EXTON_R, + MAX8907C_IRQ_GPM_SW_1SEC, + MAX8907C_IRQ_GPM_SW_F, + MAX8907C_IRQ_GPM_SW_R, + MAX8907C_IRQ_GPM_SYSCKEN_F, + MAX8907C_IRQ_GPM_SYSCKEN_R, + MAX8907C_IRQ_RTC_ALARM1, + MAX8907C_IRQ_RTC_ALARM0, + MAX8907C_NR_IRQS, +}; + +struct max8907c { + struct device *dev; + struct mutex io_lock; + struct mutex irq_lock; + struct i2c_client *i2c_power; + struct i2c_client *i2c_rtc; + int irq_base; + int core_irq; + + unsigned char cache_chg[2]; + unsigned char cache_on[2]; + unsigned char cache_rtc; + +}; + +struct max8907c_platform_data { + int num_subdevs; + struct platform_device **subdevs; + int irq_base; + int (*max8907c_setup)(void); +}; + +int max8907c_reg_read(struct i2c_client *i2c, u8 reg); +int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val); +int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val); +int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val); +int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val); + +int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base); +void max8907c_irq_free(struct max8907c *chip); +int max8907c_suspend(struct i2c_client *i2c, pm_message_t state); +int max8907c_resume(struct i2c_client *i2c); +int max8907c_power_off(void); +void max8907c_deep_sleep(int enter); +int max8907c_pwr_en_config(void); +int max8907c_pwr_en_attach(void); +#endif diff --git a/include/linux/mfd/ricoh583.h b/include/linux/mfd/ricoh583.h new file mode 100644 index 000000000000..086cbff5eefb --- /dev/null +++ b/include/linux/mfd/ricoh583.h @@ -0,0 +1,162 @@ +/* include/linux/mfd/ricoh583.h + * + * Core driver interface to access RICOH583 power management chip. + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_MFD_RICOH583_H +#define __LINUX_MFD_RICOH583_H + +/* RICOH583 IRQ definitions */ +enum { + RICOH583_IRQ_ONKEY, + RICOH583_IRQ_ACOK, + RICOH583_IRQ_LIDOPEN, + RICOH583_IRQ_PREOT, + RICOH583_IRQ_CLKSTP, + RICOH583_IRQ_ONKEY_OFF, + RICOH583_IRQ_WD, + RICOH583_IRQ_EN_PWRREQ1, + RICOH583_IRQ_EN_PWRREQ2, + RICOH583_IRQ_PRE_VINDET, + + RICOH583_IRQ_DC0LIM, + RICOH583_IRQ_DC1LIM, + RICOH583_IRQ_DC2LIM, + RICOH583_IRQ_DC3LIM, + + RICOH583_IRQ_CTC, + RICOH583_IRQ_YALE, + RICOH583_IRQ_DALE, + RICOH583_IRQ_WALE, + + RICOH583_IRQ_AIN1L, + RICOH583_IRQ_AIN2L, + RICOH583_IRQ_AIN3L, + RICOH583_IRQ_VBATL, + RICOH583_IRQ_VIN3L, + RICOH583_IRQ_VIN8L, + RICOH583_IRQ_AIN1H, + RICOH583_IRQ_AIN2H, + RICOH583_IRQ_AIN3H, + RICOH583_IRQ_VBATH, + RICOH583_IRQ_VIN3H, + RICOH583_IRQ_VIN8H, + RICOH583_IRQ_ADCEND, + + RICOH583_IRQ_GPIO0, + RICOH583_IRQ_GPIO1, + RICOH583_IRQ_GPIO2, + RICOH583_IRQ_GPIO3, + RICOH583_IRQ_GPIO4, + RICOH583_IRQ_GPIO5, + RICOH583_IRQ_GPIO6, + RICOH583_IRQ_GPIO7, + RICOH583_NR_IRQS, +}; + +/* Ricoh583 gpio definitions */ +enum { + RICOH583_GPIO0, + RICOH583_GPIO1, + RICOH583_GPIO2, + RICOH583_GPIO3, + RICOH583_GPIO4, + RICOH583_GPIO5, + RICOH583_GPIO6, + RICOH583_GPIO7, + + RICOH583_NR_GPIO, +}; + +enum ricoh583_deepsleep_control_id { + RICOH583_DS_NONE, + RICOH583_DS_DC0, + RICOH583_DS_DC1, + RICOH583_DS_DC2, + RICOH583_DS_DC3, + RICOH583_DS_LDO0, + RICOH583_DS_LDO1, + RICOH583_DS_LDO2, + RICOH583_DS_LDO3, + RICOH583_DS_LDO4, + RICOH583_DS_LDO5, + RICOH583_DS_LDO6, + RICOH583_DS_LDO7, + RICOH583_DS_LDO8, + RICOH583_DS_LDO9, + RICOH583_DS_PSO0, + RICOH583_DS_PSO1, + RICOH583_DS_PSO2, + RICOH583_DS_PSO3, + RICOH583_DS_PSO4, + RICOH583_DS_PSO5, + RICOH583_DS_PSO6, + RICOH583_DS_PSO7, +}; +enum ricoh583_ext_pwrreq_control { + RICOH583_EXT_PWRREQ1_CONTROL = 0x1, + RICOH583_EXT_PWRREQ2_CONTROL = 0x2, +}; + +struct ricoh583_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct ricoh583_rtc_platform_data { + int irq; +}; + +struct ricoh583_gpio_init_data { + unsigned pulldn_en:1; /* Enable pull down */ + unsigned output_mode_en:1; /* Enable output mode during init */ + unsigned output_val:1; /* Output value if it is in output mode */ + unsigned init_apply:1; /* Apply init data on configuring gpios*/ +}; + +struct ricoh583_platform_data { + int num_subdevs; + struct ricoh583_subdev_info *subdevs; + int gpio_base; + int irq_base; + + struct ricoh583_gpio_init_data *gpio_init_data; + int num_gpioinit_data; + bool enable_shutdown_pin; +}; + +extern int ricoh583_read(struct device *dev, uint8_t reg, uint8_t *val); +extern int ricoh583_bulk_read(struct device *dev, u8 reg, u8 count, + uint8_t *val); +extern int ricoh583_write(struct device *dev, u8 reg, uint8_t val); +extern int ricoh583_bulk_write(struct device *dev, u8 reg, u8 count, + uint8_t *val); +extern int ricoh583_set_bits(struct device *dev, u8 reg, uint8_t bit_mask); +extern int ricoh583_clr_bits(struct device *dev, u8 reg, uint8_t bit_mask); +extern int ricoh583_update(struct device *dev, u8 reg, uint8_t val, + uint8_t mask); +extern int ricoh583_ext_power_req_config(struct device *dev, + enum ricoh583_deepsleep_control_id control_id, + enum ricoh583_ext_pwrreq_control ext_pwr_req, + int deepsleep_slot_nr); +extern int ricoh583_power_off(void); + +#endif diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index d96fb3d3e624..e43184a43201 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -1,6 +1,10 @@ #ifndef __LINUX_MFD_TPS6586X_H #define __LINUX_MFD_TPS6586X_H +#define SM0_PWM_BIT 0 +#define SM1_PWM_BIT 1 +#define SM2_PWM_BIT 2 + enum { TPS6586X_ID_SM_0, TPS6586X_ID_SM_1, @@ -48,14 +52,58 @@ enum { TPS6586X_INT_RTC_ALM2, }; +enum pwm_pfm_mode { + PWM_ONLY, + AUTO_PWM_PFM, + PWM_DEFAULT_VALUE, + +}; + +enum slew_rate_settings { + SLEW_RATE_INSTANTLY = 0, + SLEW_RATE_0110UV_PER_SEC = 0x1, + SLEW_RATE_0220UV_PER_SEC = 0x2, + SLEW_RATE_0440UV_PER_SEC = 0x3, + SLEW_RATE_0880UV_PER_SEC = 0x4, + SLEW_RATE_1760UV_PER_SEC = 0x5, + SLEW_RATE_3520UV_PER_SEC = 0x6, + SLEW_RATE_7040UV_PER_SEC = 0x7, + SLEW_RATE_DEFAULT_VALUE, +}; + +struct tps6586x_settings { + /* SM0, SM1 and SM2 have PWM-only and auto PWM/PFM mode */ + enum pwm_pfm_mode sm_pwm_mode; + /* SM0 and SM1 have slew rate settings */ + enum slew_rate_settings slew_rate; +}; + +enum { + TPS6586X_RTC_CL_SEL_1_5PF = 0x0, + TPS6586X_RTC_CL_SEL_6_5PF = 0x1, + TPS6586X_RTC_CL_SEL_7_5PF = 0x2, + TPS6586X_RTC_CL_SEL_12_5PF = 0x3, +}; + struct tps6586x_subdev_info { int id; const char *name; void *platform_data; }; +struct tps6586x_epoch_start { + int year; + int month; + int day; + int hour; + int min; + int sec; +}; + struct tps6586x_rtc_platform_data { int irq; + struct tps6586x_epoch_start start; + int cl_sel; /* internal XTAL capacitance, see TPS6586X_RTC_CL_SEL* */ }; struct tps6586x_platform_data { @@ -78,5 +126,6 @@ extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask); extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); extern int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask); +extern int tps6586x_power_off(void); #endif /*__LINUX_MFD_TPS6586X_H */ diff --git a/include/linux/mfd/tps6591x.h b/include/linux/mfd/tps6591x.h new file mode 100644 index 000000000000..525a8616c44b --- /dev/null +++ b/include/linux/mfd/tps6591x.h @@ -0,0 +1,123 @@ +/* + * include/linux/mfd/tps6591x.c + * Core driver interface for TI TPS6591x PMIC family + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_MFD_TPS6591X_H +#define __LINUX_MFD_TPS6591X_H + +#include <linux/rtc.h> + +enum { + TPS6591X_INT_PWRHOLD_F, + TPS6591X_INT_VMBHI, + TPS6591X_INT_PWRON, + TPS6591X_INT_PWRON_LP, + TPS6591X_INT_PWRHOLD_R, + TPS6591X_INT_HOTDIE, + TPS6591X_INT_RTC_ALARM, + TPS6591X_INT_RTC_PERIOD, + TPS6591X_INT_GPIO0, + TPS6591X_INT_GPIO1, + TPS6591X_INT_GPIO2, + TPS6591X_INT_GPIO3, + TPS6591X_INT_GPIO4, + TPS6591X_INT_GPIO5, + TPS6591X_INT_WTCHDG, + TPS6591X_INT_VMBCH2_H, + TPS6591X_INT_VMBCH2_L, + TPS6591X_INT_PWRDN, + + /* Last entry */ + TPS6591X_INT_NR, +}; + +/* Gpio definitions */ +enum { + TPS6591X_GPIO_GP0 = 0, + TPS6591X_GPIO_GP1 = 1, + TPS6591X_GPIO_GP2 = 2, + TPS6591X_GPIO_GP3 = 3, + TPS6591X_GPIO_GP4 = 4, + TPS6591X_GPIO_GP5 = 5, + TPS6591X_GPIO_GP6 = 6, + TPS6591X_GPIO_GP7 = 7, + TPS6591X_GPIO_GP8 = 8, + + /* Last entry */ + TPS6591X_GPIO_NR, +}; + +struct tps6591x_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct tps6591x_rtc_platform_data { + int irq; + struct rtc_time time; +}; + +struct tps6591x_sleep_keepon_data { + /* set 1 to maintain the following on sleep mode */ + unsigned therm_keepon:1; /* themal monitoring */ + unsigned clkout32k_keepon:1; /* CLK32KOUT */ + unsigned vrtc_keepon:1; /* LD0 full load capability */ + unsigned i2chs_keepon:1; /* high speed internal clock */ +}; + +struct tps6591x_gpio_init_data { + unsigned sleep_en:1; /* Enable sleep mode */ + unsigned pulldn_en:1; /* Enable pull down */ + unsigned output_mode_en:1; /* Enable output mode during init */ + unsigned output_val:1; /* Output value if it is in output mode */ + unsigned init_apply:1; /* Apply init data on configuring gpios*/ +}; + +struct tps6591x_platform_data { + int gpio_base; + int irq_base; + + int num_subdevs; + struct tps6591x_subdev_info *subdevs; + + bool dev_slp_en; + struct tps6591x_sleep_keepon_data *slp_keepon; + + struct tps6591x_gpio_init_data *gpio_init_data; + int num_gpioinit_data; +}; + +/* + * NOTE: the functions below are not intended for use outside + * of the TPS6591X sub-device drivers + */ +extern int tps6591x_write(struct device *dev, int reg, uint8_t val); +extern int tps6591x_writes(struct device *dev, int reg, int len, uint8_t *val); +extern int tps6591x_read(struct device *dev, int reg, uint8_t *val); +extern int tps6591x_reads(struct device *dev, int reg, int len, uint8_t *val); +extern int tps6591x_set_bits(struct device *dev, int reg, uint8_t bit_mask); +extern int tps6591x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); +extern int tps6591x_update(struct device *dev, int reg, uint8_t val, + uint8_t mask); +extern int tps6591x_power_off(void); + +#endif /*__LINUX_MFD_TPS6591X_H */ diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h new file mode 100644 index 000000000000..ef5502c5c767 --- /dev/null +++ b/include/linux/mfd/tps80031.h @@ -0,0 +1,191 @@ +/* + * include/linux/mfd/tps80031.c + * + * Core driver interface for TI TPS80031 PMIC + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_MFD_TPS80031_H +#define __LINUX_MFD_TPS80031_H + +#include <linux/rtc.h> + +/* Supported chips */ +enum chips { + TPS80031 = 0x00000001, + TPS80032 = 0x00000002, +}; + +enum { + TPS80031_INT_PWRON, + TPS80031_INT_RPWRON, + TPS80031_INT_SYS_VLOW, + TPS80031_INT_RTC_ALARM, + TPS80031_INT_RTC_PERIOD, + TPS80031_INT_HOT_DIE, + TPS80031_INT_VXX_SHORT, + TPS80031_INT_SPDURATION, + TPS80031_INT_WATCHDOG, + TPS80031_INT_BAT, + TPS80031_INT_SIM, + TPS80031_INT_MMC, + TPS80031_INT_RES, + TPS80031_INT_GPADC_RT, + TPS80031_INT_GPADC_SW2_EOC, + TPS80031_INT_CC_AUTOCAL, + TPS80031_INT_ID_WKUP, + TPS80031_INT_VBUSS_WKUP, + TPS80031_INT_ID, + TPS80031_INT_VBUS, + TPS80031_INT_CHRG_CTRL, + TPS80031_INT_EXT_CHRG, + TPS80031_INT_INT_CHRG, + TPS80031_INT_RES2, + TPS80031_INT_BAT_TEMP_OVRANGE, + TPS80031_INT_BAT_REMOVED, + TPS80031_INT_VBUS_DET, + TPS80031_INT_VAC_DET, + TPS80031_INT_FAULT_WDG, + TPS80031_INT_LINCH_GATED, + + /* Last interrupt id to get the end number */ + TPS80031_INT_NR, +}; + +enum adc_channel { + BATTERY_TYPE = 0, /* External ADC */ + BATTERY_TEMPERATURE = 1, /* External ADC */ + AUDIO_ACCESSORY = 2, /* External ADC */ + TEMPERATURE_EXTERNAL_DIODE = 3, /* External ADC */ + TEMPERATURE_MEASUREMENT = 4, /* External ADC */ + GENERAL_PURPOSE_1 = 5, /* External ADC */ + GENERAL_PURPOSE_2 = 6, /* External ADC */ + SYSTEM_SUPPLY = 7, /* Internal ADC */ + BACKUP_BATTERY = 8, /* Internal ADC */ + EXTERNAL_CHARGER_INPUT = 9, /* Internal ADC */ + VBUS = 10, /* Internal ADC */ + VBUS_DCDC_OUTPUT_CURRENT = 11, /* Internal ADC */ + DIE_TEMPERATURE_1 = 12, /* Internal ADC */ + DIE_TEMPERATURE_2 = 13, /* Internal ADC */ + USB_ID_LINE = 14, /* Internal ADC */ + TEST_NETWORK_1 = 15, /* Internal ADC */ + TEST_NETWORK_2 = 16, /* Internal ADC */ + BATTERY_CHARGING_CURRENT = 17, /* Internal ADC */ + BATTERY_VOLTAGE = 18, /* Internal ADC */ +}; + +enum TPS80031_GPIO { + TPS80031_GPIO_REGEN1, + TPS80031_GPIO_REGEN2, + TPS80031_GPIO_SYSEN, + + /* Last entry */ + TPS80031_GPIO_NR, +}; + +enum { + SLAVE_ID0 = 0, + SLAVE_ID1 = 1, + SLAVE_ID2 = 2, + SLAVE_ID3 = 3, +}; + +enum { + I2C_ID0_ADDR = 0x12, + I2C_ID1_ADDR = 0x48, + I2C_ID2_ADDR = 0x49, + I2C_ID3_ADDR = 0x4A, +}; + +/* External power requests */ +enum tps80031_ext_control { + PWR_REQ_INPUT_NONE = 0x00000000, + PWR_REQ_INPUT_PREQ1 = 0x00000001, + PWR_REQ_INPUT_PREQ2 = 0x00000002, + PWR_REQ_INPUT_PREQ3 = 0x00000004, +}; + +struct tps80031_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct tps80031_rtc_platform_data { + int irq; + struct rtc_time time; +}; + +struct tps80031_32kclock_plat_data { + unsigned en_clk32kao:1; + unsigned en_clk32kg:1; + unsigned en_clk32kaudio:1; +}; + +struct tps80031_gpio_init_data { + int gpio_nr; + enum tps80031_ext_control ext_control; +}; + +struct tps80031_platform_data { + int num_subdevs; + struct tps80031_subdev_info *subdevs; + int gpio_base; + int irq_base; + struct tps80031_32kclock_plat_data *clk32k_pdata; + struct tps80031_gpio_init_data *gpio_init_data; + int gpio_init_data_size; +}; + +struct tps80031_bg_platform_data { + int irq_base; + int battery_present; +}; + +/* + * NOTE: the functions below are not intended for use outside + * of the TPS80031 sub-device drivers + */ +extern int tps80031_write(struct device *dev, int sid, int reg, uint8_t val); +extern int tps80031_writes(struct device *dev, int sid, int reg, int len, + uint8_t *val); +extern int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val); +extern int tps80031_reads(struct device *dev, int sid, int reg, int len, + uint8_t *val); +extern int tps80031_set_bits(struct device *dev, int sid, int reg, + uint8_t bit_mask); +extern int tps80031_clr_bits(struct device *dev, int sid, int reg, + uint8_t bit_mask); +extern int tps80031_update(struct device *dev, int sid, int reg, uint8_t val, + uint8_t mask); +extern int tps80031_force_update(struct device *dev, int sid, int reg, + uint8_t val, uint8_t mask); +extern int tps80031_ext_power_req_config(struct device *dev, + enum tps80031_ext_control ext_pwr_ctrl, int preq_bit, + int state_reg_add, int trans_reg_add); + +extern int tps80031_power_off(void); + +extern unsigned long tps80031_get_chip_info(struct device *dev); + +extern int tps80031_gpadc_conversion(int channle_no); + +extern int tps80031_get_pmu_version(struct device *dev); + +#endif /*__LINUX_MFD_TPS80031_H */ diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 5666f3abfab7..9d499a078bbc 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -145,6 +145,7 @@ struct sdhci_host { struct tasklet_struct finish_tasklet; struct timer_list timer; /* Timer for timeouts */ + unsigned int card_int_set; /* card int status */ unsigned int caps; /* Alternative capabilities */ diff --git a/include/linux/mpu.h b/include/linux/mpu.h new file mode 100644 index 000000000000..d66d9e76b9af --- /dev/null +++ b/include/linux/mpu.h @@ -0,0 +1,467 @@ +/* + $License: + Copyright (C) 2010 InvenSense Corporation, All Rights Reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. + $ + */ + +#ifndef __MPU_H_ +#define __MPU_H_ + +#ifdef __KERNEL__ +#include <linux/types.h> +#include <linux/ioctl.h> +#elif defined LINUX +#include <sys/ioctl.h> +#endif + +#ifdef M_HW +#include "mpu6000.h" +#else +#include "mpu3050.h" +#endif + +/* Number of axes on each sensor */ +#define GYRO_NUM_AXES (3) +#define ACCEL_NUM_AXES (3) +#define COMPASS_NUM_AXES (3) + +#if defined __KERNEL__ || defined LINUX +#define MPU_IOCTL (0x81) /* Magic number for MPU Iocts */ +/* IOCTL commands for /dev/mpu */ +#define MPU_SET_MPU_CONFIG _IOW(MPU_IOCTL, 0x00, struct mldl_cfg) +#define MPU_GET_MPU_CONFIG _IOR(MPU_IOCTL, 0x00, struct mldl_cfg) + +#define MPU_SET_PLATFORM_DATA _IOW(MPU_IOCTL, 0x01, struct mldl_cfg) + +#define MPU_READ _IOR(MPU_IOCTL, 0x10, struct mpu_read_write) +#define MPU_WRITE _IOW(MPU_IOCTL, 0x10, struct mpu_read_write) +#define MPU_READ_MEM _IOR(MPU_IOCTL, 0x11, struct mpu_read_write) +#define MPU_WRITE_MEM _IOW(MPU_IOCTL, 0x11, struct mpu_read_write) +#define MPU_READ_FIFO _IOR(MPU_IOCTL, 0x12, struct mpu_read_write) +#define MPU_WRITE_FIFO _IOW(MPU_IOCTL, 0x12, struct mpu_read_write) + +#define MPU_READ_COMPASS _IOR(MPU_IOCTL, 0x12, unsigned char) +#define MPU_READ_ACCEL _IOR(MPU_IOCTL, 0x13, unsigned char) +#define MPU_READ_PRESSURE _IOR(MPU_IOCTL, 0x14, unsigned char) + +#define MPU_CONFIG_ACCEL _IOW(MPU_IOCTL, 0x20, struct ext_slave_config) +#define MPU_CONFIG_COMPASS _IOW(MPU_IOCTL, 0x21, struct ext_slave_config) +#define MPU_CONFIG_PRESSURE _IOW(MPU_IOCTL, 0x22, struct ext_slave_config) + +#define MPU_GET_CONFIG_ACCEL _IOR(MPU_IOCTL, 0x20, struct ext_slave_config) +#define MPU_GET_CONFIG_COMPASS _IOR(MPU_IOCTL, 0x21, struct ext_slave_config) +#define MPU_GET_CONFIG_PRESSURE _IOR(MPU_IOCTL, 0x22, struct ext_slave_config) + +#define MPU_SUSPEND _IO(MPU_IOCTL, 0x30) +#define MPU_RESUME _IO(MPU_IOCTL, 0x31) +/* Userspace PM Event response */ +#define MPU_PM_EVENT_HANDLED _IO(MPU_IOCTL, 0x32) + +#endif +/* Structure for the following IOCTL's: + MPU_READ + MPU_WRITE + MPU_READ_MEM + MPU_WRITE_MEM + MPU_READ_FIFO + MPU_WRITE_FIFO +*/ +struct mpu_read_write { + /* Memory address or register address depending on ioctl */ + unsigned short address; + unsigned short length; + unsigned char *data; +}; + +enum mpuirq_data_type { + MPUIRQ_DATA_TYPE_MPU_IRQ, + MPUIRQ_DATA_TYPE_SLAVE_IRQ, + MPUIRQ_DATA_TYPE_PM_EVENT, + MPUIRQ_DATA_TYPE_NUM_TYPES, +}; + +/* User space PM event notification */ +#define MPU_PM_EVENT_SUSPEND_PREPARE (3) +#define MPU_PM_EVENT_POST_SUSPEND (4) + +#define MAX_MPUIRQ_DATA_SIZE (32) + +struct mpuirq_data { + int interruptcount; + unsigned long long irqtime; + int data_type; + int data_size; + void *data; +}; + +enum ext_slave_config_key { + MPU_SLAVE_CONFIG_ODR_SUSPEND, + MPU_SLAVE_CONFIG_ODR_RESUME, + MPU_SLAVE_CONFIG_FSR_SUSPEND, + MPU_SLAVE_CONFIG_FSR_RESUME, + MPU_SLAVE_CONFIG_MOT_THS, + MPU_SLAVE_CONFIG_NMOT_THS, + MPU_SLAVE_CONFIG_MOT_DUR, + MPU_SLAVE_CONFIG_NMOT_DUR, + MPU_SLAVE_CONFIG_IRQ_SUSPEND, + MPU_SLAVE_CONFIG_IRQ_RESUME, + MPU_SLAVE_WRITE_REGISTERS, + MPU_SLAVE_READ_REGISTERS, + MPU_SLAVE_CONFIG_NUM_CONFIG_KEYS, +}; + +/* For the MPU_SLAVE_CONFIG_IRQ_SUSPEND and MPU_SLAVE_CONFIG_IRQ_RESUME */ +enum ext_slave_config_irq_type { + MPU_SLAVE_IRQ_TYPE_NONE, + MPU_SLAVE_IRQ_TYPE_MOTION, + MPU_SLAVE_IRQ_TYPE_DATA_READY, +}; + +/* Structure for the following IOCTS's + * MPU_CONFIG_ACCEL + * MPU_CONFIG_COMPASS + * MPU_CONFIG_PRESSURE + * MPU_GET_CONFIG_ACCEL + * MPU_GET_CONFIG_COMPASS + * MPU_GET_CONFIG_PRESSURE + */ +struct ext_slave_config { + int key; + int len; + int apply; + void *data; +}; + +enum ext_slave_type { + EXT_SLAVE_TYPE_GYROSCOPE, + EXT_SLAVE_TYPE_ACCELEROMETER, + EXT_SLAVE_TYPE_COMPASS, + EXT_SLAVE_TYPE_PRESSURE, + /*EXT_SLAVE_TYPE_TEMPERATURE */ +}; + +enum ext_slave_id { + ID_INVALID = 0, + + ACCEL_ID_LIS331, + ACCEL_ID_LSM303, + ACCEL_ID_LIS3DH, + ACCEL_ID_KXSD9, + ACCEL_ID_KXTF9, + ACCEL_ID_BMA150, + ACCEL_ID_BMA222, + ACCEL_ID_ADI346, + ACCEL_ID_MMA8450, + ACCEL_ID_MMA845X, + ACCEL_ID_MPU6000, + + COMPASS_ID_AKM, + COMPASS_ID_AMI30X, + COMPASS_ID_AMI306, + COMPASS_ID_YAS529, + COMPASS_ID_YAS530, + COMPASS_ID_HMC5883, + COMPASS_ID_LSM303, + COMPASS_ID_MMC314X, + COMPASS_ID_HSCDTD002B, + COMPASS_ID_HSCDTD004A, + + PRESSURE_ID_BMA085, +}; + +enum ext_slave_endian { + EXT_SLAVE_BIG_ENDIAN, + EXT_SLAVE_LITTLE_ENDIAN, + EXT_SLAVE_FS8_BIG_ENDIAN, + EXT_SLAVE_FS16_BIG_ENDIAN, +}; + +enum ext_slave_bus { + EXT_SLAVE_BUS_INVALID = -1, + EXT_SLAVE_BUS_PRIMARY = 0, + EXT_SLAVE_BUS_SECONDARY = 1 +}; + + +/** + * struct ext_slave_platform_data - Platform data for mpu3050 slave devices + * + * @get_slave_descr: Function pointer to retrieve the struct ext_slave_descr + * for this slave + * @irq: the irq number attached to the slave if any. + * @adapt_num: the I2C adapter number. + * @bus: the bus the slave is attached to: enum ext_slave_bus + * @address: the I2C slave address of the slave device. + * @orientation: the mounting matrix of the device relative to MPU. + * @irq_data: private data for the slave irq handler + * @private_data: additional data, user customizable. Not touched by the MPU + * driver. + * + * The orientation matricies are 3x3 rotation matricies + * that are applied to the data to rotate from the mounting orientation to the + * platform orientation. The values must be one of 0, 1, or -1 and each row and + * column should have exactly 1 non-zero value. + */ +struct ext_slave_platform_data { + struct ext_slave_descr *(*get_slave_descr) (void); + int irq; + int adapt_num; + int bus; + unsigned char address; + signed char orientation[9]; + void *irq_data; + void *private_data; +}; + + +struct tFixPntRange { + long mantissa; + long fraction; +}; + +/** + * struct ext_slave_descr - Description of the slave device for programming. + * + * @suspend: function pointer to put the device in suspended state + * @resume: function pointer to put the device in running state + * @read: function that reads the device data + * @init: function used to preallocate memory used by the driver + * @exit: function used to free memory allocated for the driver + * @config: function used to configure the device + * @get_config:function used to get the device's configuration + * + * @name: text name of the device + * @type: device type. enum ext_slave_type + * @id: enum ext_slave_id + * @reg: starting register address to retrieve data. + * @len: length in bytes of the sensor data. Should be 6. + * @endian: byte order of the data. enum ext_slave_endian + * @range: full scale range of the slave ouput: struct tFixPntRange + * + * Defines the functions and information about the slave the mpu3050 needs to + * use the slave device. + */ +struct ext_slave_descr { + int (*init) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*exit) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*suspend) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*resume) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*read) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata, + unsigned char *data); + int (*config) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata, + struct ext_slave_config *config); + int (*get_config) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata, + struct ext_slave_config *config); + + char *name; + unsigned char type; + unsigned char id; + unsigned char reg; + unsigned int len; + unsigned char endian; + struct tFixPntRange range; +}; + +/** + * struct mpu3050_platform_data - Platform data for the mpu3050 driver + * @int_config: Bits [7:3] of the int config register. + * @orientation: Orientation matrix of the gyroscope + * @level_shifter: 0: VLogic, 1: VDD + * @accel: Accel platform data + * @compass: Compass platform data + * @pressure: Pressure platform data + * + * Contains platform specific information on how to configure the MPU3050 to + * work on this platform. The orientation matricies are 3x3 rotation matricies + * that are applied to the data to rotate from the mounting orientation to the + * platform orientation. The values must be one of 0, 1, or -1 and each row and + * column should have exactly 1 non-zero value. + */ +struct mpu3050_platform_data { + unsigned char int_config; + signed char orientation[MPU_NUM_AXES * MPU_NUM_AXES]; + unsigned char level_shifter; + struct ext_slave_platform_data accel; + struct ext_slave_platform_data compass; + struct ext_slave_platform_data pressure; +}; + + +/* + Accelerometer +*/ +#define get_accel_slave_descr NULL + +#ifdef CONFIG_MPU_SENSORS_ADXL346 /* ADI accelerometer */ +struct ext_slave_descr *adxl346_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr adxl346_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_BMA150 /* Bosch accelerometer */ +struct ext_slave_descr *bma150_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr bma150_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_BMA222 /* Bosch 222 accelerometer */ +struct ext_slave_descr *bma222_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr bma222_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_KXSD9 /* Kionix accelerometer */ +struct ext_slave_descr *kxsd9_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr kxsd9_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_KXTF9 /* Kionix accelerometer */ +struct ext_slave_descr *kxtf9_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr kxtf9_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_LIS331DLH /* ST accelerometer */ +struct ext_slave_descr *lis331dlh_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr lis331dlh_get_slave_descr +#endif + + +#ifdef CONFIG_MPU_SENSORS_LIS3DH /* ST accelerometer */ +struct ext_slave_descr *lis3dh_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr lis3dh_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_LSM303DLHA /* ST accelerometer */ +struct ext_slave_descr *lsm303dlha_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr lsm303dlha_get_slave_descr +#endif + +/* MPU6000 Accel */ +#if defined(CONFIG_MPU_SENSORS_MPU6000) || \ + defined(CONFIG_MPU_SENSORS_MPU6000_MODULE) +struct ext_slave_descr *mantis_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr mantis_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_MMA8450 /* Freescale accelerometer */ +struct ext_slave_descr *mma8450_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr mma8450_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_MMA845X /* Freescale accelerometer */ +struct ext_slave_descr *mma845x_get_slave_descr(void); +#undef get_accel_slave_descr +#define get_accel_slave_descr mma845x_get_slave_descr +#endif + + +/* + Compass +*/ +#define get_compass_slave_descr NULL + +#ifdef CONFIG_MPU_SENSORS_AK8975 /* AKM compass */ +struct ext_slave_descr *ak8975_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr ak8975_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_AMI30X /* AICHI Steel AMI304/305 compass */ +struct ext_slave_descr *ami30x_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr ami30x_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_AMI306 /* AICHI Steel AMI306 compass */ +struct ext_slave_descr *ami306_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr ami306_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_HMC5883 /* Honeywell compass */ +struct ext_slave_descr *hmc5883_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr hmc5883_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_MMC314X /* MEMSIC compass */ +struct ext_slave_descr *mmc314x_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr mmc314x_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_LSM303DLHM /* ST compass */ +struct ext_slave_descr *lsm303dlhm_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr lsm303dlhm_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_YAS529 /* Yamaha compass */ +struct ext_slave_descr *yas529_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr yas529_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_YAS530 /* Yamaha compass */ +struct ext_slave_descr *yas530_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr yas530_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_HSCDTD002B /* Alps HSCDTD002B compass */ +struct ext_slave_descr *hscdtd002b_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr hscdtd002b_get_slave_descr +#endif + +#ifdef CONFIG_MPU_SENSORS_HSCDTD004A /* Alps HSCDTD004A compass */ +struct ext_slave_descr *hscdtd004a_get_slave_descr(void); +#undef get_compass_slave_descr +#define get_compass_slave_descr hscdtd004a_get_slave_descr +#endif +/* + Pressure +*/ +#define get_pressure_slave_descr NULL + +#ifdef CONFIG_MPU_SENSORS_BMA085 /* BMA pressure */ +struct ext_slave_descr *bma085_get_slave_descr(void); +#undef get_pressure_slave_descr +#define get_pressure_slave_descr bma085_get_slave_descr +#endif + +#endif /* __MPU_H_ */ diff --git a/include/linux/mpu3050.h b/include/linux/mpu3050.h new file mode 100644 index 000000000000..a8dcd5a9473f --- /dev/null +++ b/include/linux/mpu3050.h @@ -0,0 +1,255 @@ +/* + $License: + Copyright (C) 2010 InvenSense Corporation, All Rights Reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. + $ + */ + +#ifndef __MPU3050_H_ +#define __MPU3050_H_ + +#ifdef __KERNEL__ +#include <linux/types.h> +#endif + +#ifdef M_HW +#error MPU6000 build including MPU3050 header +#endif + +#define MPU_NAME "mpu3050" +#define DEFAULT_MPU_SLAVEADDR 0x68 + +/*==== MPU REGISTER SET ====*/ +enum mpu_register { + MPUREG_WHO_AM_I = 0, /* 00 0x00 */ + MPUREG_PRODUCT_ID, /* 01 0x01 */ + MPUREG_02_RSVD, /* 02 0x02 */ + MPUREG_03_RSVD, /* 03 0x03 */ + MPUREG_04_RSVD, /* 04 0x04 */ + MPUREG_XG_OFFS_TC, /* 05 0x05 */ + MPUREG_06_RSVD, /* 06 0x06 */ + MPUREG_07_RSVD, /* 07 0x07 */ + MPUREG_YG_OFFS_TC, /* 08 0x08 */ + MPUREG_09_RSVD, /* 09 0x09 */ + MPUREG_0A_RSVD, /* 10 0x0a */ + MPUREG_ZG_OFFS_TC, /* 11 0x0b */ + MPUREG_X_OFFS_USRH, /* 12 0x0c */ + MPUREG_X_OFFS_USRL, /* 13 0x0d */ + MPUREG_Y_OFFS_USRH, /* 14 0x0e */ + MPUREG_Y_OFFS_USRL, /* 15 0x0f */ + MPUREG_Z_OFFS_USRH, /* 16 0x10 */ + MPUREG_Z_OFFS_USRL, /* 17 0x11 */ + MPUREG_FIFO_EN1, /* 18 0x12 */ + MPUREG_FIFO_EN2, /* 19 0x13 */ + MPUREG_AUX_SLV_ADDR, /* 20 0x14 */ + MPUREG_SMPLRT_DIV, /* 21 0x15 */ + MPUREG_DLPF_FS_SYNC, /* 22 0x16 */ + MPUREG_INT_CFG, /* 23 0x17 */ + MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */ + MPUREG_19_RSVD, /* 25 0x19 */ + MPUREG_INT_STATUS, /* 26 0x1a */ + MPUREG_TEMP_OUT_H, /* 27 0x1b */ + MPUREG_TEMP_OUT_L, /* 28 0x1c */ + MPUREG_GYRO_XOUT_H, /* 29 0x1d */ + MPUREG_GYRO_XOUT_L, /* 30 0x1e */ + MPUREG_GYRO_YOUT_H, /* 31 0x1f */ + MPUREG_GYRO_YOUT_L, /* 32 0x20 */ + MPUREG_GYRO_ZOUT_H, /* 33 0x21 */ + MPUREG_GYRO_ZOUT_L, /* 34 0x22 */ + MPUREG_23_RSVD, /* 35 0x23 */ + MPUREG_24_RSVD, /* 36 0x24 */ + MPUREG_25_RSVD, /* 37 0x25 */ + MPUREG_26_RSVD, /* 38 0x26 */ + MPUREG_27_RSVD, /* 39 0x27 */ + MPUREG_28_RSVD, /* 40 0x28 */ + MPUREG_29_RSVD, /* 41 0x29 */ + MPUREG_2A_RSVD, /* 42 0x2a */ + MPUREG_2B_RSVD, /* 43 0x2b */ + MPUREG_2C_RSVD, /* 44 0x2c */ + MPUREG_2D_RSVD, /* 45 0x2d */ + MPUREG_2E_RSVD, /* 46 0x2e */ + MPUREG_2F_RSVD, /* 47 0x2f */ + MPUREG_30_RSVD, /* 48 0x30 */ + MPUREG_31_RSVD, /* 49 0x31 */ + MPUREG_32_RSVD, /* 50 0x32 */ + MPUREG_33_RSVD, /* 51 0x33 */ + MPUREG_34_RSVD, /* 52 0x34 */ + MPUREG_DMP_CFG_1, /* 53 0x35 */ + MPUREG_DMP_CFG_2, /* 54 0x36 */ + MPUREG_BANK_SEL, /* 55 0x37 */ + MPUREG_MEM_START_ADDR, /* 56 0x38 */ + MPUREG_MEM_R_W, /* 57 0x39 */ + MPUREG_FIFO_COUNTH, /* 58 0x3a */ + MPUREG_FIFO_COUNTL, /* 59 0x3b */ + MPUREG_FIFO_R_W, /* 60 0x3c */ + MPUREG_USER_CTRL, /* 61 0x3d */ + MPUREG_PWR_MGM, /* 62 0x3e */ + MPUREG_3F_RSVD, /* 63 0x3f */ + NUM_OF_MPU_REGISTERS /* 64 0x40 */ +}; + +/*==== BITS FOR MPU ====*/ + +/*---- MPU 'FIFO_EN1' register (12) ----*/ +#define BIT_TEMP_OUT 0x80 +#define BIT_GYRO_XOUT 0x40 +#define BIT_GYRO_YOUT 0x20 +#define BIT_GYRO_ZOUT 0x10 +#define BIT_ACCEL_XOUT 0x08 +#define BIT_ACCEL_YOUT 0x04 +#define BIT_ACCEL_ZOUT 0x02 +#define BIT_AUX_1OUT 0x01 +/*---- MPU 'FIFO_EN2' register (13) ----*/ +#define BIT_AUX_2OUT 0x02 +#define BIT_AUX_3OUT 0x01 +/*---- MPU 'DLPF_FS_SYNC' register (16) ----*/ +#define BITS_EXT_SYNC_NONE 0x00 +#define BITS_EXT_SYNC_TEMP 0x20 +#define BITS_EXT_SYNC_GYROX 0x40 +#define BITS_EXT_SYNC_GYROY 0x60 +#define BITS_EXT_SYNC_GYROZ 0x80 +#define BITS_EXT_SYNC_ACCELX 0xA0 +#define BITS_EXT_SYNC_ACCELY 0xC0 +#define BITS_EXT_SYNC_ACCELZ 0xE0 +#define BITS_EXT_SYNC_MASK 0xE0 +#define BITS_FS_250DPS 0x00 +#define BITS_FS_500DPS 0x08 +#define BITS_FS_1000DPS 0x10 +#define BITS_FS_2000DPS 0x18 +#define BITS_FS_MASK 0x18 +#define BITS_DLPF_CFG_256HZ_NOLPF2 0x00 +#define BITS_DLPF_CFG_188HZ 0x01 +#define BITS_DLPF_CFG_98HZ 0x02 +#define BITS_DLPF_CFG_42HZ 0x03 +#define BITS_DLPF_CFG_20HZ 0x04 +#define BITS_DLPF_CFG_10HZ 0x05 +#define BITS_DLPF_CFG_5HZ 0x06 +#define BITS_DLPF_CFG_2100HZ_NOLPF 0x07 +#define BITS_DLPF_CFG_MASK 0x07 +/*---- MPU 'INT_CFG' register (17) ----*/ +#define BIT_ACTL 0x80 +#define BIT_ACTL_LOW 0x80 +#define BIT_ACTL_HIGH 0x00 +#define BIT_OPEN 0x40 +#define BIT_OPEN_DRAIN 0x40 +#define BIT_PUSH_PULL 0x00 +#define BIT_LATCH_INT_EN 0x20 +#define BIT_LATCH_INT_EN 0x20 +#define BIT_INT_PULSE_WIDTH_50US 0x00 +#define BIT_INT_ANYRD_2CLEAR 0x10 +#define BIT_INT_STAT_READ_2CLEAR 0x00 +#define BIT_MPU_RDY_EN 0x04 +#define BIT_DMP_INT_EN 0x02 +#define BIT_RAW_RDY_EN 0x01 +/*---- MPU 'INT_STATUS' register (1A) ----*/ +#define BIT_INT_STATUS_FIFO_OVERLOW 0x80 +#define BIT_MPU_RDY 0x04 +#define BIT_DMP_INT 0x02 +#define BIT_RAW_RDY 0x01 +/*---- MPU 'BANK_SEL' register (37) ----*/ +#define BIT_PRFTCH_EN 0x20 +#define BIT_CFG_USER_BANK 0x10 +#define BITS_MEM_SEL 0x0f +/*---- MPU 'USER_CTRL' register (3D) ----*/ +#define BIT_DMP_EN 0x80 +#define BIT_FIFO_EN 0x40 +#define BIT_AUX_IF_EN 0x20 +#define BIT_AUX_RD_LENG 0x10 +#define BIT_AUX_IF_RST 0x08 +#define BIT_DMP_RST 0x04 +#define BIT_FIFO_RST 0x02 +#define BIT_GYRO_RST 0x01 +/*---- MPU 'PWR_MGM' register (3E) ----*/ +#define BIT_H_RESET 0x80 +#define BIT_SLEEP 0x40 +#define BIT_STBY_XG 0x20 +#define BIT_STBY_YG 0x10 +#define BIT_STBY_ZG 0x08 +#define BITS_CLKSEL 0x07 + +/*---- MPU Silicon Revision ----*/ +#define MPU_SILICON_REV_A4 1 /* MPU A4 Device */ +#define MPU_SILICON_REV_B1 2 /* MPU B1 Device */ +#define MPU_SILICON_REV_B4 3 /* MPU B4 Device */ +#define MPU_SILICON_REV_B6 4 /* MPU B6 Device */ + +/*---- MPU Memory ----*/ +#define MPU_MEM_BANK_SIZE (256) +#define FIFO_HW_SIZE (512) + +enum MPU_MEMORY_BANKS { + MPU_MEM_RAM_BANK_0 = 0, + MPU_MEM_RAM_BANK_1, + MPU_MEM_RAM_BANK_2, + MPU_MEM_RAM_BANK_3, + MPU_MEM_NUM_RAM_BANKS, + MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS, + /* This one is always last */ + MPU_MEM_NUM_BANKS +}; + +#define MPU_NUM_AXES (3) + +/*---- structure containing control variables used by MLDL ----*/ +/*---- MPU clock source settings ----*/ +/*---- MPU filter selections ----*/ +enum mpu_filter { + MPU_FILTER_256HZ_NOLPF2 = 0, + MPU_FILTER_188HZ, + MPU_FILTER_98HZ, + MPU_FILTER_42HZ, + MPU_FILTER_20HZ, + MPU_FILTER_10HZ, + MPU_FILTER_5HZ, + MPU_FILTER_2100HZ_NOLPF, + NUM_MPU_FILTER +}; + +enum mpu_fullscale { + MPU_FS_250DPS = 0, + MPU_FS_500DPS, + MPU_FS_1000DPS, + MPU_FS_2000DPS, + NUM_MPU_FS +}; + +enum mpu_clock_sel { + MPU_CLK_SEL_INTERNAL = 0, + MPU_CLK_SEL_PLLGYROX, + MPU_CLK_SEL_PLLGYROY, + MPU_CLK_SEL_PLLGYROZ, + MPU_CLK_SEL_PLLEXT32K, + MPU_CLK_SEL_PLLEXT19M, + MPU_CLK_SEL_RESERVED, + MPU_CLK_SEL_STOP, + NUM_CLK_SEL +}; + +enum mpu_ext_sync { + MPU_EXT_SYNC_NONE = 0, + MPU_EXT_SYNC_TEMP, + MPU_EXT_SYNC_GYROX, + MPU_EXT_SYNC_GYROY, + MPU_EXT_SYNC_GYROZ, + MPU_EXT_SYNC_ACCELX, + MPU_EXT_SYNC_ACCELY, + MPU_EXT_SYNC_ACCELZ, + NUM_MPU_EXT_SYNC +}; + +#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \ + ((ext_sync << 5) | (full_scale << 3) | lpf) + +#endif /* __MPU3050_H_ */ diff --git a/include/linux/mpu6000.h b/include/linux/mpu6000.h new file mode 100644 index 000000000000..5a63c8f07b70 --- /dev/null +++ b/include/linux/mpu6000.h @@ -0,0 +1,406 @@ +/* + $License: + Copyright (C) 2010 InvenSense Corporation, All Rights Reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. + $ + */ + +/** + * @defgroup + * @brief + * + * @{ + * @file mpu6000.h + * @brief + */ + +#ifndef __MPU6000_H_ +#define __MPU6000_H_ + +#define MPU_NAME "mpu6000" +#define DEFAULT_MPU_SLAVEADDR 0x68 + +/*==== M_HW REGISTER SET ====*/ +enum { + MPUREG_XG_OFFS_TC = 0, /* 0x00 */ + MPUREG_YG_OFFS_TC, /* 0x00 */ + MPUREG_ZG_OFFS_TC, /* 0x00 */ + MPUREG_X_FINE_GAIN, /* 0x00 */ + MPUREG_Y_FINE_GAIN, /* 0x00 */ + MPUREG_Z_FINE_GAIN, /* 0x00 */ + MPUREG_XA_OFFS_H, /* 0x00 */ + MPUREG_XA_OFFS_L_TC, /* 0x00 */ + MPUREG_YA_OFFS_H, /* 0x00 */ + MPUREG_YA_OFFS_L_TC, /* 0x00 */ + MPUREG_ZA_OFFS_H, /* 0x00 */ + MPUREG_ZA_OFFS_L_TC, /* 0xB */ + MPUREG_0C_RSVD, /* 0x00 */ + MPUREG_0D_RSVD, /* 0x00 */ + MPUREG_0E_RSVD, /* 0x00 */ + MPUREG_0F_RSVD, /* 0x00 */ + MPUREG_10_RSVD, /* 0x00 */ + MPUREG_11_RSVD, /* 0x00 */ + MPUREG_12_RSVD, /* 0x00 */ + MPUREG_XG_OFFS_USRH, /* 0x00 */ + MPUREG_XG_OFFS_USRL, /* 0x00 */ + MPUREG_YG_OFFS_USRH, /* 0x00 */ + MPUREG_YG_OFFS_USRL, /* 0x00 */ + MPUREG_ZG_OFFS_USRH, /* 0x00 */ + MPUREG_ZG_OFFS_USRL, /* 0x00 */ + MPUREG_SMPLRT_DIV, /* 0x19 */ + MPUREG_CONFIG, /* 0x1A ==> DLPF_FS_SYNC */ + MPUREG_GYRO_CONFIG, /* 0x00 */ + MPUREG_ACCEL_CONFIG, /* 0x00 */ + MPUREG_ACCEL_FF_THR, /* 0x00 */ + MPUREG_ACCEL_FF_DUR, /* 0x00 */ + MPUREG_ACCEL_MOT_THR, /* 0x00 */ + MPUREG_ACCEL_MOT_DUR, /* 0x00 */ + MPUREG_ACCEL_ZRMOT_THR, /* 0x00 */ + MPUREG_ACCEL_ZRMOT_DUR, /* 0x00 */ + MPUREG_FIFO_EN, /* 0x23 */ + MPUREG_I2C_MST_CTRL, /* 0x00 */ + MPUREG_I2C_SLV0_ADDR, /* 0x25 */ + MPUREG_I2C_SLV0_REG, /* 0x00 */ + MPUREG_I2C_SLV0_CTRL, /* 0x00 */ + MPUREG_I2C_SLV1_ADDR, /* 0x28 */ + MPUREG_I2C_SLV1_REG_PASSWORD, /* 0x00 */ + MPUREG_I2C_SLV1_CTRL, /* 0x00 */ + MPUREG_I2C_SLV2_ADDR, /* 0x2B */ + MPUREG_I2C_SLV2_REG, /* 0x00 */ + MPUREG_I2C_SLV2_CTRL, /* 0x00 */ + MPUREG_I2C_SLV3_ADDR, /* 0x2E */ + MPUREG_I2C_SLV3_REG, /* 0x00 */ + MPUREG_I2C_SLV3_CTRL, /* 0x00 */ + MPUREG_I2C_SLV4_ADDR, /* 0x31 */ + MPUREG_I2C_SLV4_REG, /* 0x00 */ + MPUREG_I2C_SLV4_DO, /* 0x00 */ + MPUREG_I2C_SLV4_CTRL, /* 0x00 */ + MPUREG_I2C_SLV4_DI, /* 0x00 */ + MPUREG_I2C_MST_STATUS, /* 0x36 */ + MPUREG_INT_PIN_CFG, /* 0x37 ==> -* INT_CFG */ + MPUREG_INT_ENABLE, /* 0x38 ==> / */ + MPUREG_DMP_INT_STATUS, /* 0x39 */ + MPUREG_INT_STATUS, /* 0x3A */ + MPUREG_ACCEL_XOUT_H, /* 0x3B */ + MPUREG_ACCEL_XOUT_L, /* 0x00 */ + MPUREG_ACCEL_YOUT_H, /* 0x00 */ + MPUREG_ACCEL_YOUT_L, /* 0x00 */ + MPUREG_ACCEL_ZOUT_H, /* 0x00 */ + MPUREG_ACCEL_ZOUT_L, /* 0x00 */ + MPUREG_TEMP_OUT_H, /* 0x41 */ + MPUREG_TEMP_OUT_L, /* 0x00 */ + MPUREG_GYRO_XOUT_H, /* 0x43 */ + MPUREG_GYRO_XOUT_L, /* 0x00 */ + MPUREG_GYRO_YOUT_H, /* 0x00 */ + MPUREG_GYRO_YOUT_L, /* 0x00 */ + MPUREG_GYRO_ZOUT_H, /* 0x00 */ + MPUREG_GYRO_ZOUT_L, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_00, /* 0x49 */ + MPUREG_EXT_SLV_SENS_DATA_01, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_02, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_03, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_04, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_05, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_06, /* 0x4F */ + MPUREG_EXT_SLV_SENS_DATA_07, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_08, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_09, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_10, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_11, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_12, /* 0x55 */ + MPUREG_EXT_SLV_SENS_DATA_13, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_14, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_15, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_16, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_17, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_18, /* 0x5B */ + MPUREG_EXT_SLV_SENS_DATA_19, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_20, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_21, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_22, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_23, /* 0x00 */ + ACCEL_INTEL_STATUS, /* 0x61 */ + MPUREG_62_RSVD, /* 0x00 */ + MPUREG_63_RSVD, /* 0x00 */ + MPUREG_64_RSVD, /* 0x00 */ + MPUREG_65_RSVD, /* 0x00 */ + MPUREG_66_RSVD, /* 0x00 */ + MPUREG_67_RSVD, /* 0x00 */ + SIGNAL_PATH_RESET, /* 0x68 */ + ACCEL_INTEL_CTRL, /* 0x69 */ + MPUREG_USER_CTRL, /* 0x6A */ + MPUREG_PWR_MGMT_1, /* 0x6B */ + MPUREG_PWR_MGMT_2, /* 0x00 */ + MPUREG_BANK_SEL, /* 0x6D */ + MPUREG_MEM_START_ADDR, /* 0x6E */ + MPUREG_MEM_R_W, /* 0x6F */ + MPUREG_PRGM_STRT_ADDRH, /* 0x00 */ + MPUREG_PRGM_STRT_ADDRL, /* 0x00 */ + MPUREG_FIFO_COUNTH, /* 0x72 */ + MPUREG_FIFO_COUNTL, /* 0x00 */ + MPUREG_FIFO_R_W, /* 0x74 */ + MPUREG_WHOAMI, /* 0x75,117 */ + + NUM_OF_MPU_REGISTERS /* = 0x76,118 */ +}; + +/*==== M_HW MEMORY ====*/ +enum MPU_MEMORY_BANKS { + MEM_RAM_BANK_0 = 0, + MEM_RAM_BANK_1, + MEM_RAM_BANK_2, + MEM_RAM_BANK_3, + MEM_RAM_BANK_4, + MEM_RAM_BANK_5, + MEM_RAM_BANK_6, + MEM_RAM_BANK_7, + MEM_RAM_BANK_8, + MEM_RAM_BANK_9, + MEM_RAM_BANK_10, + MEM_RAM_BANK_11, + MPU_MEM_NUM_RAM_BANKS, + MPU_MEM_OTP_BANK_0 = 16 +}; + + +/*==== M_HW parameters ====*/ + +#define NUM_REGS (NUM_OF_MPU_REGISTERS) +#define START_SENS_REGS (0x3B) +#define NUM_SENS_REGS (0x60-START_SENS_REGS+1) + +/*---- MPU Memory ----*/ +#define NUM_BANKS (MPU_MEM_NUM_RAM_BANKS) +#define BANK_SIZE (256) +#define MEM_SIZE (NUM_BANKS*BANK_SIZE) +#define MPU_MEM_BANK_SIZE (BANK_SIZE) /*alternative name */ + +#define FIFO_HW_SIZE (1024) + +#define NUM_EXT_SLAVES (4) + + +/*==== BITS FOR M_HW ====*/ + +/*---- M_HW 'FIFO_EN' register (23) ----*/ +#define BIT_TEMP_OUT 0x80 +#define BIT_GYRO_XOUT 0x40 +#define BIT_GYRO_YOUT 0x20 +#define BIT_GYRO_ZOUT 0x10 +#define BIT_ACCEL 0x08 +#define BIT_SLV_2 0x04 +#define BIT_SLV_1 0x02 +#define BIT_SLV_0 0x01 +/*---- M_HW 'CONFIG' register (1A) ----*/ +/*NONE 0xC0 */ +#define BITS_EXT_SYNC_SET 0x38 +#define BITS_DLPF_CFG 0x07 +/*---- M_HW 'GYRO_CONFIG' register (1B) ----*/ +/* voluntarily modified label from BITS_FS_SEL to + * BITS_GYRO_FS_SEL to avoid confusion with MPU + */ +#define BITS_GYRO_FS_SEL 0x18 +/*NONE 0x07 */ +/*---- M_HW 'ACCEL_CONFIG' register (1C) ----*/ +#define BITS_ACCEL_FS_SEL 0x18 +#define BITS_ACCEL_HPF 0x07 +/*---- M_HW 'I2C_MST_CTRL' register (24) ----*/ +#define BIT_MULT_MST_DIS 0x80 +#define BIT_WAIT_FOR_ES 0x40 +#define BIT_I2C_MST_VDDIO 0x20 +/*NONE 0x10 */ +#define BITS_I2C_MST_CLK 0x0F +/*---- M_HW 'I2C_SLV?_CTRL' register (27,2A,2D,30) ----*/ +#define BIT_SLV_ENABLE 0x80 +#define BIT_SLV_BYTE_SW 0x40 +/*NONE 0x20 */ +#define BIT_SLV_GRP 0x10 +#define BITS_SLV_LENG 0x0F +/*---- M_HW 'I2C_SLV4_ADDR' register (31) ----*/ +#define BIT_I2C_SLV4_RNW 0x80 +/*---- M_HW 'I2C_SLV4_CTRL' register (34) ----*/ +#define BIT_I2C_SLV4_EN 0x80 +#define BIT_SLV4_DONE_INT_EN 0x40 +/*NONE 0x3F */ +/*---- M_HW 'I2C_MST_STATUS' register (36) ----*/ +#define BIT_PASSTHROUGH 0x80 +#define BIT_I2C_SLV4_DONE 0x40 +#define BIT_I2C_LOST_ARB 0x20 +#define BIT_I2C_SLV4_NACK 0x10 +#define BIT_I2C_SLV3_NACK 0x08 +#define BIT_I2C_SLV2_NACK 0x04 +#define BIT_I2C_SLV1_NACK 0x02 +#define BIT_I2C_SLV0_NACK 0x01 +/*---- M_HW 'INT_PIN_CFG' register (37) ----*/ +#define BIT_ACTL 0x80 +#define BIT_ACTL_LOW 0x80 +#define BIT_ACTL_HIGH 0x00 +#define BIT_OPEN 0x40 +#define BIT_LATCH_INT_EN 0x20 +#define BIT_INT_ANYRD_2CLEAR 0x10 +#define BIT_ACTL_FSYNC 0x08 +#define BIT_FSYNC_INT_EN 0x04 +#define BIT_BYPASS_EN 0x02 +#define BIT_CLKOUT_EN 0x01 +/*---- M_HW 'INT_ENABLE' register (38) ----*/ +#define BIT_FF_EN 0x80 +#define BIT_MOT_EN 0x40 +#define BIT_ZMOT_EN 0x20 +#define BIT_FIFO_OVERFLOW_EN 0x10 +#define BIT_I2C_MST_INT_EN 0x08 +#define BIT_PLL_RDY_EN 0x04 +#define BIT_DMP_INT_EN 0x02 +#define BIT_RAW_RDY_EN 0x01 +/*---- M_HW 'DMP_INT_STATUS' register (39) ----*/ +/*NONE 0x80 */ +/*NONE 0x40 */ +#define BIT_DMP_INT_5 0x20 +#define BIT_DMP_INT_4 0x10 +#define BIT_DMP_INT_3 0x08 +#define BIT_DMP_INT_2 0x04 +#define BIT_DMP_INT_1 0x02 +#define BIT_DMP_INT_0 0x01 +/*---- M_HW 'INT_STATUS' register (3A) ----*/ +#define BIT_FF_INT 0x80 +#define BIT_MOT_INT 0x40 +#define BIT_ZMOT_INT 0x20 +#define BIT_FIFO_OVERFLOW_INT 0x10 +#define BIT_I2C_MST_INT 0x08 +#define BIT_PLL_RDY_INT 0x04 +#define BIT_DMP_INT 0x02 +#define BIT_RAW_DATA_RDY_INT 0x01 +/*---- M_HW 'BANK_SEL' register (6D) ----*/ +#define BIT_PRFTCH_EN 0x40 +#define BIT_CFG_USER_BANK 0x20 +#define BITS_MEM_SEL 0x1f +/*---- M_HW 'USER_CTRL' register (6A) ----*/ +#define BIT_DMP_EN 0x80 +#define BIT_FIFO_EN 0x40 +#define BIT_I2C_MST_EN 0x20 +#define BIT_I2C_IF_DIS 0x10 +#define BIT_DMP_RST 0x08 +#define BIT_FIFO_RST 0x04 +#define BIT_I2C_MST_RST 0x02 +#define BIT_SIG_COND_RST 0x01 +/*---- M_HW 'PWR_MGMT_1' register (6B) ----*/ +#define BIT_H_RESET 0x80 +#define BITS_PWRSEL 0x70 +#define BIT_WKUP_INT 0x08 +#define BITS_CLKSEL 0x07 +/*---- M_HW 'PWR_MGMT_2' register (6C) ----*/ +#define BITS_LPA_WAKE_CTRL 0xC0 +#define BIT_STBY_XA 0x20 +#define BIT_STBY_YA 0x10 +#define BIT_STBY_ZA 0x08 +#define BIT_STBY_XG 0x04 +#define BIT_STBY_YG 0x02 +#define BIT_STBY_ZG 0x01 + +/* although it has 6, this refers to the gyros */ +#define MPU_NUM_AXES (3) + +#define ACCEL_MOT_THR_LSB (32) /* mg */ +#define ACCEL_MOT_DUR_LSB (1) +#define ACCEL_ZRMOT_THR_LSB_CONVERSION(mg) ((mg *1000)/255) +#define ACCEL_ZRMOT_DUR_LSB (64) + +/*----------------------------------------------------------------------------*/ +/*---- Alternative names to take care of conflicts with current mpu3050.h ----*/ +/*----------------------------------------------------------------------------*/ + +/*-- registers --*/ +#define MPUREG_DLPF_FS_SYNC MPUREG_CONFIG /* 0x1A */ + +#define MPUREG_PRODUCT_ID MPUREG_WHOAMI /* 0x75 HACK!*/ +#define MPUREG_PWR_MGM MPUREG_PWR_MGMT_1 /* 0x6B */ +#define MPUREG_FIFO_EN1 MPUREG_FIFO_EN /* 0x23 */ +#define MPUREG_DMP_CFG_1 MPUREG_PRGM_STRT_ADDRH /* 0x70 */ +#define MPUREG_DMP_CFG_2 MPUREG_PRGM_STRT_ADDRL /* 0x71 */ +#define MPUREG_INT_CFG MPUREG_INT_ENABLE /* 0x38 */ +#define MPUREG_X_OFFS_USRH MPUREG_XG_OFFS_USRH /* 0x13 */ +#define MPUREG_WHO_AM_I MPUREG_WHOAMI /* 0x75 */ +#define MPUREG_23_RSVD MPUREG_EXT_SLV_SENS_DATA_00 /* 0x49 */ +#define MPUREG_AUX_SLV_ADDR MPUREG_I2C_SLV0_ADDR /* 0x25 */ +#define MPUREG_ACCEL_BURST_ADDR MPUREG_I2C_SLV0_REG /* 0x26 */ + +/*-- bits --*/ +/* 'USER_CTRL' register */ +#define BIT_AUX_IF_EN BIT_I2C_MST_EN +#define BIT_AUX_RD_LENG BIT_I2C_MST_EN +#define BIT_IME_IF_RST BIT_I2C_MST_RST +#define BIT_GYRO_RST BIT_SIG_COND_RST +/* 'INT_ENABLE' register */ +#define BIT_RAW_RDY BIT_RAW_DATA_RDY_INT +#define BIT_MPU_RDY_EN BIT_PLL_RDY_EN +/* 'INT_STATUS' register */ +#define BIT_INT_STATUS_FIFO_OVERLOW BIT_FIFO_OVERFLOW_INT + + + +/*---- M_HW Silicon Revisions ----*/ +#define MPU_SILICON_REV_A1 1 /* M_HW A1 Device */ +#define MPU_SILICON_REV_B1 2 /* M_HW B1 Device */ + +/*---- structure containing control variables used by MLDL ----*/ +/*---- MPU clock source settings ----*/ +/*---- MPU filter selections ----*/ +enum mpu_filter { + MPU_FILTER_256HZ_NOLPF2 = 0, + MPU_FILTER_188HZ, + MPU_FILTER_98HZ, + MPU_FILTER_42HZ, + MPU_FILTER_20HZ, + MPU_FILTER_10HZ, + MPU_FILTER_5HZ, + MPU_FILTER_2100HZ_NOLPF, + NUM_MPU_FILTER +}; + +enum mpu_fullscale { + MPU_FS_250DPS = 0, + MPU_FS_500DPS, + MPU_FS_1000DPS, + MPU_FS_2000DPS, + NUM_MPU_FS +}; + +enum mpu_clock_sel { + MPU_CLK_SEL_INTERNAL = 0, + MPU_CLK_SEL_PLLGYROX, + MPU_CLK_SEL_PLLGYROY, + MPU_CLK_SEL_PLLGYROZ, + MPU_CLK_SEL_PLLEXT32K, + MPU_CLK_SEL_PLLEXT19M, + MPU_CLK_SEL_RESERVED, + MPU_CLK_SEL_STOP, + NUM_CLK_SEL +}; + +enum mpu_ext_sync { + MPU_EXT_SYNC_NONE = 0, + MPU_EXT_SYNC_TEMP, + MPU_EXT_SYNC_GYROX, + MPU_EXT_SYNC_GYROY, + MPU_EXT_SYNC_GYROZ, + MPU_EXT_SYNC_ACCELX, + MPU_EXT_SYNC_ACCELY, + MPU_EXT_SYNC_ACCELZ, + NUM_MPU_EXT_SYNC +}; + +#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \ + ((ext_sync << 5) | (full_scale << 3) | lpf) + +#endif /* __IMU6000_H_ */ diff --git a/include/linux/nct1008.h b/include/linux/nct1008.h index d65693507299..40519883fc5e 100644 --- a/include/linux/nct1008.h +++ b/include/linux/nct1008.h @@ -25,15 +25,21 @@ #include <linux/types.h> +#include <mach/edp.h> + +#define MAX_ZONES 16 + struct nct1008_platform_data { bool supported_hwrev; bool ext_range; u8 conv_rate; u8 offset; u8 hysteresis; - u8 shutdown_ext_limit; - u8 shutdown_local_limit; - u8 throttling_ext_limit; + s8 shutdown_ext_limit; + s8 shutdown_local_limit; + s8 throttling_ext_limit; + s8 thermal_zones[MAX_ZONES]; + u8 thermal_zones_sz; void (*alarm_fn)(bool raised); }; diff --git a/include/linux/nfc/pn544.h b/include/linux/nfc/pn544.h index 7ab8521f2347..9285000dbb46 100644 --- a/include/linux/nfc/pn544.h +++ b/include/linux/nfc/pn544.h @@ -1,97 +1,33 @@ /* - * Driver include for the PN544 NFC chip. + * Copyright (C) 2010 Trusted Logic S.A. * - * Copyright (C) Nokia Corporation - * - * Author: Jari Vanhala <ext-jari.vanhala@nokia.com> - * Contact: Matti Aaltoenn <matti.j.aaltonen@nokia.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef _PN544_H_ -#define _PN544_H_ - -#include <linux/i2c.h> - -#define PN544_DRIVER_NAME "pn544" -#define PN544_MAXWINDOW_SIZE 7 -#define PN544_WINDOW_SIZE 4 -#define PN544_RETRIES 10 -#define PN544_MAX_I2C_TRANSFER 0x0400 -#define PN544_MSG_MAX_SIZE 0x21 /* at normal HCI mode */ - -/* ioctl */ -#define PN544_CHAR_BASE 'P' -#define PN544_IOR(num, dtype) _IOR(PN544_CHAR_BASE, num, dtype) -#define PN544_IOW(num, dtype) _IOW(PN544_CHAR_BASE, num, dtype) -#define PN544_GET_FW_MODE PN544_IOW(1, unsigned int) -#define PN544_SET_FW_MODE PN544_IOW(2, unsigned int) -#define PN544_GET_DEBUG PN544_IOW(3, unsigned int) -#define PN544_SET_DEBUG PN544_IOW(4, unsigned int) - -/* Timing restrictions (ms) */ -#define PN544_RESETVEN_TIME 30 /* 7 */ -#define PN544_PVDDVEN_TIME 0 -#define PN544_VBATVEN_TIME 0 -#define PN544_GPIO4VEN_TIME 0 -#define PN544_WAKEUP_ACK 5 -#define PN544_WAKEUP_GUARD (PN544_WAKEUP_ACK + 1) -#define PN544_INACTIVITY_TIME 1000 -#define PN544_INTERFRAME_DELAY 200 /* us */ -#define PN544_BAUDRATE_CHANGE 150 /* us */ - -/* Debug bits */ -#define PN544_DEBUG_BUF 0x01 -#define PN544_DEBUG_READ 0x02 -#define PN544_DEBUG_WRITE 0x04 -#define PN544_DEBUG_IRQ 0x08 -#define PN544_DEBUG_CALLS 0x10 -#define PN544_DEBUG_MODE 0x20 - -/* Normal (HCI) mode */ -#define PN544_LLC_HCI_OVERHEAD 3 /* header + crc (to length) */ -#define PN544_LLC_MIN_SIZE (1 + PN544_LLC_HCI_OVERHEAD) /* length + */ -#define PN544_LLC_MAX_DATA (PN544_MSG_MAX_SIZE - 2) -#define PN544_LLC_MAX_HCI_SIZE (PN544_LLC_MAX_DATA - 2) +#define PN544_MAGIC 0xE9 -struct pn544_llc_packet { - unsigned char length; /* of rest of packet */ - unsigned char header; - unsigned char data[PN544_LLC_MAX_DATA]; /* includes crc-ccitt */ -}; - -/* Firmware upgrade mode */ -#define PN544_FW_HEADER_SIZE 3 -/* max fw transfer is 1024bytes, but I2C limits it to 0xC0 */ -#define PN544_MAX_FW_DATA (PN544_MAX_I2C_TRANSFER - PN544_FW_HEADER_SIZE) - -struct pn544_fw_packet { - unsigned char command; /* status in answer */ - unsigned char length[2]; /* big-endian order (msf) */ - unsigned char data[PN544_MAX_FW_DATA]; -}; +/* + * PN544 power control via ioctl + * PN544_SET_PWR(0): power off + * PN544_SET_PWR(1): power on + * PN544_SET_PWR(2): reset and power on with firmware download enabled + */ +#define PN544_SET_PWR _IOW(PN544_MAGIC, 0x01, unsigned int) -#ifdef __KERNEL__ -/* board config */ -struct pn544_nfc_platform_data { - int (*request_resources) (struct i2c_client *client); - void (*free_resources) (void); - void (*enable) (int fw); - int (*test) (void); - void (*disable) (void); +struct pn544_i2c_platform_data { + unsigned int irq_gpio; + unsigned int ven_gpio; + unsigned int firm_gpio; }; -#endif /* __KERNEL__ */ - -#endif /* _PN544_H_ */ diff --git a/include/linux/nvhost.h b/include/linux/nvhost.h new file mode 100644 index 000000000000..a1d211de1ef1 --- /dev/null +++ b/include/linux/nvhost.h @@ -0,0 +1,73 @@ +/* + * include/linux/nvhost.h + * + * Tegra graphics host driver + * + * Copyright (c) 2009-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __LINUX_NVHOST_H +#define __LINUX_NVHOST_H + +#include <linux/device.h> +#include <linux/types.h> + +struct nvhost_master; + +struct nvhost_device { + const char *name; + struct device dev; + int id; + u32 num_resources; + struct resource *resource; + + struct nvhost_master *host; +}; + +extern int nvhost_device_register(struct nvhost_device *); +extern void nvhost_device_unregister(struct nvhost_device *); + +extern struct bus_type nvhost_bus_type; + +struct nvhost_driver { + int (*probe)(struct nvhost_device *); + int (*remove)(struct nvhost_device *); + void (*shutdown)(struct nvhost_device *); + int (*suspend)(struct nvhost_device *, pm_message_t state); + int (*resume)(struct nvhost_device *); + struct device_driver driver; +}; + +extern int nvhost_driver_register(struct nvhost_driver *); +extern void nvhost_driver_unregister(struct nvhost_driver *); +extern struct resource *nvhost_get_resource(struct nvhost_device *, + unsigned int, unsigned int); +extern int nvhost_get_irq(struct nvhost_device *, unsigned int); +extern struct resource *nvhost_get_resource_byname(struct nvhost_device *, + unsigned int, const char *); +extern int nvhost_get_irq_byname(struct nvhost_device *, const char *); + +#define to_nvhost_device(x) container_of((x), struct nvhost_device, dev) +#define to_nvhost_driver(drv) (container_of((drv), struct nvhost_driver, \ + driver)) + +#define nvhost_get_drvdata(_dev) dev_get_drvdata(&(_dev)->dev) +#define nvhost_set_drvdata(_dev, data) dev_set_drvdata(&(_dev)->dev, (data)) + +int nvhost_bus_register(struct nvhost_master *host); + +#endif diff --git a/include/linux/nvhost_ioctl.h b/include/linux/nvhost_ioctl.h new file mode 100644 index 000000000000..31ff22f45fb9 --- /dev/null +++ b/include/linux/nvhost_ioctl.h @@ -0,0 +1,196 @@ +/* + * include/linux/nvhost_ioctl.h + * + * Tegra graphics host driver + * + * Copyright (c) 2009-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __LINUX_NVHOST_IOCTL_H +#define __LINUX_NVHOST_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#if !defined(__KERNEL__) +#define __user +#endif + +#define NVHOST_INVALID_SYNCPOINT 0xFFFFFFFF +#define NVHOST_NO_TIMEOUT (-1) +#define NVHOST_NO_CONTEXT 0x0 +#define NVHOST_IOCTL_MAGIC 'H' +#define NVHOST_PRIORITY_LOW 50 +#define NVHOST_PRIORITY_MEDIUM 100 +#define NVHOST_PRIORITY_HIGH 150 + +/* version 0 header (used with write() submit interface) */ +struct nvhost_submit_hdr { + __u32 syncpt_id; + __u32 syncpt_incrs; + __u32 num_cmdbufs; + __u32 num_relocs; +}; + +#define NVHOST_SUBMIT_VERSION_V0 0x0 +#define NVHOST_SUBMIT_VERSION_V1 0x1 +#define NVHOST_SUBMIT_VERSION_MAX_SUPPORTED NVHOST_SUBMIT_VERSION_V1 + +/* version 1 header (used with ioctl() submit interface) */ +struct nvhost_submit_hdr_ext { + __u32 syncpt_id; /* version 0 fields */ + __u32 syncpt_incrs; + __u32 num_cmdbufs; + __u32 num_relocs; + __u32 submit_version; /* version 1 fields */ + __u32 num_waitchks; + __u32 waitchk_mask; + __u32 pad[5]; /* future expansion */ +}; + +struct nvhost_cmdbuf { + __u32 mem; + __u32 offset; + __u32 words; +}; + +struct nvhost_reloc { + __u32 cmdbuf_mem; + __u32 cmdbuf_offset; + __u32 target; + __u32 target_offset; +}; + +struct nvhost_waitchk { + __u32 mem; + __u32 offset; + __u32 syncpt_id; + __u32 thresh; +}; + +struct nvhost_get_param_args { + __u32 value; +}; + +struct nvhost_set_nvmap_fd_args { + __u32 fd; +}; + +struct nvhost_read_3d_reg_args { + __u32 offset; + __u32 value; +}; + +struct nvhost_clk_rate_args { + __u64 rate; +}; + +struct nvhost_set_timeout_args { + __u32 timeout; +}; + +struct nvhost_set_priority_args { + __u32 priority; +}; + +#define NVHOST_IOCTL_CHANNEL_FLUSH \ + _IOR(NVHOST_IOCTL_MAGIC, 1, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_GET_SYNCPOINTS \ + _IOR(NVHOST_IOCTL_MAGIC, 2, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_GET_WAITBASES \ + _IOR(NVHOST_IOCTL_MAGIC, 3, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_GET_MODMUTEXES \ + _IOR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD \ + _IOW(NVHOST_IOCTL_MAGIC, 5, struct nvhost_set_nvmap_fd_args) +#define NVHOST_IOCTL_CHANNEL_NULL_KICKOFF \ + _IOR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_SUBMIT_EXT \ + _IOW(NVHOST_IOCTL_MAGIC, 7, struct nvhost_submit_hdr_ext) +#define NVHOST_IOCTL_CHANNEL_READ_3D_REG \ + _IOWR(NVHOST_IOCTL_MAGIC, 8, struct nvhost_read_3d_reg_args) +#define NVHOST_IOCTL_CHANNEL_GET_CLK_RATE \ + _IOR(NVHOST_IOCTL_MAGIC, 9, struct nvhost_clk_rate_args) +#define NVHOST_IOCTL_CHANNEL_SET_CLK_RATE \ + _IOW(NVHOST_IOCTL_MAGIC, 10, struct nvhost_clk_rate_args) +#define NVHOST_IOCTL_CHANNEL_SET_TIMEOUT \ + _IOW(NVHOST_IOCTL_MAGIC, 11, struct nvhost_set_timeout_args) +#define NVHOST_IOCTL_CHANNEL_GET_TIMEDOUT \ + _IOR(NVHOST_IOCTL_MAGIC, 12, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_SET_PRIORITY \ + _IOW(NVHOST_IOCTL_MAGIC, 13, struct nvhost_set_priority_args) +#define NVHOST_IOCTL_CHANNEL_LAST \ + _IOC_NR(NVHOST_IOCTL_CHANNEL_SET_PRIORITY) +#define NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvhost_submit_hdr_ext) + +struct nvhost_ctrl_syncpt_read_args { + __u32 id; + __u32 value; +}; + +struct nvhost_ctrl_syncpt_incr_args { + __u32 id; +}; + +struct nvhost_ctrl_syncpt_wait_args { + __u32 id; + __u32 thresh; + __s32 timeout; +}; + +struct nvhost_ctrl_syncpt_waitex_args { + __u32 id; + __u32 thresh; + __s32 timeout; + __u32 value; +}; + +struct nvhost_ctrl_module_mutex_args { + __u32 id; + __u32 lock; +}; + +struct nvhost_ctrl_module_regrdwr_args { + __u32 id; + __u32 num_offsets; + __u32 block_size; + __u32 *offsets; + __u32 *values; + __u32 write; +}; + +#define NVHOST_IOCTL_CTRL_SYNCPT_READ \ + _IOWR(NVHOST_IOCTL_MAGIC, 1, struct nvhost_ctrl_syncpt_read_args) +#define NVHOST_IOCTL_CTRL_SYNCPT_INCR \ + _IOW(NVHOST_IOCTL_MAGIC, 2, struct nvhost_ctrl_syncpt_incr_args) +#define NVHOST_IOCTL_CTRL_SYNCPT_WAIT \ + _IOW(NVHOST_IOCTL_MAGIC, 3, struct nvhost_ctrl_syncpt_wait_args) + +#define NVHOST_IOCTL_CTRL_MODULE_MUTEX \ + _IOWR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_ctrl_module_mutex_args) +#define NVHOST_IOCTL_CTRL_MODULE_REGRDWR \ + _IOWR(NVHOST_IOCTL_MAGIC, 5, struct nvhost_ctrl_module_regrdwr_args) + +#define NVHOST_IOCTL_CTRL_SYNCPT_WAITEX \ + _IOWR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_ctrl_syncpt_waitex_args) + +#define NVHOST_IOCTL_CTRL_LAST \ + _IOC_NR(NVHOST_IOCTL_CTRL_SYNCPT_WAITEX) +#define NVHOST_IOCTL_CTRL_MAX_ARG_SIZE \ + sizeof(struct nvhost_ctrl_module_regrdwr_args) + +#endif diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h index 6bca5b569acb..09f32de5c671 100644 --- a/include/linux/platform_data/tegra_usb.h +++ b/include/linux/platform_data/tegra_usb.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010-2011 NVIDIA Corporation * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -21,11 +22,26 @@ enum tegra_usb_operating_modes { TEGRA_USB_OTG, }; +enum tegra_usb_phy_type { + TEGRA_USB_PHY_TYPE_UTMIP = 0, + TEGRA_USB_PHY_TYPE_LINK_ULPI = 1, + TEGRA_USB_PHY_TYPE_NULL_ULPI = 2, + TEGRA_USB_PHY_TYPE_HSIC = 3, + TEGRA_USB_PHY_TYPE_ICUSB = 4, +}; + struct tegra_ehci_platform_data { enum tegra_usb_operating_modes operating_mode; /* power down the phy on bus suspend */ int power_down_on_bus_suspend; + int hotplug; void *phy_config; + enum tegra_usb_phy_type phy_type; +}; + +struct tegra_otg_platform_data { + struct platform_device *ehci_device; + struct tegra_ehci_platform_data *ehci_pdata; }; #endif /* _TEGRA_USB_H_ */ diff --git a/include/linux/power/max8907c-charger.h b/include/linux/power/max8907c-charger.h new file mode 100644 index 000000000000..2cebad768b0d --- /dev/null +++ b/include/linux/power/max8907c-charger.h @@ -0,0 +1,64 @@ +/* linux/power/max8907c-charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MAX8907C_CHARGER_H +#define __LINUX_MAX8907C_CHARGER_H + +/* interrupt */ +#define MAX8907C_VCHG_OVP (1 << 0) +#define MAX8907C_VCHG_F (1 << 1) +#define MAX8907C_VCHG_R (1 << 2) +#define MAX8907C_THM_OK_R (1 << 8) +#define MAX8907C_THM_OK_F (1 << 9) +#define MAX8907C_MBATTLOW_F (1 << 10) +#define MAX8907C_MBATTLOW_R (1 << 11) +#define MAX8907C_CHG_RST (1 << 12) +#define MAX8907C_CHG_DONE (1 << 13) +#define MAX8907C_CHG_TOPOFF (1 << 14) +#define MAX8907C_CHK_TMR_FAULT (1 << 15) + +enum max8907c_charger_topoff_threshold { + MAX8907C_TOPOFF_5PERCENT = 0x00, + MAX8907C_TOPOFF_10PERCENT = 0x01, + MAX8907C_TOPOFF_15PERCENT = 0x02, + MAX8907C_TOPOFF_20PERCENT = 0x03, +}; + +enum max8907c_charger_restart_hysteresis { + MAX8907C_RESTART_100MV = 0x00, + MAX8907C_RESTART_150MV = 0x01, + MAX8907C_RESTART_200MV = 0x02, + MAX8907C_RESTART_FLOAT = 0x03, +}; + +enum max8907c_fast_charging_current { + MAX8907C_FASTCHARGE_90MA = 0x00, + MAX8907C_FASTCHARGE_300MA = 0x01, + MAX8907C_FASTCHARGE_460MA = 0x02, + MAX8907C_FASTCHARGE_600MA = 0x03, + MAX8907C_FASTCHARGE_700MA = 0x04, + MAX8907C_FASTCHARGE_800MA = 0x05, + MAX8907C_FASTCHARGE_900MA = 0x06, + MAX8907C_FASTCHARGE_1000MA = 0x07, +}; + +enum max8907c_fast_charger_time { + MAX8907C_FCHARGE_TM_8H = 0x00, + MAX8907C_FCHARGE_TM_12H = 0x01, + MAX8907C_FCHARGE_TM_16H = 0x02, + MAX8907C_FCHARGE_TM_OFF = 0x03, +}; + +struct max8907c_charger_pdata { + int irq; + enum max8907c_charger_topoff_threshold topoff_threshold; + enum max8907c_charger_restart_hysteresis restart_hysteresis; + enum max8907c_charger_restart_hysteresis fast_charging_current; + enum max8907c_fast_charger_time fast_charger_time; +}; + +#endif diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 60a65cd7e1a0..04e59205dec9 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -78,5 +78,7 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, size_t val_count); int regmap_update_bits(struct regmap *map, unsigned int reg, unsigned int mask, unsigned int val); +int regmap_update_bits_lazy(struct regmap *map, unsigned int reg, + unsigned int mask, unsigned int val); #endif diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index b47771aa5718..24aae2104c08 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -92,6 +92,10 @@ * FORCE_DISABLE Regulator forcibly shut down by software. * VOLTAGE_CHANGE Regulator voltage changed. * DISABLE Regulator was disabled. + * PRE_ENABLE Regulator is to be enabled + * POST_ENABLE Regulator was enabled + * OUT_PRECHANGE Regulator is enabled and its voltage is to be changed + * OUT_POSTCHANGE Regulator is enabled and its voltage was changed * * NOTE: These events can be OR'ed together when passed into handler. */ @@ -104,6 +108,10 @@ #define REGULATOR_EVENT_FORCE_DISABLE 0x20 #define REGULATOR_EVENT_VOLTAGE_CHANGE 0x40 #define REGULATOR_EVENT_DISABLE 0x80 +#define REGULATOR_EVENT_PRE_ENABLE 0x100 +#define REGULATOR_EVENT_POST_ENABLE 0x200 +#define REGULATOR_EVENT_OUT_PRECHANGE 0x400 +#define REGULATOR_EVENT_OUT_POSTCHANGE 0x800 struct regulator; diff --git a/include/linux/regulator/gpio-switch-regulator.h b/include/linux/regulator/gpio-switch-regulator.h new file mode 100644 index 000000000000..68776b93ef00 --- /dev/null +++ b/include/linux/regulator/gpio-switch-regulator.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _GPIO_SWITCH_REGULATOR_H +#define _GPIO_SWITCH_REGULATOR_H + +#include <linux/regulator/machine.h> + +/* + * struct gpio_switch_regulator_subdev_data - Gpio switch regulator subdevice + * data. + * + * Subdevice data to register a gpio regulator switch device driver. + * + * @regulator_name: The name of regulator. + * @input_supply: Input supply name. + * @id: The id of the switch. + * @gpio_nr: Gpio nr which controls this switch. + * @active_low: true if making gpio low makes voltage output enable. + * @init_state: 1 if init_state should be active. + * @voltages: Possible voltages to set at output. The values are in millivolt. + * @n_voltages: Number of voltages. + * @num_consumer_supplies: Number of cosumer supplies. + * @consumer_supplies: List of consumer spllies. + */ +struct gpio_switch_regulator_subdev_data { + const char *regulator_name; + const char *input_supply; + int id; + int gpio_nr; + int active_low; + int pin_group; + int init_state; + int *voltages; + unsigned n_voltages; + struct regulator_consumer_supply *consumer_supplies; + int num_consumer_supplies; + struct regulation_constraints constraints; + int (*enable_rail)(struct gpio_switch_regulator_subdev_data *pdata); + int (*disable_rail)(struct gpio_switch_regulator_subdev_data *pdata); + +}; + +/** + * gpio_switch_regulator_platform_data - platform data for gpio_switch_regulator + * @num_subdevs: number of regulators used + * @subdevs: pointer to regulators used + */ +struct gpio_switch_regulator_platform_data { + int num_subdevs; + struct gpio_switch_regulator_subdev_data **subdevs; +}; + +#endif diff --git a/include/linux/regulator/max77663-regulator.h b/include/linux/regulator/max77663-regulator.h new file mode 100644 index 000000000000..093ca42d4ca7 --- /dev/null +++ b/include/linux/regulator/max77663-regulator.h @@ -0,0 +1,125 @@ +/* + * include/linux/regulator/max77663-regulator.h + * Maxim LDO and Buck regulators driver + * + * Copyright 2011 Maxim Integrated Products, Inc. + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + */ + +#ifndef __LINUX_REGULATOR_MAX77663_REGULATOR_H__ +#define __LINUX_REGULATOR_MAX77663_REGULATOR_H__ + +#include <linux/regulator/machine.h> + +#define max77663_rails(_name) "max77663_"#_name + +enum max77663_regulator_id { + MAX77663_REGULATOR_ID_SD0, + MAX77663_REGULATOR_ID_DVSSD0, + MAX77663_REGULATOR_ID_SD1, + MAX77663_REGULATOR_ID_DVSSD1, + MAX77663_REGULATOR_ID_SD2, + MAX77663_REGULATOR_ID_SD3, + MAX77663_REGULATOR_ID_SD4, + MAX77663_REGULATOR_ID_LDO0, + MAX77663_REGULATOR_ID_LDO1, + MAX77663_REGULATOR_ID_LDO2, + MAX77663_REGULATOR_ID_LDO3, + MAX77663_REGULATOR_ID_LDO4, + MAX77663_REGULATOR_ID_LDO5, + MAX77663_REGULATOR_ID_LDO6, + MAX77663_REGULATOR_ID_LDO7, + MAX77663_REGULATOR_ID_LDO8, + MAX77663_REGULATOR_ID_NR, +}; + +/* FPS Power Up/Down Period */ +enum max77663_regulator_fps_power_period { + FPS_POWER_PERIOD_0, + FPS_POWER_PERIOD_1, + FPS_POWER_PERIOD_2, + FPS_POWER_PERIOD_3, + FPS_POWER_PERIOD_4, + FPS_POWER_PERIOD_5, + FPS_POWER_PERIOD_6, + FPS_POWER_PERIOD_7, + FPS_POWER_PERIOD_DEF = -1, +}; + +/* FPS Time Period */ +enum max77663_regulator_fps_time_period { + FPS_TIME_PERIOD_20US, + FPS_TIME_PERIOD_40US, + FPS_TIME_PERIOD_80US, + FPS_TIME_PERIOD_160US, + FPS_TIME_PERIOD_320US, + FPS_TIME_PERIOD_640US, + FPS_TIME_PERIOD_1280US, + FPS_TIME_PERIOD_2560US, + FPS_TIME_PERIOD_DEF = -1, +}; + +/* FPS Enable Source */ +enum max77663_regulator_fps_en_src { + FPS_EN_SRC_EN0, + FPS_EN_SRC_EN1, + FPS_EN_SRC_SW, + FPS_EN_SRC_RSVD, +}; + +/* FPS Source */ +enum max77663_regulator_fps_src { + FPS_SRC_0, + FPS_SRC_1, + FPS_SRC_2, + FPS_SRC_NONE, + FPS_SRC_DEF = -1, +}; + +/* + * Flags + */ +/* SD0 is controlled by EN2 */ +#define EN2_CTRL_SD0 0x01 + +/* SD Slew Rate */ +#define SD_SLEW_RATE_SLOWEST 0x02 /* 13.75mV/us */ +#define SD_SLEW_RATE_SLOW 0x04 /* 27.50mV/us */ +#define SD_SLEW_RATE_FAST 0x08 /* 55.00mV/us */ +#define SD_SLEW_RATE_FASTEST 0x10 /* 100.00mV/us */ +#define SD_SLEW_RATE_MASK 0x1E + +/* SD Forced PWM Mode */ +#define SD_FORCED_PWM_MODE 0x20 + +/* SD Failling Slew Rate Active-Discharge Mode */ +#define SD_FSRADE_DISABLE 0x40 + +struct max77663_regulator_fps_cfg { + enum max77663_regulator_fps_src src; + enum max77663_regulator_fps_en_src en_src; + enum max77663_regulator_fps_time_period time_period; +}; + +struct max77663_regulator_platform_data { + struct regulator_init_data init_data; + bool init_apply; + bool init_enable; + int init_uV; + enum max77663_regulator_fps_src fps_src; + enum max77663_regulator_fps_power_period fps_pu_period; + enum max77663_regulator_fps_power_period fps_pd_period; + + int num_fps_cfgs; + struct max77663_regulator_fps_cfg *fps_cfgs; + + unsigned int flags; +}; + +#endif /* __LINUX_REGULATOR_MAX77663_REGULATOR_H__ */ diff --git a/include/linux/regulator/max8907c-regulator.h b/include/linux/regulator/max8907c-regulator.h new file mode 100644 index 000000000000..ddc5f0a60339 --- /dev/null +++ b/include/linux/regulator/max8907c-regulator.h @@ -0,0 +1,46 @@ +/* linux/regulator/max8907c-regulator.h + * + * Functions to access MAX8907C power management chip. + * + * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_REGULATOR_MAX8907C_H +#define __LINUX_REGULATOR_MAX8907C_H + +/* IDs */ +#define MAX8907C_SD1 0 +#define MAX8907C_SD2 1 +#define MAX8907C_SD3 2 +#define MAX8907C_LDO1 3 +#define MAX8907C_LDO2 4 +#define MAX8907C_LDO3 5 +#define MAX8907C_LDO4 6 +#define MAX8907C_LDO5 7 +#define MAX8907C_LDO6 8 +#define MAX8907C_LDO7 9 +#define MAX8907C_LDO8 10 +#define MAX8907C_LDO9 11 +#define MAX8907C_LDO10 12 +#define MAX8907C_LDO11 13 +#define MAX8907C_LDO12 14 +#define MAX8907C_LDO13 15 +#define MAX8907C_LDO14 16 +#define MAX8907C_LDO15 17 +#define MAX8907C_LDO16 18 +#define MAX8907C_LDO17 19 +#define MAX8907C_LDO18 20 +#define MAX8907C_LDO19 21 +#define MAX8907C_LDO20 22 +#define MAX8907C_OUT5V 23 +#define MAX8907C_OUT33V 24 +#define MAX8907C_BBAT 25 +#define MAX8907C_SDBY 26 +#define MAX8907C_VRTC 27 +#define MAX8907C_WLED 27 + +#endif diff --git a/include/linux/regulator/ricoh583-regulator.h b/include/linux/regulator/ricoh583-regulator.h new file mode 100644 index 000000000000..39fdb9e56e05 --- /dev/null +++ b/include/linux/regulator/ricoh583-regulator.h @@ -0,0 +1,63 @@ +/* + * linux/regulator/ricoh583-regulator.h + * + * Interface for regulator driver for RICOH583 power management chip. + * + * Copyright (C) 2011 NVIDIA Corporation + * + * Copyright (C) 2011 RICOH COMPANY,LTD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_REGULATOR_RICOH583_H +#define __LINUX_REGULATOR_RICOH583_H + +#include <linux/regulator/machine.h> + + +#define ricoh583_rails(_name) "RICOH583_"#_name + +/* RICHOH Regulator IDs */ +enum regulator_id { + RICOH583_ID_DC0, + RICOH583_ID_DC1, + RICOH583_ID_DC2, + RICOH583_ID_DC3, + RICOH583_ID_LDO0, + RICOH583_ID_LDO1, + RICOH583_ID_LDO2, + RICOH583_ID_LDO3, + RICOH583_ID_LDO4, + RICOH583_ID_LDO5, + RICOH583_ID_LDO6, + RICOH583_ID_LDO7, + RICOH583_ID_LDO8, + RICOH583_ID_LDO9, +}; + +struct ricoh583_regulator_platform_data { + struct regulator_init_data regulator; + int init_uV; + unsigned init_enable:1; + unsigned init_apply:1; + int deepsleep_uV; + int deepsleep_slots; + unsigned long ext_pwr_req; + unsigned long flags; +}; + +#endif diff --git a/include/linux/regulator/tps6236x-regulator.h b/include/linux/regulator/tps6236x-regulator.h new file mode 100644 index 000000000000..7e8a37529665 --- /dev/null +++ b/include/linux/regulator/tps6236x-regulator.h @@ -0,0 +1,54 @@ +/* + * include/linux/regulator/tps6236x.h + * + * Interface for regulator driver for TI TPS6236x Processor core supply + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __REGULATOR_TPS6236X_H +#define __REGULATOR_TPS6236X_H + +#include <linux/regulator/machine.h> + +/* + * struct tps6236x_regulator_platform_data - tps6236x regulator platform data. + * + * @reg_init_data: The regulator init data. + * @internal_pd_enable: internal pull down enable or not. + * @vsel: Select the voltage id register. + * @init_uV: initial micro volts which need to be set. + * @init_enable: Enable or do not enable the rails during initialization. + * @init_apply: Init parameter applied or not. + * @is_force_pwm: Enable force pwm or not. If not then PFM mode configuration + * will be used. + * @enable_discharge: Enable discharge the output capacitor via a typ. 300Ohm + * path + */ + +struct tps6236x_regulator_platform_data { + struct regulator_init_data reg_init_data; + int internal_pd_enable; + int vsel; + int init_uV; + unsigned init_apply:1; + bool is_force_pwm; + bool enable_discharge; +}; + +#endif /* __REGULATOR_TPS6236X_H */ diff --git a/include/linux/regulator/tps6591x-regulator.h b/include/linux/regulator/tps6591x-regulator.h new file mode 100644 index 000000000000..7f7f647906d0 --- /dev/null +++ b/include/linux/regulator/tps6591x-regulator.h @@ -0,0 +1,77 @@ +/* + * include/linux/regulator/tps6591x-regulator.h + * + * Interface for regulator driver for TI TPS6591x PMIC family + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __REGULATOR_TPS6591X_H +#define __REGULATOR_TPS6591X_H + +#include <linux/regulator/machine.h> + +#define tps6591x_rails(_name) "tps6591x_"#_name + +enum { + TPS6591X_ID_VIO, + TPS6591X_ID_VDD_1, + TPS6591X_ID_VDD_2, + TPS6591X_ID_VDDCTRL, + TPS6591X_ID_LDO_1, + TPS6591X_ID_LDO_2, + TPS6591X_ID_LDO_3, + TPS6591X_ID_LDO_4, + TPS6591X_ID_LDO_5, + TPS6591X_ID_LDO_6, + TPS6591X_ID_LDO_7, + TPS6591X_ID_LDO_8, +}; + +enum tps6591x_ext_control { + EXT_CTRL_NONE = 0x0, + EXT_CTRL_EN1, + EXT_CTRL_EN2, + EXT_CTRL_SLEEP_OFF, +}; + +enum tps6591x_config_flags { + LDO_LOW_POWER_ON_SUSPEND = 0x1, +}; + +/* + * struct tps6591x_regulator_platform_data - tps6591x regulator platform data. + * + * @regulator: The regulator init data. + * @init_uV: initial micro volts which need to be set. + * @init_enable: Enable or do not enable the rails during initialization. + * @init_apply: Init parameter applied or not. + * @slew_rate_uV_per_us: Slew rate microvolt per microsec. + */ + +struct tps6591x_regulator_platform_data { + struct regulator_init_data regulator; + int init_uV; + unsigned init_enable:1; + unsigned init_apply:1; + enum tps6591x_ext_control ectrl; + int slew_rate_uV_per_us; + unsigned int flags; +}; + +#endif /* __REGULATOR_TPS6591X_H */ diff --git a/include/linux/regulator/tps80031-regulator.h b/include/linux/regulator/tps80031-regulator.h new file mode 100644 index 000000000000..d84a8c48b4f0 --- /dev/null +++ b/include/linux/regulator/tps80031-regulator.h @@ -0,0 +1,89 @@ +/* + * include/linux/regulator/tps80031-regulator.h + * + * Interface for regulator driver for TI TPS80031 + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __REGULATOR_TPS80031_H +#define __REGULATOR_TPS80031_H + +#include <linux/regulator/machine.h> + +#define tps80031_rails(_name) "tps80031_"#_name + +enum { + TPS80031_ID_VIO, + TPS80031_ID_SMPS1, + TPS80031_ID_SMPS2, + TPS80031_ID_SMPS3, + TPS80031_ID_SMPS4, + TPS80031_ID_VANA, + TPS80031_ID_LDO1, + TPS80031_ID_LDO2, + TPS80031_ID_LDO3, + TPS80031_ID_LDO4, + TPS80031_ID_LDO5, + TPS80031_ID_LDO6, + TPS80031_ID_LDO7, + TPS80031_ID_LDOLN, + TPS80031_ID_LDOUSB, + TPS80031_ID_VBUS, + TPS80031_ID_CHARGER, +}; + + +enum { + /* USBLDO input selection */ + USBLDO_INPUT_VSYS = 0x00000001, + USBLDO_INPUT_PMID = 0x00000002, + + /* LDO3 output mode */ + LDO3_OUTPUT_VIB = 0x00000004, + + /* VBUS configuration */ + VBUS_DISCHRG_EN_PDN = 0x00000004, + VBUS_SW_ONLY = 0x00000008, + VBUS_SW_N_ID = 0x00000010, +}; + +/* + * struct tps80031_regulator_platform_data - tps80031 regulator platform data. + * + * @regulator: The regulator init data. + * @init_uV: initial micro volts which need to be set. + * @init_enable: Enable or do not enable the rails during initialization. + * @init_apply: Init parameter applied or not. + * @ext_pwr_ctrl: External power request control. + * @flags: Configuration flag to configure the rails. It should be ORed of + * above enums. + * @delay_us: Delay in microsecond after setting the desired voltage. + */ + +struct tps80031_regulator_platform_data { + struct regulator_init_data regulator; + int init_uV; + unsigned init_enable:1; + unsigned init_apply:1; + unsigned int ext_pwr_ctrl; + unsigned int flags; + int delay_us; +}; + +#endif /* __REGULATOR_TPS80031_H */ diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index c75bda37c18e..543e361b15c1 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -2,10 +2,10 @@ * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. - * - * Redistribution of this file is permitted under the terms of the GNU + * + * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) - * + * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). @@ -86,7 +86,7 @@ #define UART_LCR 3 /* Out: Line Control Register */ /* - * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ @@ -110,8 +110,10 @@ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_HW_RTS 0x40 /* Enable hw control of RTS (Tegra UART) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_HW_CTS 0x20 /* Enable HW based CTS control (Tegra UART)*/ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ diff --git a/include/linux/spi-tegra.h b/include/linux/spi-tegra.h new file mode 100644 index 000000000000..380965005516 --- /dev/null +++ b/include/linux/spi-tegra.h @@ -0,0 +1,50 @@ +/* + * include/linux/spi-tegra.c + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_SPI_TEGRA_H +#define _LINUX_SPI_TEGRA_H + +#include <linux/clk.h> + +struct spi_clk_parent { + const char *name; + struct clk *parent_clk; + unsigned long fixed_clk_rate; +}; + +struct tegra_spi_platform_data { + bool is_dma_based; + int max_dma_buffer; + bool is_clkon_always; + unsigned int max_rate; + struct spi_clk_parent *parent_clk_list; + int parent_clk_count; +}; + +/* Controller data from device to pass some info like + * hw based chip select can be used or not and if yes + * then CS hold and setup time. */ +struct tegra_spi_device_controller_data { + bool is_hw_based_cs; + int cs_setup_clk_count; + int cs_hold_clk_count; +}; + +#endif /* _LINUX_SPI_TEGRA_H */ diff --git a/include/linux/tegra_audio.h b/include/linux/tegra_audio.h index db4661aacb4f..516b5a89c4e6 100644 --- a/include/linux/tegra_audio.h +++ b/include/linux/tegra_audio.h @@ -31,6 +31,16 @@ struct tegra_audio_in_config { int stereo; }; +struct dam_srate { + unsigned int in_sample_rate; + unsigned int out_sample_rate; + unsigned int audio_bits; + unsigned int client_bits; + unsigned int audio_channels; + unsigned int client_channels; + unsigned int apbif_chan; +}; + #define TEGRA_AUDIO_IN_SET_CONFIG _IOW(TEGRA_AUDIO_MAGIC, 2, \ const struct tegra_audio_in_config *) #define TEGRA_AUDIO_IN_GET_CONFIG _IOR(TEGRA_AUDIO_MAGIC, 3, \ @@ -54,4 +64,15 @@ struct tegra_audio_in_config { #define TEGRA_AUDIO_GET_BIT_FORMAT _IOR(TEGRA_AUDIO_MAGIC, 12, \ unsigned int *) +#define DAM_SRC_START _IOW(TEGRA_AUDIO_MAGIC, 13, struct dam_srate *) +#define DAM_SRC_STOP _IO(TEGRA_AUDIO_MAGIC, 14) +#define DAM_MIXING_START _IOW(TEGRA_AUDIO_MAGIC, 15, struct dam_srate *) +#define DAM_MIXING_STOP _IO(TEGRA_AUDIO_MAGIC, 16) +#define DAM_SET_MIXING_FLAG _IO(TEGRA_AUDIO_MAGIC, 17) + +#define I2S_START _IOW(TEGRA_AUDIO_MAGIC, 15, struct i2s_pcm_format *) +#define I2S_STOP _IOW(TEGRA_AUDIO_MAGIC, 16, struct i2s_pcm_format *) +#define I2S_LOOPBACK _IOW(TEGRA_AUDIO_MAGIC, 17, unsigned int *) +#define I2S_MODE_I2S _IOW(TEGRA_AUDIO_MAGIC, 18, unsigned int *) + #endif/*_CPCAP_AUDIO_H*/ diff --git a/include/linux/tegra_avp.h b/include/linux/tegra_avp.h index 2650b553c615..9dc92f821368 100644 --- a/include/linux/tegra_avp.h +++ b/include/linux/tegra_avp.h @@ -30,6 +30,9 @@ struct tegra_avp_lib { unsigned long handle; }; +struct tegra_avp_platform_data { + unsigned long emc_clk_rate; +}; #define TEGRA_AVP_IOCTL_MAGIC 'r' #define TEGRA_AVP_IOCTL_LOAD_LIB _IOWR(TEGRA_AVP_IOCTL_MAGIC, 0x40, struct tegra_avp_lib) diff --git a/include/linux/tegra_caif.h b/include/linux/tegra_caif.h new file mode 100644 index 000000000000..fed67499defc --- /dev/null +++ b/include/linux/tegra_caif.h @@ -0,0 +1,34 @@ +/* include/linux/tegra_caif.h + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _TEGRA_CAIF_H_ +#define _TEGRA_CAIF_H_ + +/* The GPIO details needed by the rainbow caif */ +struct tegra_caif_platform_data { + int reset; + int power; + int awr; + int cwr; + int spi_int; + int spi_ss; +}; + +#endif /* _TEGRA_CAIF_H_ */ + diff --git a/include/linux/tegra_mediaserver.h b/include/linux/tegra_mediaserver.h new file mode 100644 index 000000000000..f28473baf63e --- /dev/null +++ b/include/linux/tegra_mediaserver.h @@ -0,0 +1,112 @@ +/* include/linux/tegra_mediaserver.h + * + * Media Server driver for NVIDIA Tegra SoCs + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + + +#ifndef _TEGRA_MEDIASERVER_H +#define _TEGRA_MEDIASERVER_H + +#include <linux/ioctl.h> + +#define TEGRA_MEDIASERVER_MAGIC 'm' +#define TEGRA_MEDIASERVER_IOCTL_ALLOC \ + _IOWR(TEGRA_MEDIASERVER_MAGIC, 0x40, \ + union tegra_mediaserver_alloc_info) + +enum tegra_mediaserver_resource_type { + TEGRA_MEDIASERVER_RESOURCE_BLOCK = 0, + TEGRA_MEDIASERVER_RESOURCE_IRAM, +}; + +enum tegra_mediaserver_block_type { + TEGRA_MEDIASERVER_BLOCK_AUDDEC = 0, + TEGRA_MEDIASERVER_BLOCK_VIDDEC, +}; + +enum tegra_mediaserver_iram_type { + TEGRA_MEDIASERVER_IRAM_SCRATCH = 0, + TEGRA_MEDIASERVER_IRAM_SHARED, +}; + + +struct tegra_mediaserver_block_info { + int nvmm_block_handle; + int avp_block_handle; + int avp_block_library_handle; + int service_handle; + int service_library_handle; +}; + +struct tegra_mediaserver_iram_info { + unsigned long rm_handle; + int physical_address; +}; + +union tegra_mediaserver_alloc_info { + struct { + int tegra_mediaserver_resource_type; + + union { + struct tegra_mediaserver_block_info block; + + struct { + int tegra_mediaserver_iram_type; + int alignment; + size_t size; + } iram; + } u; + } in; + + struct { + union { + struct { + int count; + } block; + + struct tegra_mediaserver_iram_info iram; + } u; + } out; +}; + + +#define TEGRA_MEDIASERVER_IOCTL_FREE \ + _IOR(TEGRA_MEDIASERVER_MAGIC, 0x41, union tegra_mediaserver_free_info) + +union tegra_mediaserver_free_info { + struct { + int tegra_mediaserver_resource_type; + + union { + int nvmm_block_handle; + int iram_rm_handle; + } u; + } in; +}; + + +#define TEGRA_MEDIASERVER_IOCTL_UPDATE_BLOCK_INFO \ + _IOR(TEGRA_MEDIASERVER_MAGIC, 0x45, \ + union tegra_mediaserver_update_block_info) + +union tegra_mediaserver_update_block_info { + struct tegra_mediaserver_block_info in; +}; +#endif + diff --git a/include/linux/tegra_nvavp.h b/include/linux/tegra_nvavp.h new file mode 100644 index 000000000000..32dc4c62b4bd --- /dev/null +++ b/include/linux/tegra_nvavp.h @@ -0,0 +1,84 @@ +/* + * include/linux/tegra_nvavp.h + * + * Copyright (C) 2011 NVIDIA Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __LINUX_TEGRA_NVAVP_H +#define __LINUX_TEGRA_NVAVP_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#define NVAVP_MAX_RELOCATION_COUNT 64 + +/* avp submit flags */ +#define NVAVP_FLAG_NONE 0x00000000 +#define NVAVP_UCODE_EXT 0x00000001 /*use external ucode provided */ + +enum { + NVAVP_MODULE_ID_AVP = 2, + NVAVP_MODULE_ID_VCP = 3, + NVAVP_MODULE_ID_BSEA = 27, + NVAVP_MODULE_ID_VDE = 28, + NVAVP_MODULE_ID_MPE = 29, + NVAVP_MODULE_ID_EMC = 75, +}; + +struct nvavp_cmdbuf { + __u32 mem; + __u32 offset; + __u32 words; +}; + +struct nvavp_reloc { + __u32 cmdbuf_mem; + __u32 cmdbuf_offset; + __u32 target; + __u32 target_offset; +}; + +struct nvavp_syncpt { + __u32 id; + __u32 value; +}; + +struct nvavp_pushbuffer_submit_hdr { + struct nvavp_cmdbuf cmdbuf; + struct nvavp_reloc *relocs; + __u32 num_relocs; + struct nvavp_syncpt *syncpt; + __u32 flags; +}; + +struct nvavp_set_nvmap_fd_args { + __u32 fd; +}; + +struct nvavp_clock_args { + __u32 id; + __u32 rate; +}; + +#define NVAVP_IOCTL_MAGIC 'n' + +#define NVAVP_IOCTL_SET_NVMAP_FD _IOW(NVAVP_IOCTL_MAGIC, 0x60, \ + struct nvavp_set_nvmap_fd_args) +#define NVAVP_IOCTL_GET_SYNCPOINT_ID _IOR(NVAVP_IOCTL_MAGIC, 0x61, \ + __u32) +#define NVAVP_IOCTL_PUSH_BUFFER_SUBMIT _IOWR(NVAVP_IOCTL_MAGIC, 0x63, \ + struct nvavp_pushbuffer_submit_hdr) +#define NVAVP_IOCTL_SET_CLOCK _IOWR(NVAVP_IOCTL_MAGIC, 0x64, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_GET_CLOCK _IOR(NVAVP_IOCTL_MAGIC, 0x65, \ + struct nvavp_clock_args) + + +#define NVAVP_IOCTL_MIN_NR _IOC_NR(NVAVP_IOCTL_SET_NVMAP_FD) +#define NVAVP_IOCTL_MAX_NR _IOC_NR(NVAVP_IOCTL_GET_CLOCK) + +#endif /* __LINUX_TEGRA_NVAVP_H */ diff --git a/include/linux/tegra_overlay.h b/include/linux/tegra_overlay.h new file mode 100644 index 000000000000..2a6025afdad7 --- /dev/null +++ b/include/linux/tegra_overlay.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2010 NVIDIA Corporation + * Author: Dan Willemsen <dwillemsen@nvidia.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_OVERLAY_H +#define __LINUX_TEGRA_OVERLAY_H + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <video/tegrafb.h> + +#define TEGRA_FB_WIN_BLEND_NONE 0 +#define TEGRA_FB_WIN_BLEND_PREMULT 1 +#define TEGRA_FB_WIN_BLEND_COVERAGE 2 + +#define TEGRA_FB_WIN_FLAG_INVERT_H (1 << 0) +#define TEGRA_FB_WIN_FLAG_INVERT_V (1 << 1) +#define TEGRA_FB_WIN_FLAG_TILED (1 << 2) + +/* set index to -1 to ignore window data */ +struct tegra_overlay_windowattr { + __s32 index; + __u32 buff_id; + __u32 blend; + __u32 offset; + __u32 offset_u; + __u32 offset_v; + __u32 stride; + __u32 stride_uv; + __u32 pixformat; + __u32 x; + __u32 y; + __u32 w; + __u32 h; + __u32 out_x; + __u32 out_y; + __u32 out_w; + __u32 out_h; + __u32 z; + __u32 pre_syncpt_id; + __u32 pre_syncpt_val; + __u32 hfilter; + __u32 vfilter; + __u32 do_not_use__tiled; /* compatibility */ + __u32 flags; +}; + +#define TEGRA_OVERLAY_FLIP_FLAG_BLEND_REORDER (1 << 0) +#define TEGRA_FB_FLIP_N_WINDOWS 3 + +struct tegra_overlay_flip_args { + struct tegra_overlay_windowattr win[TEGRA_FB_FLIP_N_WINDOWS]; + __u32 post_syncpt_id; + __u32 post_syncpt_val; + __u32 flags; +}; + +#define TEGRA_OVERLAY_IOCTL_MAGIC 'O' + +#define TEGRA_OVERLAY_IOCTL_OPEN_WINDOW _IOWR(TEGRA_OVERLAY_IOCTL_MAGIC, 0x40, __u32) +#define TEGRA_OVERLAY_IOCTL_CLOSE_WINDOW _IOW(TEGRA_OVERLAY_IOCTL_MAGIC, 0x41, __u32) +#define TEGRA_OVERLAY_IOCTL_FLIP _IOW(TEGRA_OVERLAY_IOCTL_MAGIC, 0x42, struct tegra_overlay_flip_args) +#define TEGRA_OVERLAY_IOCTL_SET_NVMAP_FD _IOW(TEGRA_OVERLAY_IOCTL_MAGIC, 0x43, __u32) + +#define TEGRA_OVERLAY_IOCTL_MIN_NR _IOC_NR(TEGRA_OVERLAY_IOCTL_OPEN_WINDOW) +#define TEGRA_OVERLAY_IOCTL_MAX_NR _IOC_NR(TEGRA_OVERLAY_IOCTL_SET_NVMAP_FD) + +#endif diff --git a/include/linux/tegra_pwm_bl.h b/include/linux/tegra_pwm_bl.h new file mode 100644 index 000000000000..71a81f2eda88 --- /dev/null +++ b/include/linux/tegra_pwm_bl.h @@ -0,0 +1,31 @@ +/* Tegra PWM backlight data * + * + * Copyright (C) 2011 NVIDIA Corporation + * Author: Renuka Apte <rapte@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef TEGRA_PWM_BL_H +#define TEGRA_PWM_BL_H + +#include <linux/backlight.h> + +struct platform_tegra_pwm_backlight_data { + int which_dc; + int which_pwm; + void (*switch_to_sfio)(int); + int gpio_conf_to_sfio; + unsigned int dft_brightness; + unsigned int max_brightness; + unsigned int period; + unsigned int clk_div; + unsigned int clk_select; + int (*notify)(struct device *dev, int brightness); + int (*check_fb)(struct device *dev, struct fb_info *info); +}; + +#endif /* TERGA_PWM_BL_H */ diff --git a/include/linux/tegra_uart.h b/include/linux/tegra_uart.h new file mode 100644 index 000000000000..3d35e217cbca --- /dev/null +++ b/include/linux/tegra_uart.h @@ -0,0 +1,43 @@ +/* include/linux/tegra_uart.h + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _TEGRA_UART_H_ +#define _TEGRA_UART_H_ + +#include <linux/clk.h> + +struct uart_clk_parent { + const char *name; + struct clk *parent_clk; + unsigned long fixed_clk_rate; +}; + +struct tegra_uart_platform_data { + void (*wake_peer)(struct uart_port *); + struct uart_clk_parent *parent_clk_list; + int parent_clk_count; +}; + +int tegra_uart_is_tx_empty(struct uart_port *); +void tegra_uart_request_clock_on(struct uart_port *); +void tegra_uart_set_mctrl(struct uart_port *, unsigned int); +void tegra_uart_request_clock_off(struct uart_port *uport); + +#endif /* _TEGRA_UART_H_ */ + diff --git a/include/linux/tps80031-charger.h b/include/linux/tps80031-charger.h new file mode 100644 index 000000000000..26c228edc306 --- /dev/null +++ b/include/linux/tps80031-charger.h @@ -0,0 +1,62 @@ +/* + * include/linux/tps80031-charger.h + * + * Battery charger driver interface for TI TPS80031 PMIC + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_TPS80031_CHARGER_H +#define __LINUX_TPS80031_CHARGER_H + +#include <linux/regulator/machine.h> + +enum charging_states { + charging_state_idle, + charging_state_charging_in_progress, + charging_state_charging_completed, + charging_state_charging_stopped, +}; + +/** + * Callback type definition which is called when any state changed in the + * charging. + */ +typedef void (*charging_callback_t)(enum charging_states state, void *args); + +struct tps80031_charger_platform_data { + int regulator_id; + int max_charge_volt_mV; + int max_charge_current_mA; + int charging_term_current_mA; + int refresh_time; + int irq_base; + int watch_time_sec; + struct regulator_consumer_supply *consumer_supplies; + int num_consumer_supplies; + int (*board_init)(void *board_data); + void *board_data; +}; + +/** + * Register the callback function for the client. This callback gets called + * when there is any change in the chanrging states. + */ +extern int register_charging_state_callback(charging_callback_t cb, void *args); + +#endif /*__LINUX_TPS80031_CHARGER_H */ diff --git a/include/linux/tracelevel.h b/include/linux/tracelevel.h new file mode 100644 index 000000000000..ac3351c6ed85 --- /dev/null +++ b/include/linux/tracelevel.h @@ -0,0 +1,42 @@ +/* + * include/linux/tracelevel.c + * + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef _TRACELEVEL_H +#define _TRACELEVEL_H + +/* tracelevel allows a subsystem author to add priorities to + * trace_events. For usage details, see tracelevel.txt. + */ + +#define TRACELEVEL_ERR 3 +#define TRACELEVEL_WARN 2 +#define TRACELEVEL_INFO 1 +#define TRACELEVEL_DEBUG 0 + +#define TRACELEVEL_MAX TRACELEVEL_ERR +#define TRACELEVEL_DEFAULT TRACELEVEL_ERR + +int __tracelevel_register(char *name, unsigned int level); +int tracelevel_set_level(int level); + +#define tracelevel_register(name, level) \ + __tracelevel_register(#name, level) + +#endif /* _TRACELEVEL_H */ diff --git a/include/media/ad5820.h b/include/media/ad5820.h new file mode 100644 index 000000000000..c3e710113402 --- /dev/null +++ b/include/media/ad5820.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010-2011 NVIDIA Corporation. + * + * Contributors: + * Sachin Nikam <snikam@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __AD5820_H__ +#define __AD5820_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define AD5820_IOCTL_GET_CONFIG _IOR('o', 1, struct ad5820_config) +#define AD5820_IOCTL_SET_POSITION _IOW('o', 2, u32) + +struct ad5820_config { + __u32 settle_time; + __u32 actuator_range; + __u32 pos_low; + __u32 pos_high; + float focal_length; + float fnumber; + float max_aperture; +}; + +#endif /* __AD5820_H__ */ + diff --git a/include/media/ar0832_main.h b/include/media/ar0832_main.h new file mode 100644 index 000000000000..f5e3713b46fb --- /dev/null +++ b/include/media/ar0832_main.h @@ -0,0 +1,106 @@ +/* +* ar0832_main.h +* +* Copyright (c) 2011, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __AR0832_MAIN_H__ +#define __AR0832_MAIN_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define AR0832_IOCTL_SET_MODE _IOW('o', 0x01, struct ar0832_mode) +#define AR0832_IOCTL_SET_FRAME_LENGTH _IOW('o', 0x02, __u32) +#define AR0832_IOCTL_SET_COARSE_TIME _IOW('o', 0x03, __u32) +#define AR0832_IOCTL_SET_GAIN _IOW('o', 0x04, __u16) +#define AR0832_IOCTL_GET_STATUS _IOR('o', 0x05, __u8) +#define AR0832_IOCTL_GET_OTP _IOR('o', 0x06, struct ar0832_otp_data) +#define AR0832_IOCTL_TEST_PATTERN _IOW('o', 0x07, enum ar0832_test_pattern) +#define AR0832_IOCTL_SET_POWER_ON _IOW('o', 0x08, struct ar0832_mode) +#define AR0832_IOCTL_SET_SENSOR_REGION _IOW('o', 0x09, struct ar0832_stereo_region) + +#define AR0832_FOCUSER_IOCTL_GET_CONFIG _IOR('o', 0x10, struct ar0832_focuser_config) +#define AR0832_FOCUSER_IOCTL_SET_POSITION _IOW('o', 0x11, __u32) + +#define AR0832_IOCTL_GET_SENSOR_ID _IOR('o', 0x12, __u16) + +#define AR0832_SENSOR_ID_8141 0x1006 +#define AR0832_SENSOR_ID_8140 0x3006 + +enum ar0832_test_pattern { + TEST_PATTERN_NONE, + TEST_PATTERN_COLORBARS, + TEST_PATTERN_CHECKERBOARD +}; + +struct ar0832_otp_data { + /* Only the first 5 bytes are actually used. */ + __u8 sensor_serial_num[6]; + __u8 part_num[8]; + __u8 lens_id[1]; + __u8 manufacture_id[2]; + __u8 factory_id[2]; + __u8 manufacture_date[9]; + __u8 manufacture_line[2]; + + __u32 module_serial_num; + __u8 focuser_liftoff[2]; + __u8 focuser_macro[2]; + __u8 reserved1[12]; + __u8 shutter_cal[16]; + __u8 reserved2[183]; + + /* Big-endian. CRC16 over 0x00-0x41 (inclusive) */ + __u16 crc; + __u8 reserved3[3]; + __u8 auto_load[2]; +} __attribute__ ((packed)); + +struct ar0832_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; + int stereo; +}; + +struct ar0832_point{ + int x; + int y; +}; + +struct ar0832_reg { + __u16 addr; + __u16 val; +}; + +struct ar0832_stereo_region { + int camera_index; + struct ar0832_point image_start; + struct ar0832_point image_end; +}; + +struct ar0832_focuser_config { + __u32 settle_time; + __u32 actuator_range; + __u32 pos_low; + __u32 pos_high; + __u32 focal_length; + __u32 fnumber; + __u32 max_aperture; +}; + +#ifdef __KERNEL__ +struct ar0832_platform_data { + int (*power_on)(int is_stereo); + int (*power_off)(int is_stereo); + char *id; +}; +#endif /* __KERNEL__ */ + +#endif diff --git a/include/media/nvc.h b/include/media/nvc.h new file mode 100644 index 000000000000..35bd6e2470d1 --- /dev/null +++ b/include/media/nvc.h @@ -0,0 +1,145 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_H__ +#define __NVC_H__ + +#include <linux/ioctl.h> + +struct nvc_param { + int param; + __u32 sizeofvalue; + void *p_value; +} __packed; + +#define NVC_PARAM_EXPOSURE 0 +#define NVC_PARAM_GAIN 1 +#define NVC_PARAM_FRAMERATE 2 +#define NVC_PARAM_MAX_FRAMERATE 3 +#define NVC_PARAM_INPUT_CLOCK 4 +#define NVC_PARAM_LOCUS 5 +#define NVC_PARAM_FLASH_CAPS 6 +#define NVC_PARAM_FLASH_LEVEL 7 +#define NVC_PARAM_FLASH_PIN_STATE 8 +#define NVC_PARAM_TORCH_CAPS 9 +#define NVC_PARAM_TORCH_LEVEL 10 +#define NVC_PARAM_FOCAL_LEN 11 +#define NVC_PARAM_MAX_APERTURE 12 +#define NVC_PARAM_FNUMBER 13 +#define NVC_PARAM_EXPOSURE_LIMITS 14 +#define NVC_PARAM_GAIN_LIMITS 15 +#define NVC_PARAM_FRAMERATE_LIMITS 16 +#define NVC_PARAM_FRAME_RATES 17 +#define NVC_PARAM_EXP_LATCH_TIME 19 +#define NVC_PARAM_REGION_USED 20 +#define NVC_PARAM_SELF_TEST 23 +#define NVC_PARAM_STS 24 +#define NVC_PARAM_TESTMODE 25 +#define NVC_PARAM_EXPECTED_VALUES 26 +#define NVC_PARAM_RESET 27 +#define NVC_PARAM_OPTIMIZE_RES 28 +#define NVC_PARAM_LINES_PER_SEC 30 +#define NVC_PARAM_CAPS 31 +#define NVC_PARAM_STEREO_CAP 33 +#define NVC_PARAM_FOCUS_STEREO 34 +#define NVC_PARAM_STEREO 35 +#define NVC_PARAM_INHERENT_GAIN 36 +#define NVC_PARAM_VIEW_ANGLE_H 37 +#define NVC_PARAM_VIEW_ANGLE_V 38 +#define NVC_PARAM_DEV_ID 46 +#define NVC_PARAM_TEST_PATTERN 0x10000002 +#define NVC_PARAM_SENSOR_TYPE 0x10000006 +#define NVC_PARAM_I2C 1001 + +/* sync off */ +#define NVC_SYNC_OFF 0 +/* use only this device (the one receiving the call) */ +#define NVC_SYNC_MASTER 1 +/* use only the synced device (the "other" device) */ +#define NVC_SYNC_SLAVE 2 +/* use both synced devices at the same time */ +#define NVC_SYNC_STEREO 3 + +#define NVC_RESET_HARD 0 +#define NVC_RESET_SOFT 1 + +#define NVC_IOCTL_PWR_WR _IOW('o', 102, int) +#define NVC_IOCTL_PWR_RD _IOW('o', 103, int) +#define NVC_IOCTL_PARAM_WR _IOW('o', 104, struct nvc_param) +#define NVC_IOCTL_PARAM_RD _IOWR('o', 105, struct nvc_param) + + +#ifdef __KERNEL__ + +#include <linux/regulator/consumer.h> + +/* The NVC_CFG_ defines are for the .cfg entry in the + * platform data structure. + */ +/* Device not registered if not found */ +#define NVC_CFG_NODEV (1 << 0) +/* Don't return errors */ +#define NVC_CFG_NOERR (1 << 1) +/* Always go to _PWR_STDBY instead of _PWR_OFF */ +#define NVC_CFG_OFF2STDBY (1 << 2) +/* Init device at sys boot */ +#define NVC_CFG_BOOT_INIT (1 << 3) +/* Sync mode uses an I2C MUX to send at same time */ +#define NVC_CFG_SYNC_I2C_MUX (1 << 4) + +/* Expected higher level power calls are: + * 1 = OFF + * 2 = STANDBY + * 3 = ON + * These will be multiplied by 2 before given to the driver's PM code that + * uses the _PWR_ defines. This allows us to insert defines to give more power + * granularity and still remain linear with regards to the power usage and + * full power state transition latency for easy implementation of PM + * algorithms. + * The PM actions: + * _PWR_ERR = Non-valid state. + * _PWR_OFF_DELAYED = _PWR_OFF is called after a period of time. + * _PWR_OFF = Device, regulators, clocks, etc is turned off. The longest + * transition time to _PWR_ON is from this state. + * _PWR_STDBY_OFF = Device is useless but powered. No communication possible. + * Device does not retain programming. Main purpose is for + * faster return to _PWR_ON without regulator delays. + * _PWR_STDBY = Device is in standby. Device retains programming. + * _PWR_COMM = Device is powered enough to communicate with the device. + * _PWR_ON = Device is at full power with active output. + * + * The kernel drivers treat these calls as guaranteed level of service. + */ + +#define NVC_PWR_ERR 0 +#define NVC_PWR_OFF_DELAYED 1 +#define NVC_PWR_OFF 2 +#define NVC_PWR_STDBY_OFF 3 +#define NVC_PWR_STDBY 4 +#define NVC_PWR_COMM 5 +#define NVC_PWR_ON 6 + +struct nvc_regulator { + bool vreg_flag; + struct regulator *vreg; + const char *vreg_name; +}; + +#endif /* __KERNEL__ */ + +#endif /* __NVC_H__ */ + diff --git a/include/media/nvc_focus.h b/include/media/nvc_focus.h new file mode 100644 index 000000000000..fd83258abab3 --- /dev/null +++ b/include/media/nvc_focus.h @@ -0,0 +1,48 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_FOCUS_H__ +#define __NVC_FOCUS_H__ + +enum nvc_focus_sts { + NVC_FOCUS_STS_UNKNOWN = 1, + NVC_FOCUS_STS_NO_DEVICE, + NVC_FOCUS_STS_INITIALIZING, + NVC_FOCUS_STS_INIT_ERR, + NVC_FOCUS_STS_WAIT_FOR_MOVE_END, + NVC_FOCUS_STS_WAIT_FOR_SETTLE, + NVC_FOCUS_STS_LENS_SETTLED, + NVC_FOCUS_STS_FORCE32 = 0x7FFFFFFF +}; + +struct nvc_focus_nvc { + __u32 focal_length; + __u32 fnumber; + __u32 max_aperature; +} __packed; + +struct nvc_focus_cap { + __u32 version; + __u32 actuator_range; + __u32 settle_time; + __u32 focus_macro; + __u32 focus_hyper; + __u32 focus_infinity; +} __packed; + +#endif /* __NVC_FOCUS_H__ */ + diff --git a/include/media/nvc_torch.h b/include/media/nvc_torch.h new file mode 100644 index 000000000000..7c88bc75af05 --- /dev/null +++ b/include/media/nvc_torch.h @@ -0,0 +1,43 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_TORCH_H__ +#define __NVC_TORCH_H__ + +struct nvc_torch_level_info { + __s32 guidenum; + __u32 sustaintime; + __s32 rechargefactor; +} __packed; + +struct nvc_torch_pin_state { + __u16 mask; + __u16 values; +} __packed; + +struct nvc_torch_flash_capabilities { + __u32 numberoflevels; + struct nvc_torch_level_info levels[]; +} __packed; + +struct nvc_torch_torch_capabilities { + __u32 numberoflevels; + __s32 guidenum[]; +} __packed; + +#endif /* __NVC_TORCH_H__ */ + diff --git a/include/media/ov14810.h b/include/media/ov14810.h new file mode 100644 index 000000000000..67a864959186 --- /dev/null +++ b/include/media/ov14810.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV14810_H__ +#define __OV14810_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV14810_IOCTL_SET_MODE _IOW('o', 1, struct ov14810_mode) +#define OV14810_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV14810_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV14810_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV14810_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV14810_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) +#define OV14810_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) + +struct ov14810_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; +#ifdef __KERNEL__ +struct ov14810_platform_data { + int (*power_on)(void); + int (*power_off)(void); + void (*synchronize_sensors)(void); +}; +#endif /* __KERNEL__ */ + +#endif /* __OV14810_H__ */ diff --git a/include/media/ov2710.h b/include/media/ov2710.h new file mode 100644 index 000000000000..e3d43056d700 --- /dev/null +++ b/include/media/ov2710.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2010 Motorola, Inc. + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV2710_H__ +#define __OV2710_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV2710_IOCTL_SET_MODE _IOW('o', 1, struct ov2710_mode) +#define OV2710_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV2710_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV2710_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV2710_IOCTL_GET_STATUS _IOR('o', 5, __u8) + +struct ov2710_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; +#ifdef __KERNEL__ +struct ov2710_platform_data { + int (*power_on)(void); + int (*power_off)(void); + +}; +#endif /* __KERNEL__ */ + +#endif /* __OV2710_H__ */ + diff --git a/include/media/ov5650.h b/include/media/ov5650.h new file mode 100644 index 000000000000..00efcec61a5f --- /dev/null +++ b/include/media/ov5650.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2010 Motorola, Inc. + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV5650_H__ +#define __OV5650_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV5650_IOCTL_SET_MODE _IOW('o', 1, struct ov5650_mode) +#define OV5650_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV5650_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV5650_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV5650_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV5650_IOCTL_SET_BINNING _IOW('o', 6, __u8) +#define OV5650_IOCTL_TEST_PATTERN _IOW('o', 7, enum ov5650_test_pattern) +#define OV5650_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) +#define OV5650_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) + +/* OV5650 registers */ +#define OV5650_SRM_GRUP_ACCESS (0x3212) +#define OV5650_ARRAY_CONTROL_01 (0x3621) +#define OV5650_ANALOG_CONTROL_D (0x370D) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_CONTROL_HS_HIGH (0x3800) +#define OV5650_TIMING_CONTROL_HS_LOW (0x3801) +#define OV5650_TIMING_CONTROL_VS_HIGH (0x3802) +#define OV5650_TIMING_CONTROL_VS_LOW (0x3803) +#define OV5650_TIMING_HW_HIGH (0x3804) +#define OV5650_TIMING_HW_LOW (0x3805) +#define OV5650_TIMING_VH_HIGH (0x3806) +#define OV5650_TIMING_VH_LOW (0x3807) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_HREFST_MAN_HIGH (0x3824) +#define OV5650_TIMING_HREFST_MAN_LOW (0x3825) +#define OV5650_H_BINNING_BIT (1 << 7) +#define OV5650_H_SUBSAMPLING_BIT (1 << 6) +#define OV5650_V_BINNING_BIT (1 << 6) +#define OV5650_V_SUBSAMPLING_BIT (1 << 0) +#define OV5650_GROUP_HOLD_BIT (1 << 7) +#define OV5650_GROUP_LAUNCH_BIT (1 << 5) +#define OV5650_GROUP_HOLD_END_BIT (1 << 4) +#define OV5650_GROUP_ID(id) (id) + +enum ov5650_test_pattern { + TEST_PATTERN_NONE, + TEST_PATTERN_COLORBARS, + TEST_PATTERN_CHECKERBOARD +}; + +struct ov5650_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +#ifdef __KERNEL__ +struct ov5650_platform_data { + int (*power_on)(void); + int (*power_off)(void); + void (*synchronize_sensors)(void); +}; +#endif /* __KERNEL__ */ + +#endif /* __OV5650_H__ */ + diff --git a/include/media/ov9726.h b/include/media/ov9726.h new file mode 100644 index 000000000000..b1e759ba583c --- /dev/null +++ b/include/media/ov9726.h @@ -0,0 +1,62 @@ +/* +* ov9726.h +* +* Copyright (c) 2011, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __OV9726_H__ +#define __OV9726_H__ + +#include <linux/ioctl.h> + +#define OV9726_I2C_ADDR 0x20 + +#define OV9726_IOCTL_SET_MODE _IOW('o', 1, struct ov9726_mode) +#define OV9726_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV9726_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV9726_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV9726_IOCTL_GET_STATUS _IOR('o', 5, __u8) + +struct ov9726_mode { + int mode_id; + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov9726_reg { + __u16 addr; + __u16 val; +}; + +#ifdef __KERNEL__ +#define OV9726_REG_FRAME_LENGTH_HI 0x340 +#define OV9726_REG_FRAME_LENGTH_LO 0x341 +#define OV9726_REG_COARSE_TIME_HI 0x202 +#define OV9726_REG_COARSE_TIME_LO 0x203 +#define OV9726_REG_GAIN_HI 0x204 +#define OV9726_REG_GAIN_LO 0x205 + +#define OV9726_MAX_RETRIES 3 + +#define OV9726_TABLE_WAIT_MS 0 +#define OV9726_TABLE_END 1 + +struct ov9726_platform_data { + int (*power_on)(void); + int (*power_off)(void); + unsigned gpio_rst; + bool rst_low_active; + unsigned gpio_pwdn; + bool pwdn_low_active; +}; +#endif /* __KERNEL__ */ + +#endif /* __OV9726_H__ */ + diff --git a/include/media/sh532u.h b/include/media/sh532u.h new file mode 100644 index 000000000000..19da2070b70f --- /dev/null +++ b/include/media/sh532u.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __SH532U_H__ +#define __SH532U_H__ + +#include <media/nvc_focus.h> + + +struct sh532u_platform_data { + int cfg; + int num; + int sync; + const char *dev_name; + struct nvc_focus_nvc (*nvc); + struct nvc_focus_cap (*cap); + struct sh532u_pdata_info (*info); + __u8 i2c_addr_rom; + unsigned gpio_reset; +/* Due to a Linux limitation, a GPIO is defined to "enable" the device. This + * workaround is for when the device's power GPIO's are behind an I2C expander. + * The Linux limitation doesn't allow the I2C GPIO expander to be ready for + * use when this device is probed. + */ + unsigned gpio_en; +}; + +struct sh532u_pdata_info { + __s16 pos_low; + __s16 pos_high; + __s16 limit_low; + __s16 limit_high; + int move_timeoutms; + __u32 focus_hyper_ratio; + __u32 focus_hyper_div; +}; + + +/* Register Definition : Sany Driver IC */ +/* EEPROM addresses */ +#define addrHallOffset 0x10 +#define addrHallBias 0x11 +#define addrInf1 0x12 +#define addrMac1 0x13 +#define addrLoopGainH 0x14 +#define addrLoopGainL 0x15 +#define addrInf2 0x16 +#define addrMac2 0x17 + +#define addrInf1_H 0x20 /* bottom mechanical limit of HVCA */ +#define addrInf1_L 0x21 +#define addrMac1_H 0x22 /* top mechanical limit of HVCA */ +#define addrMac1_L 0x23 +#define addrInf2_H 0x24 /* lens position when object is ?120cm */ +#define addrInf2_L 0x25 +#define addrMac2_H 0x26 /* lens position when object is ?10cm */ +#define addrMac2_L 0x27 +#define addrDacDeltaUp_H 0x28 /* difference between face up and down */ +#define addrDacDeltaUp_L 0x29 +#define addrAFoffset_H 0x2A /* best focus position subtract value */ +#define addrAFoffset_L 0x2B + +/* Convergence Judgement */ +#define INI_MSSET_211 0x00 +#define CHTGOKN_TIME 0x80 +#define CHTGOKN_WAIT 1 +#define CHTGOKN_TIMEOUT 50 +#define CHTGSTOKN_TOMEOUT 15 + +/* StepMove */ +#define STMV_SIZE 0x0180 + +#define STMCHTG_ON 0x08 +#define STMSV_ON 0x04 +#define STMLFF_ON 0x02 +#define STMVEN_ON 0x01 +#define STMCHTG_OFF 0x00 +#define STMSV_OFF 0x00 +#define STMLFF_OFF 0x00 +#define STMVEN_OFF 0x00 + +#define STMCHTG_SET STMCHTG_ON +#define STMSV_SET STMSV_ON +#define STMLFF_SET STMLFF_OFF + +#define CHTGST_ON 0x01 +#define DEFAULT_DADAT 0x8040 + +/* Delay RAM 00h ~ 3Fh */ +#define ADHXI_211H 0x00 +#define ADHXI_211L 0x01 +#define PIDZO_211H 0x02 +#define PIDZO_211L 0x03 +#define RZ_211H 0x04 +#define RZ_211L 0x05 +#define DZ1_211H 0x06 +#define DZ1_211L 0x07 +#define DZ2_211H 0x08 +#define DZ2_211L 0x09 +#define UZ1_211H 0x0A +#define UZ1_211L 0x0B +#define UZ2_211H 0x0C +#define UZ2_211L 0x0D +#define IZ1_211H 0x0E +#define IZ1_211L 0x0F +#define IZ2_211H 0x10 +#define IZ2_211L 0x11 +#define MS1Z01_211H 0x12 +#define MS1Z01_211L 0x13 +#define MS1Z11_211H 0x14 +#define MS1Z11_211L 0x15 +#define MS1Z12_211H 0x16 +#define MS1Z12_211L 0x17 +#define MS1Z22_211H 0x18 +#define MS1Z22_211L 0x19 +#define MS2Z01_211H 0x1A +#define MS2Z01_211L 0x1B +#define MS2Z11_211H 0x1C +#define MS2Z11_211L 0x1D +#define MS2Z12_211H 0x1E +#define MS2Z12_211L 0x1F +#define MS2Z22_211H 0x20 +#define MS2Z22_211L 0x21 +#define MS2Z23_211H 0x22 +#define MS2Z23_211L 0x23 +#define OZ1_211H 0x24 +#define OZ1_211L 0x25 +#define OZ2_211H 0x26 +#define OZ2_211L 0x27 +#define DAHLXO_211H 0x28 +#define DAHLXO_211L 0x29 +#define OZ3_211H 0x2A +#define OZ3_211L 0x2B +#define OZ4_211H 0x2C +#define OZ4_211L 0x2D +#define OZ5_211H 0x2E +#define OZ5_211L 0x2F +#define oe_211H 0x30 +#define oe_211L 0x31 +#define MSR1CMAX_211H 0x32 +#define MSR1CMAX_211L 0x33 +#define MSR1CMIN_211H 0x34 +#define MSR1CMIN_211L 0x35 +#define MSR2CMAX_211H 0x36 +#define MSR2CMAX_211L 0x37 +#define MSR2CMIN_211H 0x38 +#define MSR2CMIN_211L 0x39 +#define OFFSET_211H 0x3A +#define OFFSET_211L 0x3B +#define ADOFFSET_211H 0x3C +#define ADOFFSET_211L 0x3D +#define EZ_211H 0x3E +#define EZ_211L 0x3F + +/* Coefficient RAM 40h ~ 7Fh */ +#define ag_211H 0x40 +#define ag_211L 0x41 +#define da_211H 0x42 +#define da_211L 0x43 +#define db_211H 0x44 +#define db_211L 0x45 +#define dc_211H 0x46 +#define dc_211L 0x47 +#define dg_211H 0x48 +#define dg_211L 0x49 +#define pg_211H 0x4A +#define pg_211L 0x4B +#define gain1_211H 0x4C +#define gain1_211L 0x4D +#define gain2_211H 0x4E +#define gain2_211L 0x4F +#define ua_211H 0x50 +#define ua_211L 0x51 +#define uc_211H 0x52 +#define uc_211L 0x53 +#define ia_211H 0x54 +#define ia_211L 0x55 +#define ib_211H 0x56 +#define ib_211L 0x57 +#define i_c_211H 0x58 +#define i_c_211L 0x59 +#define ms11a_211H 0x5A +#define ms11a_211L 0x5B +#define ms11c_211H 0x5C +#define ms11c_211L 0x5D +#define ms12a_211H 0x5E +#define ms12a_211L 0x5F +#define ms12c_211H 0x60 +#define ms12c_211L 0x61 +#define ms21a_211H 0x62 +#define ms21a_211L 0x63 +#define ms21b_211H 0x64 +#define ms21b_211L 0x65 +#define ms21c_211H 0x66 +#define ms21c_211L 0x67 +#define ms22a_211H 0x68 +#define ms22a_211L 0x69 +#define ms22c_211H 0x6A +#define ms22c_211L 0x6B +#define ms22d_211H 0x6C +#define ms22d_211L 0x6D +#define ms22e_211H 0x6E +#define ms22e_211L 0x6F +#define ms23p_211H 0x70 +#define ms23p_211L 0x71 +#define oa_211H 0x72 +#define oa_211L 0x73 +#define oc_211H 0x74 +#define oc_211L 0x75 +#define PX12_211H 0x76 +#define PX12_211L 0x77 +#define PX3_211H 0x78 +#define PX3_211L 0x79 +#define MS2X_211H 0x7A +#define MS2X_211L 0x7B +#define CHTGX_211H 0x7C +#define CHTGX_211L 0x7D +#define CHTGN_211H 0x7E +#define CHTGN_211L 0x7F + +/* Register 80h ~ 9F */ +#define CLKSEL_211 0x80 +#define ADSET_211 0x81 +#define PWMSEL_211 0x82 +#define SWTCH_211 0x83 +#define STBY_211 0x84 +#define CLR_211 0x85 +#define DSSEL_211 0x86 +#define ENBL_211 0x87 +#define ANA1_211 0x88 +#define STMVEN_211 0x8A +#define STPT_211 0x8B +#define SWFC_211 0x8C +#define SWEN_211 0x8D +#define MSNUM_211 0x8E +#define MSSET_211 0x8F +#define DLYMON_211 0x90 +#define MONA_211 0x91 +#define PWMLIMIT_211 0x92 +#define PINSEL_211 0x93 +#define PWMSEL2_211 0x94 +#define SFTRST_211 0x95 +#define TEST_211 0x96 +#define PWMZONE2_211 0x97 +#define PWMZONE1_211 0x98 +#define PWMZONE0_211 0x99 +#define ZONE3_211 0x9A +#define ZONE2_211 0x9B +#define ZONE1_211 0x9C +#define ZONE0_211 0x9D +#define GCTIM_211 0x9E +#define GCTIM_211NU 0x9F +#define STMINT_211 0xA0 +#define STMVENDH_211 0xA1 +#define STMVENDL_211 0xA2 +#define MSNUMR_211 0xA3 +#define ANA2_211 0xA4 + +/* Device ID of HVCA Drive IC */ +#define HVCA_DEVICE_ID 0xE4 + +/* Device ID of E2P ROM */ +#define EEP_DEVICE_ID 0xA0 +#define EEP_PAGE0 0x00 +#define EEP_PAGE1 0x02 +#define EEP_PAGE2 0x04 +#define EEP_PAGE3 0x06 +/* E2P ROM has 1023 bytes. So there are 4 pages memory */ +/* E2PROM Device ID = 1 0 1 0 0 P0 P1 0 */ +/* +P0 P1 +0 0 : Page 0 +0 1 : Page 1 +1 0 : Page 2 +1 1 : Page 3 +*/ +/* Page 0: address 0x000~0x0FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE0 */ +/* Page 1: address 0x100~0x1FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE1 */ +/* Page 2: address 0x200~0x2FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE2 */ +/* Page 3: address 0x300~0x3FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE3 */ +/* +*/ + +/* E2P data type define of HVCA Initial Value Section */ +#define DIRECT_MODE 0x00 +#define INDIRECT_EEPROM 0x10 +#define INDIRECT_HVCA 0x20 +#define MASK_AND 0x70 +#define MASK_OR 0x80 + +#define DATA_1BYTE 0x01 +#define DATA_2BYTE 0x02 + +#define START_ADDR 0x0030 +#define END_ADDR 0x01BF + +/*Macro define*/ +#if !defined(abs) +#define abs(a) (((a) > 0) ? (a) : -(a)) +#endif + +#endif +/* __SH532U_H__ */ + diff --git a/include/media/soc380.h b/include/media/soc380.h new file mode 100644 index 000000000000..254625f74f82 --- /dev/null +++ b/include/media/soc380.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION, All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of NVIDIA CORPORATION nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC380_H__ +#define __SOC380_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define SOC380_IOCTL_SET_MODE _IOW('o', 1, struct soc380_mode) +#define SOC380_IOCTL_GET_STATUS _IOR('o', 2, struct soc380_status) + +struct soc380_mode { + int xres; + int yres; +}; + +struct soc380_status { + int data; + int status; +}; + +#ifdef __KERNEL__ +struct soc380_platform_data { + int (*power_on)(void); + int (*power_off)(void); + +}; +#endif /* __KERNEL__ */ + +#endif /* __SOC380_H__ */ + diff --git a/include/media/ssl3250a.h b/include/media/ssl3250a.h new file mode 100644 index 000000000000..c4e802fa2efc --- /dev/null +++ b/include/media/ssl3250a.h @@ -0,0 +1,38 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __SSL3250A_H__ +#define __SSL3250A_H__ + +#include <media/nvc_torch.h> + +#define SSL3250A_MAX_TORCH_LEVEL 11 +#define SSL3250A_MAX_FLASH_LEVEL 20 + +struct ssl3250a_platform_data { + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state (*pinstate); /* see notes in driver */ + unsigned max_amp_torch; /* maximum torch value allowed */ + unsigned max_amp_flash; /* maximum flash value allowed */ + unsigned gpio_act; /* GPIO connected to the ACT signal */ +}; + +#endif /* __SSL3250A_H__ */ + diff --git a/include/media/tegra_camera.h b/include/media/tegra_camera.h index 3c8ddcab26e3..d7d08bd9a99b 100644 --- a/include/media/tegra_camera.h +++ b/include/media/tegra_camera.h @@ -13,6 +13,11 @@ * GNU General Public License for more details. * */ +#ifndef TEGRA_CAMERA_H +#define TEGRA_CAMERA_H + +/* this is to enable VI pattern generator (Null Sensor) */ +#define TEGRA_CAMERA_ENABLE_PD2VI_CLK 0x1 enum { TEGRA_CAMERA_MODULE_ISP = 0, @@ -29,10 +34,22 @@ struct tegra_camera_clk_info { uint id; uint clk_id; unsigned long rate; + uint flag; /* to inform if any special bits need to enabled/disabled */ +}; + +enum StereoCameraMode { + Main = 0x0, /* Sets the default camera to Main */ + StereoCameraMode_Left = 0x01, /* the left camera is on. */ + StereoCameraMode_Right = 0x02, /* the right camera is on. */ + StereoCameraMode_Stereo = 0x03, /* both cameras are on. */ + StereoCameraMode_Force32 = 0x7FFFFFFF }; + #define TEGRA_CAMERA_IOCTL_ENABLE _IOWR('i', 1, uint) #define TEGRA_CAMERA_IOCTL_DISABLE _IOWR('i', 2, uint) #define TEGRA_CAMERA_IOCTL_CLK_SET_RATE \ _IOWR('i', 3, struct tegra_camera_clk_info) #define TEGRA_CAMERA_IOCTL_RESET _IOWR('i', 4, uint) + +#endif diff --git a/include/media/tps61050.h b/include/media/tps61050.h new file mode 100644 index 000000000000..ac7a328a4b2d --- /dev/null +++ b/include/media/tps61050.h @@ -0,0 +1,97 @@ +/* + * tps61050.h - tps61050 flash/torch kernel driver + * + * Copyright (C) 2011 NVIDIA Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __TPS61050_H__ +#define __TPS61050_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define NUM_TORCH_LEVELS 8 +#define NUM_FLASH_LEVELS 9 + +/* Expected higher level power calls are: + * 1 = OFF + * 2 = STANDBY + * 3 = ON + * These will be multiplied by 2 before given to the driver PM code + * that uses the _PWR_ defines. This allows us to insert defines + * (most notably _PWR_COMM) allowing more versatile PM. + * The PM actions: + * _PWR_OFF = board support for regulators, clocks, etc so no + * power to device. + * _PWR_STDBY = board support to put device in reset. Device is + * useless but powered. No communication possible. + * _PWR_COMM = Device is powered but in SW standby. Communication + * is possible and device retains programming. + * _PWR_ON = Full power with active output. + */ + +#define TPS61050_PWR_ERR 0 +#define TPS61050_PWR_OFF 2 +#define TPS61050_PWR_STDBY 4 +#define TPS61050_PWR_COMM 5 +#define TPS61050_PWR_ON 6 + +#define TPS61050_CFG_NOSENSOR (1 << 0) + +#define TPS61050_IOCTL_CAP _IOWR('o', 1, struct tps61050_param) +#define TPS61050_IOCTL_PWR _IOW('o', 2, __u8) +#define TPS61050_IOCTL_PARAM_RD _IOWR('o', 3, struct tps61050_param) +#define TPS61050_IOCTL_PARAM_WR _IOW('o', 4, struct tps61050_param) + +#define TPS61050_FLASH_CAPS 6 +#define TPS61050_FLASH_LEVEL 7 +#define TPS61050_FLASH_PIN_STATE 8 +#define TPS61050_TORCH_CAPS 9 +#define TPS61050_TORCH_LEVEL 10 + +struct tps61050_param { + int param; + __s32 sizeofvalue; + void *p_value; +}; + +struct tps61050_level_info { + __s32 guidenum; + __u32 sustaintime; + __s32 rechargefactor; +}; + +struct tps61050_pin_state { + __u16 mask; + __u16 values; +}; + +struct tps61050_flash_capabilities { + __u32 numberoflevels; + struct tps61050_level_info levels[NUM_FLASH_LEVELS]; +}; + +struct tps61050_torch_capabilities { + __u32 numberoflevels; + __s32 guidenum[NUM_TORCH_LEVELS]; +}; + +#ifdef __KERNEL__ +struct tps61050_platform_data { + int cfg; + int num; + int max_amp_torch; + int max_amp_flash; + void (*pinstate); + int (*init)(void); + void (*exit)(void); + int (*pm)(int); + int (*gpio_envm)(int); + int (*gpio_sync)(int); +}; +#endif /* __KERNEL__ */ + +#endif /* __TPS61050_H__ */ diff --git a/include/sound/max98088.h b/include/sound/max98088.h index c3ba8239182d..9b4fceb360ac 100644 --- a/include/sound/max98088.h +++ b/include/sound/max98088.h @@ -31,6 +31,10 @@ struct max98088_pdata { struct max98088_eq_cfg *eq_cfg; unsigned int eq_cfgcnt; + /* has to be one of 25,50,100 or 200 ms + as per the data sheet */ + unsigned int debounce_time_ms; + /* Receiver output can be configured as power amplifier or LINE out */ /* Set receiver_mode to: * 0 = amplifier output, or diff --git a/include/trace/events/nvhost.h b/include/trace/events/nvhost.h new file mode 100644 index 000000000000..a0184440a09c --- /dev/null +++ b/include/trace/events/nvhost.h @@ -0,0 +1,413 @@ +/* + * include/trace/events/nvhost.h + * + * Nvhost event logging to ftrace. + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM nvhost + +#if !defined(_TRACE_NVHOST_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_NVHOST_H + +#include <linux/ktime.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(nvhost, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry(__field(const char *, name)), + TP_fast_assign(__entry->name = name;), + TP_printk("name=%s", __entry->name) +); + +DEFINE_EVENT(nvhost, nvhost_channel_open, + TP_PROTO(const char *name), + TP_ARGS(name) +); + +DEFINE_EVENT(nvhost, nvhost_channel_release, + TP_PROTO(const char *name), + TP_ARGS(name) +); + +DEFINE_EVENT(nvhost, nvhost_ioctl_channel_flush, + TP_PROTO(const char *name), + TP_ARGS(name) +); + +TRACE_EVENT(nvhost_channel_write_submit, + TP_PROTO(const char *name, ssize_t count, u32 cmdbufs, u32 relocs, + u32 syncpt_id, u32 syncpt_incrs), + + TP_ARGS(name, count, cmdbufs, relocs, syncpt_id, syncpt_incrs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(ssize_t, count) + __field(u32, cmdbufs) + __field(u32, relocs) + __field(u32, syncpt_id) + __field(u32, syncpt_incrs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->count = count; + __entry->cmdbufs = cmdbufs; + __entry->relocs = relocs; + __entry->syncpt_id = syncpt_id; + __entry->syncpt_incrs = syncpt_incrs; + ), + + TP_printk("name=%s, count=%d, cmdbufs=%u, relocs=%u, syncpt_id=%u, syncpt_incrs=%u", + __entry->name, __entry->count, __entry->cmdbufs, __entry->relocs, + __entry->syncpt_id, __entry->syncpt_incrs) +); + +TRACE_EVENT(nvhost_ioctl_channel_submit, + TP_PROTO(const char *name, u32 version, u32 cmdbufs, u32 relocs, + u32 waitchks, u32 syncpt_id, u32 syncpt_incrs), + + TP_ARGS(name, version, cmdbufs, relocs, waitchks, + syncpt_id, syncpt_incrs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, version) + __field(u32, cmdbufs) + __field(u32, relocs) + __field(u32, waitchks) + __field(u32, syncpt_id) + __field(u32, syncpt_incrs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->version = version; + __entry->cmdbufs = cmdbufs; + __entry->relocs = relocs; + __entry->waitchks = waitchks; + __entry->syncpt_id = syncpt_id; + __entry->syncpt_incrs = syncpt_incrs; + ), + + TP_printk("name=%s, version=%u, cmdbufs=%u, relocs=%u, waitchks=%u, syncpt_id=%u, syncpt_incrs=%u", + __entry->name, __entry->version, __entry->cmdbufs, __entry->relocs, + __entry->waitchks, __entry->syncpt_id, __entry->syncpt_incrs) +); + +TRACE_EVENT(nvhost_channel_write_cmdbuf, + TP_PROTO(const char *name, u32 mem_id, + u32 words, u32 offset), + + TP_ARGS(name, mem_id, words, offset), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, mem_id) + __field(u32, words) + __field(u32, offset) + ), + + TP_fast_assign( + __entry->name = name; + __entry->mem_id = mem_id; + __entry->words = words; + __entry->offset = offset; + ), + + TP_printk("name=%s, mem_id=%08x, words=%u, offset=%d", + __entry->name, __entry->mem_id, + __entry->words, __entry->offset) +); + +TRACE_EVENT(nvhost_channel_write_cmdbuf_data, + TP_PROTO(const char *name, u32 mem_id, + u32 words, u32 offset, void *cmdbuf), + + TP_ARGS(name, mem_id, words, offset, cmdbuf), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, mem_id) + __field(u32, words) + __field(u32, offset) + __field(bool, cmdbuf) + __dynamic_array(u32, cmdbuf, words) + ), + + TP_fast_assign( + if (cmdbuf) { + memcpy(__get_dynamic_array(cmdbuf), cmdbuf+offset, + words * sizeof(u32)); + } + __entry->cmdbuf = cmdbuf; + __entry->name = name; + __entry->mem_id = mem_id; + __entry->words = words; + __entry->offset = offset; + ), + + TP_printk("name=%s, mem_id=%08x, words=%u, offset=%d, contents=[%s]", + __entry->name, __entry->mem_id, + __entry->words, __entry->offset, + __print_hex(__get_dynamic_array(cmdbuf), + __entry->cmdbuf ? __entry->words * 4 : 0)) +); + +TRACE_EVENT(nvhost_channel_write_relocs, + TP_PROTO(const char *name, u32 relocs), + + TP_ARGS(name, relocs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, relocs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->relocs = relocs; + ), + + TP_printk("name=%s, relocs=%u", + __entry->name, __entry->relocs) +); + +TRACE_EVENT(nvhost_channel_write_waitchks, + TP_PROTO(const char *name, u32 waitchks, u32 waitmask), + + TP_ARGS(name, waitchks, waitmask), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, waitchks) + __field(u32, waitmask) + ), + + TP_fast_assign( + __entry->name = name; + __entry->waitchks = waitchks; + __entry->waitmask = waitmask; + ), + + TP_printk("name=%s, waitchks=%u, waitmask=%08x", + __entry->name, __entry->waitchks, __entry->waitmask) +); + +TRACE_EVENT(nvhost_channel_context_switch, + TP_PROTO(const char *name, void *old_ctx, void *new_ctx), + + TP_ARGS(name, old_ctx, new_ctx), + + TP_STRUCT__entry( + __field(const char *, name) + __field(void*, old_ctx) + __field(void*, new_ctx) + ), + + TP_fast_assign( + __entry->name = name; + __entry->old_ctx = old_ctx; + __entry->new_ctx = new_ctx; + ), + + TP_printk("name=%s, old=%p, new=%p", + __entry->name, __entry->old_ctx, __entry->new_ctx) +); + +TRACE_EVENT(nvhost_ctrlopen, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name + ), + TP_printk("name=%s", __entry->name) +); + +TRACE_EVENT(nvhost_ctrlrelease, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name + ), + TP_printk("name=%s", __entry->name) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_module_mutex, + TP_PROTO(u32 lock, u32 id), + + TP_ARGS(lock, id), + + TP_STRUCT__entry( + __field(u32, lock); + __field(u32, id); + ), + + TP_fast_assign( + __entry->lock = lock; + __entry->id = id; + ), + + TP_printk("lock=%u, id=%d", + __entry->lock, __entry->id) + ); + +TRACE_EVENT(nvhost_ioctl_ctrl_syncpt_incr, + TP_PROTO(u32 id), + + TP_ARGS(id), + + TP_STRUCT__entry( + __field(u32, id); + ), + + TP_fast_assign( + __entry->id = id; + ), + + TP_printk("id=%d", __entry->id) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_syncpt_read, + TP_PROTO(u32 id), + + TP_ARGS(id), + + TP_STRUCT__entry( + __field(u32, id); + ), + + TP_fast_assign( + __entry->id = id; + ), + + TP_printk("id=%d", __entry->id) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_syncpt_wait, + TP_PROTO(u32 id, u32 threshold, s32 timeout), + + TP_ARGS(id, threshold, timeout), + + TP_STRUCT__entry( + __field(u32, id) + __field(u32, threshold) + __field(s32, timeout) + ), + + TP_fast_assign( + __entry->id = id; + __entry->threshold = threshold; + __entry->timeout = timeout; + ), + + TP_printk("id=%u, threshold=%u, timeout=%d", + __entry->id, __entry->threshold, __entry->timeout) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_module_regrdwr, + TP_PROTO(u32 id, u32 num_offsets, bool write), + + TP_ARGS(id, num_offsets, write), + + TP_STRUCT__entry( + __field(u32, id) + __field(u32, num_offsets) + __field(bool, write) + ), + + TP_fast_assign( + __entry->id = id; + __entry->num_offsets = num_offsets; + __entry->write = write; + ), + + TP_printk("id=%u, num_offsets=%u, write=%d", + __entry->id, __entry->num_offsets, __entry->write) +); + +TRACE_EVENT(nvhost_channel_submitted, + TP_PROTO(const char *name, u32 syncpt_base, u32 syncpt_max), + + TP_ARGS(name, syncpt_base, syncpt_max), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, syncpt_base) + __field(u32, syncpt_max) + ), + + TP_fast_assign( + __entry->name = name; + __entry->syncpt_base = syncpt_base; + __entry->syncpt_max = syncpt_max; + ), + + TP_printk("name=%s, syncpt_base=%d, syncpt_max=%d", + __entry->name, __entry->syncpt_base, __entry->syncpt_max) +); + +TRACE_EVENT(nvhost_channel_submit_complete, + TP_PROTO(const char *name, int count), + + TP_ARGS(name, count), + + TP_STRUCT__entry( + __field(const char *, name) + __field(int, count) + ), + + TP_fast_assign( + __entry->name = name; + __entry->count = count; + ), + + TP_printk("name=%s, count=%d", __entry->name, __entry->count) +); + +TRACE_EVENT(nvhost_wait_cdma, + TP_PROTO(const char *name, u32 eventid), + + TP_ARGS(name, eventid), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, eventid) + ), + + TP_fast_assign( + __entry->name = name; + __entry->eventid = eventid; + ), + + TP_printk("name=%s, event=%d", __entry->name, __entry->eventid) +); + +#endif /* _TRACE_NVHOST_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/video/tegra_dc_ext.h b/include/video/tegra_dc_ext.h new file mode 100644 index 000000000000..7f504be1346a --- /dev/null +++ b/include/video/tegra_dc_ext.h @@ -0,0 +1,309 @@ +/* + * Copyright (C) 2011, NVIDIA Corporation + * + * Author: Robert Morell <rmorell@nvidia.com> + * Some code based on fbdev extensions written by: + * Erik Gilling <konkers@android.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TEGRA_DC_EXT_H +#define __TEGRA_DC_EXT_H + +#include <linux/types.h> +#include <linux/ioctl.h> +#if defined(__KERNEL__) +# include <linux/time.h> +#else +# include <time.h> +# include <unistd.h> +#endif + +#define TEGRA_DC_EXT_FMT_P1 0 +#define TEGRA_DC_EXT_FMT_P2 1 +#define TEGRA_DC_EXT_FMT_P4 2 +#define TEGRA_DC_EXT_FMT_P8 3 +#define TEGRA_DC_EXT_FMT_B4G4R4A4 4 +#define TEGRA_DC_EXT_FMT_B5G5R5A 5 +#define TEGRA_DC_EXT_FMT_B5G6R5 6 +#define TEGRA_DC_EXT_FMT_AB5G5R5 7 +#define TEGRA_DC_EXT_FMT_B8G8R8A8 12 +#define TEGRA_DC_EXT_FMT_R8G8B8A8 13 +#define TEGRA_DC_EXT_FMT_B6x2G6x2R6x2A8 14 +#define TEGRA_DC_EXT_FMT_R6x2G6x2B6x2A8 15 +#define TEGRA_DC_EXT_FMT_YCbCr422 16 +#define TEGRA_DC_EXT_FMT_YUV422 17 +#define TEGRA_DC_EXT_FMT_YCbCr420P 18 +#define TEGRA_DC_EXT_FMT_YUV420P 19 +#define TEGRA_DC_EXT_FMT_YCbCr422P 20 +#define TEGRA_DC_EXT_FMT_YUV422P 21 +#define TEGRA_DC_EXT_FMT_YCbCr422R 22 +#define TEGRA_DC_EXT_FMT_YUV422R 23 +#define TEGRA_DC_EXT_FMT_YCbCr422RA 24 +#define TEGRA_DC_EXT_FMT_YUV422RA 25 + +#define TEGRA_DC_EXT_BLEND_NONE 0 +#define TEGRA_DC_EXT_BLEND_PREMULT 1 +#define TEGRA_DC_EXT_BLEND_COVERAGE 2 + +#define TEGRA_DC_EXT_FLIP_FLAG_INVERT_H (1 << 0) +#define TEGRA_DC_EXT_FLIP_FLAG_INVERT_V (1 << 1) +#define TEGRA_DC_EXT_FLIP_FLAG_TILED (1 << 2) + +struct tegra_dc_ext_flip_windowattr { + __s32 index; + __u32 buff_id; + __u32 blend; + __u32 offset; + __u32 offset_u; + __u32 offset_v; + __u32 stride; + __u32 stride_uv; + __u32 pixformat; + /* + * x, y, w, h are fixed-point: 20 bits of integer (MSB) and 12 bits of + * fractional (LSB) + */ + __u32 x; + __u32 y; + __u32 w; + __u32 h; + __u32 out_x; + __u32 out_y; + __u32 out_w; + __u32 out_h; + __u32 z; + __u32 swap_interval; + struct timespec timestamp; + __u32 pre_syncpt_id; + __u32 pre_syncpt_val; + /* These two are optional; if zero, U and V are taken from buff_id */ + __u32 buff_id_u; + __u32 buff_id_v; + __u32 flags; + /* Leave some wiggle room for future expansion */ + __u32 pad[5]; +}; + +#define TEGRA_DC_EXT_FLIP_N_WINDOWS 3 + +struct tegra_dc_ext_flip { + struct tegra_dc_ext_flip_windowattr win[TEGRA_DC_EXT_FLIP_N_WINDOWS]; + __u32 post_syncpt_id; + __u32 post_syncpt_val; +}; + +/* + * Cursor image format: + * - Tegra hardware supports two colors: foreground and background, specified + * by the client in RGB8. + * - The image should be specified as two 1bpp bitmaps immediately following + * each other in memory. Each pixel in the final cursor will be constructed + * from the bitmaps with the following logic: + * bitmap1 bitmap0 + * (mask) (color) + * 1 0 transparent + * 1 1 inverted + * 0 0 background color + * 0 1 foreground color + * - Exactly one of the SIZE flags must be specified. + */ +#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_32x32 1 +#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_64x64 2 +struct tegra_dc_ext_cursor_image { + struct { + __u8 r; + __u8 g; + __u8 b; + } foreground, background; + __u32 buff_id; + __u32 flags; +}; + +/* Possible flags for struct nvdc_cursor's flags field */ +#define TEGRA_DC_EXT_CURSOR_FLAGS_VISIBLE 1 + +struct tegra_dc_ext_cursor { + __s16 x; + __s16 y; + __u32 flags; +}; + +/* + * Color conversion is performed as follows: + * + * r = sat(kyrgb * sat(y + yof) + kur * u + kvr * v) + * g = sat(kyrgb * sat(y + yof) + kug * u + kvg * v) + * b = sat(kyrgb * sat(y + yof) + kub * u + kvb * v) + * + * Coefficients should be specified as fixed-point values; the exact format + * varies for each coefficient. + * The format for each coefficient is listed below with the syntax: + * - A "s." prefix means that the coefficient has a sign bit (twos complement). + * - The first number is the number of bits in the integer component (not + * including the optional sign bit). + * - The second number is the number of bits in the fractional component. + * + * All three fields should be tightly packed, justified to the LSB of the + * 16-bit value. For example, the "s.2.8" value should be packed as: + * (MSB) 5 bits of 0, 1 bit of sign, 2 bits of integer, 8 bits of frac (LSB) + */ +struct tegra_dc_ext_csc { + __u32 win_index; + __u16 yof; /* s.7.0 */ + __u16 kyrgb; /* 2.8 */ + __u16 kur; /* s.2.8 */ + __u16 kvr; /* s.2.8 */ + __u16 kug; /* s.1.8 */ + __u16 kvg; /* s.1.8 */ + __u16 kub; /* s.2.8 */ + __u16 kvb; /* s.2.8 */ +}; + +/* + * RGB Lookup table + * + * In true-color and YUV modes this is used for post-CSC RGB->RGB lookup, i.e. + * gamma-correction. In palette-indexed RGB modes, this table designates the + * mode's color palette. + * + * To convert 8-bit per channel RGB values to 16-bit, duplicate the 8 bits + * in low and high byte, e.g. r=r|(r<<8) + * + * To just update flags, set len to 0. + * + * Current Tegra DC hardware supports 8-bit per channel to 8-bit per channel, + * and each hardware window (overlay) uses its own lookup table. + * + */ +struct tegra_dc_ext_lut { + __u32 win_index; /* window index to set lut for */ + __u32 flags; /* Flag bitmask, see TEGRA_DC_EXT_LUT_FLAGS_* */ + __u32 start; /* start index to update lut from */ + __u32 len; /* number of valid lut entries */ + __u16 *r; /* array of 16-bit red values, 0 to reset */ + __u16 *g; /* array of 16-bit green values, 0 to reset */ + __u16 *b; /* array of 16-bit blue values, 0 to reset */ +}; + +/* tegra_dc_ext_lut.flags - override global fb device lookup table. + * Default behaviour is double-lookup. + */ +#define TEGRA_DC_EXT_LUT_FLAGS_FBOVERRIDE 0x01 + +#define TEGRA_DC_EXT_FLAGS_ENABLED 1 +struct tegra_dc_ext_status { + __u32 flags; + /* Leave some wiggle room for future expansion */ + __u32 pad[3]; +}; + +#define TEGRA_DC_EXT_SET_NVMAP_FD \ + _IOW('D', 0x00, __s32) + +#define TEGRA_DC_EXT_GET_WINDOW \ + _IOW('D', 0x01, __u32) +#define TEGRA_DC_EXT_PUT_WINDOW \ + _IOW('D', 0x02, __u32) + +#define TEGRA_DC_EXT_FLIP \ + _IOWR('D', 0x03, struct tegra_dc_ext_flip) + +#define TEGRA_DC_EXT_GET_CURSOR \ + _IO('D', 0x04) +#define TEGRA_DC_EXT_PUT_CURSOR \ + _IO('D', 0x05) +#define TEGRA_DC_EXT_SET_CURSOR_IMAGE \ + _IOW('D', 0x06, struct tegra_dc_ext_cursor_image) +#define TEGRA_DC_EXT_SET_CURSOR \ + _IOW('D', 0x07, struct tegra_dc_ext_cursor) + +#define TEGRA_DC_EXT_SET_CSC \ + _IOW('D', 0x08, struct tegra_dc_ext_csc) + +#define TEGRA_DC_EXT_GET_STATUS \ + _IOR('D', 0x09, struct tegra_dc_ext_status) + +/* + * Returns the auto-incrementing vblank syncpoint for the head associated with + * this device node + */ +#define TEGRA_DC_EXT_GET_VBLANK_SYNCPT \ + _IOR('D', 0x09, __u32) + +#define TEGRA_DC_EXT_SET_LUT \ + _IOW('D', 0x0A, struct tegra_dc_ext_lut) + +enum tegra_dc_ext_control_output_type { + TEGRA_DC_EXT_DSI, + TEGRA_DC_EXT_LVDS, + TEGRA_DC_EXT_VGA, + TEGRA_DC_EXT_HDMI, + TEGRA_DC_EXT_DVI, +}; + +/* + * Get the properties for a given output. + * + * handle (in): Which output to query + * type (out): Describes the type of the output + * connected (out): Non-zero iff the output is currently connected + * associated_head (out): The head number that the output is currently + * bound to. -1 iff the output is not associated with any head. + * head_mask (out): Bitmask of which heads the output may be bound to (some + * outputs are permanently bound to a single head). + */ +struct tegra_dc_ext_control_output_properties { + __u32 handle; + enum tegra_dc_ext_control_output_type type; + __u32 connected; + __s32 associated_head; + __u32 head_mask; +}; + +/* + * This allows userspace to query the raw EDID data for the specified output + * handle. + * + * Here, the size parameter is both an input and an output: + * 1. Userspace passes in the size of the buffer allocated for data. + * 2. If size is too small, the call fails with the error EFBIG; otherwise, the + * raw EDID data is written to the buffer pointed to by data. In both + * cases, size will be filled in with the size of the data. + */ +struct tegra_dc_ext_control_output_edid { + __u32 handle; + __u32 size; + void *data; +}; + +struct tegra_dc_ext_event { + __u32 type; + ssize_t data_size; + char data[0]; +}; + +#define TEGRA_DC_EXT_EVENT_HOTPLUG 0x1 +struct tegra_dc_ext_control_event_hotplug { + __u32 handle; +}; + +#define TEGRA_DC_EXT_CONTROL_GET_NUM_OUTPUTS \ + _IOR('C', 0x00, __u32) +#define TEGRA_DC_EXT_CONTROL_GET_OUTPUT_PROPERTIES \ + _IOWR('C', 0x01, struct tegra_dc_ext_control_output_properties) +#define TEGRA_DC_EXT_CONTROL_GET_OUTPUT_EDID \ + _IOWR('C', 0x02, struct tegra_dc_ext_control_output_edid) +#define TEGRA_DC_EXT_CONTROL_SET_EVENT_MASK \ + _IOW('C', 0x03, __u32) + +#endif /* __TEGRA_DC_EXT_H */ diff --git a/include/video/tegrafb.h b/include/video/tegrafb.h index 6e765c5b175a..919661b1a8e0 100644 --- a/include/video/tegrafb.h +++ b/include/video/tegrafb.h @@ -20,79 +20,13 @@ #include <linux/fb.h> #include <linux/types.h> -#include <asm/ioctl.h> - -#define TEGRA_FB_WIN_FMT_P1 0 -#define TEGRA_FB_WIN_FMT_P2 1 -#define TEGRA_FB_WIN_FMT_P4 2 -#define TEGRA_FB_WIN_FMT_P8 3 -#define TEGRA_FB_WIN_FMT_B4G4R4A4 4 -#define TEGRA_FB_WIN_FMT_B5G5R5A 5 -#define TEGRA_FB_WIN_FMT_B5G6R5 6 -#define TEGRA_FB_WIN_FMT_AB5G5R5 7 -#define TEGRA_FB_WIN_FMT_B8G8R8A8 12 -#define TEGRA_FB_WIN_FMT_R8G8B8A8 13 -#define TEGRA_FB_WIN_FMT_B6x2G6x2R6x2A8 14 -#define TEGRA_FB_WIN_FMT_R6x2G6x2B6x2A8 15 -#define TEGRA_FB_WIN_FMT_YCbCr422 16 -#define TEGRA_FB_WIN_FMT_YUV422 17 -#define TEGRA_FB_WIN_FMT_YCbCr420P 18 -#define TEGRA_FB_WIN_FMT_YUV420P 19 -#define TEGRA_FB_WIN_FMT_YCbCr422P 20 -#define TEGRA_FB_WIN_FMT_YUV422P 21 -#define TEGRA_FB_WIN_FMT_YCbCr422R 22 -#define TEGRA_FB_WIN_FMT_YUV422R 23 -#define TEGRA_FB_WIN_FMT_YCbCr422RA 24 -#define TEGRA_FB_WIN_FMT_YUV422RA 25 - -#define TEGRA_FB_WIN_BLEND_NONE 0 -#define TEGRA_FB_WIN_BLEND_PREMULT 1 -#define TEGRA_FB_WIN_BLEND_COVERAGE 2 - -#define TEGRA_FB_WIN_FLAG_INVERT_H (1 << 0) -#define TEGRA_FB_WIN_FLAG_INVERT_V (1 << 1) -#define TEGRA_FB_WIN_FLAG_TILED (1 << 2) - -/* set index to -1 to ignore window data */ -struct tegra_fb_windowattr { - __s32 index; - __u32 buff_id; - __u32 flags; - __u32 blend; - __u32 offset; - __u32 offset_u; - __u32 offset_v; - __u32 stride; - __u32 stride_uv; - __u32 pixformat; - __u32 x; - __u32 y; - __u32 w; - __u32 h; - __u32 out_x; - __u32 out_y; - __u32 out_w; - __u32 out_h; - __u32 z; - __u32 pre_syncpt_id; - __u32 pre_syncpt_val; -}; - -#define TEGRA_FB_FLIP_N_WINDOWS 3 - -struct tegra_fb_flip_args { - struct tegra_fb_windowattr win[TEGRA_FB_FLIP_N_WINDOWS]; - __u32 post_syncpt_id; - __u32 post_syncpt_val; -}; +#include <linux/ioctl.h> struct tegra_fb_modedb { struct fb_var_screeninfo *modedb; __u32 modedb_len; }; -#define FBIO_TEGRA_SET_NVMAP_FD _IOW('F', 0x40, __u32) -#define FBIO_TEGRA_FLIP _IOW('F', 0x41, struct tegra_fb_flip_args) #define FBIO_TEGRA_GET_MODEDB _IOWR('F', 0x42, struct tegra_fb_modedb) #endif |