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-rw-r--r--include/asm-sh/keyboard.h13
-rw-r--r--include/asm-sh/mpc1211/dma.h303
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h60
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h38
8 files changed, 0 insertions, 660 deletions
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
deleted file mode 100644
index 31dcc4fa5f28..000000000000
--- a/include/asm-sh/keyboard.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_SH_KEYBOARD_H
-#define __ASM_SH_KEYBOARD_H
-/*
- * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
- */
-
-#include <linux/kd.h>
-#include <asm/machvec.h>
-
-#ifdef CONFIG_SH_MPC1211
-#include <asm/mpc1211/keyboard-mpc1211.h>
-#endif
-#endif
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
deleted file mode 100644
index e506d1aaa0d0..000000000000
--- a/include/asm-sh/mpc1211/dma.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- */
-
-#ifndef _ASM_MPC1211_DMA_H
-#define _ASM_MPC1211_DMA_H
-
-#include <linux/spinlock.h> /* And spinlocks */
-#include <asm/io.h> /* need byte IO */
-#include <linux/delay.h>
-
-
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb outb_p
-#else
-#define dma_outb outb
-#endif
-
-#define dma_inb inb
-
-/*
- * NOTES about DMA transfers:
- *
- * controller 1: channels 0-3, byte operations, ports 00-1F
- * controller 2: channels 4-7, word operations, ports C0-DF
- *
- * - ALL registers are 8 bits only, regardless of transfer size
- * - channel 4 is not used - cascades 1 into 2.
- * - channels 0-3 are byte - addresses/counts are for physical bytes
- * - channels 5-7 are word - addresses/counts are for physical words
- * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- * - transfer count loaded to registers is 1 less than actual count
- * - controller 2 offsets are all even (2x offsets for controller 1)
- * - page registers for 5-7 don't use data bit 0, represent 128K pages
- * - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- * Address mapping for channels 0-3:
- *
- * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
- * | ... | | ... | | ... |
- * | ... | | ... | | ... |
- * | ... | | ... | | ... |
- * P7 ... P0 A7 ... A0 A7 ... A0
- * | Page | Addr MSB | Addr LSB | (DMA registers)
- *
- * Address mapping for channels 5-7:
- *
- * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
- * | ... | \ \ ... \ \ \ ... \ \
- * | ... | \ \ ... \ \ \ ... \ (not used)
- * | ... | \ \ ... \ \ \ ... \
- * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
- * | Page | Addr MSB | Addr LSB | (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
- *
- */
-
-#define MAX_DMA_CHANNELS 8
-
-/* The maximum address that we can perform a DMA transfer to on this platform */
-#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG 0x08 /* command register (w) */
-#define DMA1_STAT_REG 0x08 /* status register (r) */
-#define DMA1_REQ_REG 0x09 /* request register (w) */
-#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
-#define DMA1_MODE_REG 0x0B /* mode register (w) */
-#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
-#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
-#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
-
-#define DMA2_CMD_REG 0xD0 /* command register (w) */
-#define DMA2_STAT_REG 0xD0 /* status register (r) */
-#define DMA2_REQ_REG 0xD2 /* request register (w) */
-#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
-#define DMA2_MODE_REG 0xD6 /* mode register (w) */
-#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
-#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
-#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
-
-#define DMA_ADDR_0 0x00 /* DMA address registers */
-#define DMA_ADDR_1 0x02
-#define DMA_ADDR_2 0x04
-#define DMA_ADDR_3 0x06
-#define DMA_ADDR_4 0xC0
-#define DMA_ADDR_5 0xC4
-#define DMA_ADDR_6 0xC8
-#define DMA_ADDR_7 0xCC
-
-#define DMA_CNT_0 0x01 /* DMA count registers */
-#define DMA_CNT_1 0x03
-#define DMA_CNT_2 0x05
-#define DMA_CNT_3 0x07
-#define DMA_CNT_4 0xC2
-#define DMA_CNT_5 0xC6
-#define DMA_CNT_6 0xCA
-#define DMA_CNT_7 0xCE
-
-#define DMA_PAGE_0 0x87 /* DMA page registers */
-#define DMA_PAGE_1 0x83
-#define DMA_PAGE_2 0x81
-#define DMA_PAGE_3 0x82
-#define DMA_PAGE_5 0x8B
-#define DMA_PAGE_6 0x89
-#define DMA_PAGE_7 0x8A
-
-#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT 0x10
-
-
-extern spinlock_t dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
- unsigned long flags;
- spin_lock_irqsave(&dma_spin_lock, flags);
- return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
- spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
- if (dmanr<=3)
- dma_outb(dmanr, DMA1_MASK_REG);
- else
- dma_outb(dmanr & 3, DMA2_MASK_REG);
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
- if (dmanr<=3)
- dma_outb(dmanr | 4, DMA1_MASK_REG);
- else
- dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
- if (dmanr<=3)
- dma_outb(0, DMA1_CLEAR_FF_REG);
- else
- dma_outb(0, DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
- if (dmanr<=3)
- dma_outb(mode | dmanr, DMA1_MODE_REG);
- else
- dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
-{
- switch(dmanr) {
- case 0:
- dma_outb( pagenr & 0xff, DMA_PAGE_0);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
- break;
- case 1:
- dma_outb( pagenr & 0xff, DMA_PAGE_1);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
- break;
- case 2:
- dma_outb( pagenr & 0xff, DMA_PAGE_2);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
- break;
- case 3:
- dma_outb( pagenr & 0xff, DMA_PAGE_3);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
- break;
- case 5:
- dma_outb( pagenr & 0xfe, DMA_PAGE_5);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
- break;
- case 6:
- dma_outb( pagenr & 0xfe, DMA_PAGE_6);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
- break;
- case 7:
- dma_outb( pagenr & 0xfe, DMA_PAGE_7);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
- break;
- }
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
- set_dma_page(dmanr, a>>16);
- if (dmanr <= 3) {
- dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
- dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
- } else {
- dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
- dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
- }
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
- count--;
- if (dmanr <= 3) {
- dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
- dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
- } else {
- dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
- dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
- }
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
- unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
- : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
- /* using short to get 16-bit wrap around */
- unsigned short count;
-
- count = 1 + dma_inb(io_port);
- count += dma_inb(io_port) << 8;
- return (dmanr<=3)? count : (count<<1);
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr); /* release it again */
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
deleted file mode 100644
index 6298370bec2d..000000000000
--- a/include/asm-sh/mpc1211/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-sh/mpc1211/io.h
- *
- * Copyright 2001 Saito.K & Jeanne
- *
- * IO functions for an Interface MPC-1211
- */
-
-#ifndef _ASM_SH_IO_MPC1211_H
-#define _ASM_SH_IO_MPC1211_H
-
-#include <linux/time.h>
-
-extern int mpc1211_irq_demux(int irq);
-
-extern void init_mpc1211_IRQ(void);
-extern void heartbeat_mpc1211(void);
-
-extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
-extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
-
-#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
deleted file mode 100644
index 9020feee7b4c..000000000000
--- a/include/asm-sh/mpc1211/keyboard.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * MPC1211 specific keybord definitions
- * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
- * created 3 Nov 1996 by Geert Uytterhoeven.
- */
-
-#ifdef __KERNEL__
-
-#include <linux/kernel.h>
-#include <linux/ioport.h>
-#include <linux/kd.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-#define KEYBOARD_IRQ 1
-#define DISABLE_KBD_DURING_INTERRUPTS 0
-
-extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
-extern int pckbd_getkeycode(unsigned int scancode);
-extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
- char raw_mode);
-extern char pckbd_unexpected_up(unsigned char keycode);
-extern void pckbd_leds(unsigned char leds);
-extern void pckbd_init_hw(void);
-extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
-extern pm_callback pm_kbd_request_override;
-
-#define kbd_setkeycode pckbd_setkeycode
-#define kbd_getkeycode pckbd_getkeycode
-#define kbd_translate pckbd_translate
-#define kbd_unexpected_up pckbd_unexpected_up
-#define kbd_leds pckbd_leds
-#define kbd_init_hw pckbd_init_hw
-
-/* resource allocation */
-#define kbd_request_region()
-#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
- "keyboard", NULL)
-
-/* How to access the keyboard macros on this platform. */
-#define kbd_read_input() inb(KBD_DATA_REG)
-#define kbd_read_status() inb(KBD_STATUS_REG)
-#define kbd_write_output(val) outb(val, KBD_DATA_REG)
-#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
-
-/* Some stoneage hardware needs delays after some operations. */
-#define kbd_pause() do { } while(0)
-
-/*
- * Machine specific bits for the PS/2 driver
- */
-
-#define AUX_IRQ 12
-
-#define aux_request_irq(hand, dev_id) \
- request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
-
-#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
deleted file mode 100644
index c95d13236c3b..000000000000
--- a/include/asm-sh/mpc1211/m1543c.h
+++ /dev/null
@@ -1,200 +0,0 @@
-#ifndef __ASM_SH_M1543C_H
-#define __ASM_SH_M1543C_H
-
-/*
- * linux/include/asm-sh/m1543c.h
- * Copyright (C) 2001 Nobuhiro Sakawa
- * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
- *
- * from
- *
- * linux/include/asm-sh/smc37c93x.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * SMSC 37C93x Super IO Chip support
- */
-
-/* Default base I/O address */
-#define FDC_PRIMARY_BASE 0x3f0
-#define IDE1_PRIMARY_BASE 0x1f0
-#define IDE1_SECONDARY_BASE 0x170
-#define PARPORT_PRIMARY_BASE 0x378
-#define COM1_PRIMARY_BASE 0x2f8
-#define COM2_PRIMARY_BASE 0x3f8
-#define COM3_PRIMARY_BASE 0x3e8
-#define RTC_PRIMARY_BASE 0x070
-#define KBC_PRIMARY_BASE 0x060
-#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
-#define I8259_M_CR 0x20
-#define I8259_M_MR 0x21
-#define I8259_S_CR 0xa0
-#define I8259_S_MR 0xa1
-
-/* Logical device number */
-#define LDN_FDC 0
-#define LDN_IDE1 1
-#define LDN_IDE2 2
-#define LDN_PARPORT 3
-#define LDN_COM1 4
-#define LDN_COM2 5
-#define LDN_COM3 11
-#define LDN_RTC 6
-#define LDN_KBC 7
-
-/* Configuration port and key */
-#define CONFIG_PORT 0x3f0
-#define INDEX_PORT CONFIG_PORT
-#define DATA_PORT 0x3f1
-#define CONFIG_ENTER1 0x51
-#define CONFIG_ENTER2 0x23
-#define CONFIG_EXIT 0xbb
-
-/* Configuration index */
-#define CURRENT_LDN_INDEX 0x07
-#define POWER_CONTROL_INDEX 0x22
-#define ACTIVATE_INDEX 0x30
-#define IO_BASE_HI_INDEX 0x60
-#define IO_BASE_LO_INDEX 0x61
-#define IRQ_SELECT_INDEX 0x70
-#define PS2_IRQ_INDEX 0x72
-#define DMA_SELECT_INDEX 0x74
-
-/* UART stuff. Only for debugging. */
-/* UART Register */
-
-#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
-#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
-#define UART_IER 0x2 /* Interrupt Enable Register */
-#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
-#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
-#define UART_LCR 0x6 /* Line Control Register */
-#define UART_MCR 0x8 /* MODEM Control Register */
-#define UART_LSR 0xa /* Line Status Register */
-#define UART_MSR 0xc /* MODEM Status Register */
-#define UART_SCR 0xe /* Scratch Register */
-#define UART_DLL 0x0 /* Divisor Latch (LS) */
-#define UART_DLM 0x2 /* Divisor Latch (MS) */
-
-#ifndef __ASSEMBLY__
-typedef struct uart_reg {
- volatile __u16 rbr;
- volatile __u16 ier;
- volatile __u16 iir;
- volatile __u16 lcr;
- volatile __u16 mcr;
- volatile __u16 lsr;
- volatile __u16 msr;
- volatile __u16 scr;
-} uart_reg;
-#endif /* ! __ASSEMBLY__ */
-
-/* Alias for Write Only Register */
-
-#define thr rbr
-#define tcr iir
-
-/* Alias for Divisor Latch Register */
-
-#define dll rbr
-#define dlm ier
-#define fcr iir
-
-/* Interrupt Enable Register */
-
-#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
-#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
-#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
-#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
-
-/* Interrupt Ident Register */
-
-#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
-#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
-#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
-#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
-#define IIR_FIFO 0xc000 /* FIFOs enabled */
-
-/* FIFO Control Register */
-
-#define FCR_FEN 0x0100 /* FIFO enable */
-#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
-#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
-#define FCR_DMA 0x0800 /* DMA mode select */
-#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
-#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
-
-/* Line Control Register */
-
-#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
-#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
-#define LCR_STB 0x0400 /* Number of Stop Bits */
-#define LCR_PEN 0x0800 /* Parity Enable */
-#define LCR_EPS 0x1000 /* Even Parity Select */
-#define LCR_SP 0x2000 /* Stick Parity */
-#define LCR_SB 0x4000 /* Set Break */
-#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
-
-/* MODEM Control Register */
-
-#define MCR_DTR 0x0100 /* Data Terminal Ready */
-#define MCR_RTS 0x0200 /* Request to Send */
-#define MCR_OUT1 0x0400 /* Out 1 */
-#define MCR_IRQEN 0x0800 /* IRQ Enable */
-#define MCR_LOOP 0x1000 /* Loop */
-
-/* Line Status Register */
-
-#define LSR_DR 0x0100 /* Data Ready */
-#define LSR_OE 0x0200 /* Overrun Error */
-#define LSR_PE 0x0400 /* Parity Error */
-#define LSR_FE 0x0800 /* Framing Error */
-#define LSR_BI 0x1000 /* Break Interrupt */
-#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
-#define LSR_TEMT 0x4000 /* Transmitter Empty */
-#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
-
-/* MODEM Status Register */
-
-#define MSR_DCTS 0x0100 /* Delta Clear to Send */
-#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
-#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
-#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
-#define MSR_CTS 0x1000 /* Clear to Send */
-#define MSR_DSR 0x2000 /* Data Set Ready */
-#define MSR_RI 0x4000 /* Ring Indicator */
-#define MSR_DCD 0x8000 /* Data Carrier Detect */
-
-/* Baud Rate Divisor */
-
-#define UART_CLK (1843200) /* 1.8432 MHz */
-#define UART_BAUD(x) (UART_CLK / (16 * (x)))
-
-/* RTC register definition */
-#define RTC_SECONDS 0
-#define RTC_SECONDS_ALARM 1
-#define RTC_MINUTES 2
-#define RTC_MINUTES_ALARM 3
-#define RTC_HOURS 4
-#define RTC_HOURS_ALARM 5
-#define RTC_DAY_OF_WEEK 6
-#define RTC_DAY_OF_MONTH 7
-#define RTC_MONTH 8
-#define RTC_YEAR 9
-#define RTC_FREQ_SELECT 10
-# define RTC_UIP 0x80
-# define RTC_DIV_CTL 0x70
-/* This RTC can work under 32.768KHz clock only. */
-# define RTC_OSC_ENABLE 0x20
-# define RTC_OSC_DISABLE 0x00
-#define RTC_CONTROL 11
-# define RTC_SET 0x80
-# define RTC_PIE 0x40
-# define RTC_AIE 0x20
-# define RTC_UIE 0x10
-# define RTC_SQWE 0x08
-# define RTC_DM_BINARY 0x04
-# define RTC_24H 0x02
-# define RTC_DST_EN 0x01
-
-#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
deleted file mode 100644
index e245f2a3cd78..000000000000
--- a/include/asm-sh/mpc1211/mc146818rtc.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * MPC1211 uses PC/AT style RTC definitions.
- */
-#include <asm-x86/mc146818rtc_32.h>
-
-
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
deleted file mode 100644
index fa456c3e4e01..000000000000
--- a/include/asm-sh/mpc1211/mpc1211.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __ASM_SH_MPC1211_H
-#define __ASM_SH_MPC1211_H
-
-/*
- * linux/include/asm-sh/mpc1211.h
- *
- * Copyright (C) 2001 Saito.K & Jeanne
- *
- * Interface MPC-1211 support
- */
-
-#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
-#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
-
-#define PCIPAR (0xa4000cf8) /* PCI Config address */
-#define PCIPDR (0xa4000cfc) /* PCI Config data */
-
-#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
deleted file mode 100644
index d9162c5ed76a..000000000000
--- a/include/asm-sh/mpc1211/pci.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Low-Level PCI Support for MPC-1211
- *
- * (c) 2002 Saito.K & Jeanne
- *
- */
-
-#ifndef _PCI_MPC1211_H_
-#define _PCI_MPC1211_H_
-
-#include <linux/pci.h>
-
-/* set debug level 4=verbose...1=terse */
-//#define DEBUG_PCI 3
-#undef DEBUG_PCI
-
-#ifdef DEBUG_PCI
-#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
-#else
-#define PCIDBG(n, x...)
-#endif
-
-/* startup values */
-#define PCI_PROBE_BIOS 1
-#define PCI_PROBE_CONF1 2
-#define PCI_PROBE_CONF2 4
-#define PCI_NO_CHECKS 0x400
-#define PCI_ASSIGN_ROMS 0x1000
-#define PCI_BIOS_IRQ_SCAN 0x2000
-
-/* MPC-1211 Specific Values */
-#define PCIPAR (0xa4000cf8) /* PCI Config address */
-#define PCIPDR (0xa4000cfc) /* PCI Config data */
-
-#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
-#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
-
-#endif /* _PCI_MPC1211_H_ */