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2016-01-14MLK-11521 ARM: dts: fix a typo for clock name 'pll1_bypass_src'Bai Ping
Fix a typo for clock name 'pll1_bypass_src'. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11518-05 ARM: defconfig: enable the device coolingBai Ping
Enable the device cooling device in the defconfig. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11518-04 thermal: imx: enable irq later when in thermal probeBai Ping
The tempmon irq handler should be register later when the tempmon module have been initialized in a known staus to avoid that the irq happened earlier when do probe. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11518-03 thermal: imx enable devfreq coolingBai Ping
Enable devfreq cooling to trigger GPU freq change when hot trip is reached. Make sure thermal driver loaded after cpufreq is loaded, otherwise, cpu_cooling will not get valid cpufreq table, hence cpu_cooling will be not working. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11518-02 thermal: imx: add .get_trend callback fn in thermal driverBai Ping
add .get_trend callback to determine the thermal raise/fall trend, when the temp great than a threshold, drop to the lowest trend (THERMAL_TREND_DROP_FULL). Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11518-01 thermal: imx: add thermal support for imx7Bai Ping
This pacth re-write part of the code the support i.MX6 and i.MX7 in thermal driver. the TEMPMON module in i.MX6 and i.MX7 can provide the same funtion, but has different register offset and bitfield define. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-10188 arm: imx: Add dummy LDO2p5 regulator for VBUS wakeupBai Ping
LDO2p5 cannot be disabled in low power idle mode when the USB driver enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy regulator that the USB driver will enable when VBUS wakeup is required. This patch is copied from commit 7d849e4d9ebca3c as code the structure has changed too many. directly cherry-pick has too many conflicts to resolve Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit 25a42aeb8eeb0b894a70e1a0f6750ced39830a46)
2016-01-14MLK-11499 ARM: imx: add low power idle for imx6slBai Ping
Add low power idle support for i.MX6SL. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11495-03 ARM: imx: fix the ARM/IPG ratio when busfreq enabledBai Ping
On i.MX6SL, we must make sure ARM:IPG clock ratio is within 12:5 when entering wait mode. If the system is in low_bus_freq_mode, the IPG is at 12MHz according the busfreq code. So the max rate of ARM is 28.8MHz when entering wait mode. As there is no way run at this clk rate, so set ARM to run from 24MHz OSC. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11495-02 ARM: imx: add busfreq support for imx6slBai Ping
Add busfreq support for i.MX6SL SOC. we support three busfreq mode (high_bus_freq_mode/low_bus_freq_mode and audio_bus_freq_mode). Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11495-01 ARM: dts: imx: add busfreq device node for imx6slBai Ping
Add busfreq device node for imx6sl. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11249-2 ARM: imx: add support for dynamic settings of gpc timingAnson Huang
On different platforms, the CPU power down/up timing may be different because of different requirements or different implementations in hardware, so we need to support dynamic setting of these timing, board level dtb file will provide these settings, and GPC driver need to read them and set them to the hardware. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit b0145b4e8556621cbe0d72e56cec5b04454db6c2)
2016-01-14MLK-11437-02 ARM: imx: change the pll1_sw/sys clks type on imx6Bai Ping
The 'PLL1_SYS' and 'PLL1_SW' clks are used by the cpufreq driver to do dynamic frequency changing procedure. The 'CLK_SET_PARENT_GATE' should not be set for 'PLL1_SW' clk, this clock's prepare_count is not zero all the time. change the clk type of 'PLL1_SYS' to fixed_factor. due to the hardware limit, when changing the ARM_PODF. This clock's output should not be gated. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11437-01 ARM: dts: imx: correct the clock info of cpu nodeBai Ping
The pll1_bypass and pll1_bypass_src clock index in cpu node should be IMX6SX_PLL1_BYPASS and IMX6SX_PLL1_BYPASS_SRC, so correct this. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11249-3 ARM: imx: improve i.mx6ul's low power idle settingAnson Huang
For low power idle with ARM power gated, per hardware requirement, there must be no interrupt coming during the power down process of ARM core, so RBC counter is enabled to hold interrupts. However, the previous setting of RBC counter is 1, which is ~30us, but the hardware design recommend a ~90us is required during ARM core power down, so we update the RBC counter value to 4(~120us) here. Previous delay loop to make sure RBC is actually enabled, 3us is needed, but the loop value assume ARM is running @1GHz, but actually ARM is running @24MHz now, so we need to update the loop value according to ARM speed. The ARM power up timing is based on IPG / 2048, IPG is 1.5MHz during low power idle, so the total latency of cpuidle exit should be updated accordingly. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit 4e1fd49da5e87c5cc23f053692e8d7648a4d4b21)
2016-01-14MLK-11234 ARM: imx: add RC-OSC freq initialization on imx6ulBai Ping
If in low power idle, we use the RC-OSC to reduce the power consumption, the RC-OSC freq need to be adjusted, otherwise, the RC-OSC freq is not very accurate. It may lead to system instability issue. Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit 8a93ab44e98bcc6611170734b829cd8d140dd722)
2016-01-14MLK-11204 ARM: imx: set int_mem_clk_lpm bit bit when entering wait mode on 6ulBai Ping
This bit is used to keep the ARM Platform memory clocks enabled if an interrupt is pending when entering low power mode. This bit should always bet set when the CCM_CLPCR_LPM bits are set to 01(WAIT Mode) or 10 (STOP mode) without power gating. Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit 0272868641041c5a9eb1b3476660711bb5cd69e4)
2016-01-14MLK-11021-03 ARM: imx6: add low power idle support on imx6ulBai Ping
Add the low power idle support on i.MX6UL. The ANATOP can enter low power when all PLLs are powered down. If need entering low power idle with LDO_2P5 and LDO_1P1 power down and other anatop module in low power mode, add "uart_from_osc' on command line to make sure the UART clk is from osc to let the PLL3 power down when entering low power idle. Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit 5215cba66938fd09f44e61b2c7b7ae0ef0629c2f)
2016-01-14MLK-11428 ARM: imx: enable busfreq support on imx6ulBai Ping
Enable the busfreq support on i.MX6UL EVK board. The busfreq support below 3 busfreq mode: * high_bus_mode: MMDC<--> 400MHz * audio_bus_mode: MMDC<--> 50MHz * low_bus_mode: MMDC<--> 24MHz Signed-off-by: Bai Ping <b51503@freescale.com>
2016-01-14MLK-11117-01 ARM: clk: imx6: adjust axi clock to 264MHz on imx6ulBai Ping
According to the latest reference manual, the default AXI clock rate should be 264MHz. Soucre AXI/AHB from pll2_bus to get the required clock rate. Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit d7560da7baee7a14ecb33d51182bbdc485ee6d7d)
2016-01-14MLK-11414-3 ARM: dts: imx: apply ENET IRQ workaround for sabresd boardShawn Guo
Cherry-pick below patch: ENGR00317981 ARM: dts: imx: apply ENET IRQ workaround for sabresd board This a forward porting of commit (ENGR00313685-15 ARM: dts: imx: apply ENET IRQ workaround for sabresd board) from imx_3.10.y to imx_3.14.y. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11414-2: ARM: dts: add dumb dts for enetirq and ldoShawn Guo
Cherry-pick below patch: ENGR00317981: ARM: dts: add dumb dts for enetirq and ldo Add a couple of dumb dts files for enetirq and ldo cases, which are asked by Yocto build for 3.14 kernel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11498 rpmsg: imx: tell remote process about the channelRichard Zhu
send a message to our remote processor, and tell remote processor about this channel Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com> (cherry picked from commit 2708c004a60c5b6da020803ee9291b83984d4a65)
2016-01-14MLK-11520 ARM: imx: enable axi clk in clk_init_on on i.mx6qdlAnson Huang
AXI clk should be always enabled, as many peripheral devices need this clk to be on, especially for busfreq, AXI podf change needs AXI clk and its parent on. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11431-4: ARM: DTS: imx: Update IPU and display propertySandor Yu
Update IPU and display property, make sure these dts files can pass build. Signed-off-by: Sandor Yu <R01008@freescale.com>
2016-01-14MLK-11431-3: ARM: DTS: imx6 Add IPU and display supportSandor Yu
Add IPU, HDMI and LDB support. Signed-off-by: Sandor Yu <R01008@freescale.com>
2016-01-14MLK-11431-2: ARM: defconfig: enable IPU and displaySandor Yu
Enable IPU, HDMI and LDB. Signed-off-by: Sandor Yu <R01008@freescale.com>
2016-01-14MLK-11431-1: IPU: forward IPU display drivers to 4.1.y kernelSandor Yu
Forward imx_3.14.y IPU and display drivers to 4.1 kernel. This includes IPU core driver, display driver, LDB and HDMI driver. Signed-off-by: Sandor Yu <R01008@freescale.com>
2016-01-14MLK-10103-2 cpufreq: imx6: increase SOC/PU voltage for vpu 352MAnson Huang
When VPU is running at 352MHz, SOC/PU voltage need to be at 1.25V for 396/792MHz setpoint, as 396M setpoint is removed, so only increase 792M setpoint's voltage. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-10103-1 ARM: imx: add VPU 352M for i.mx6qAnson Huang
When VPU freq is set to 352MHz, it needs to source clk from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change freq to 352M, cpufreq's 396M setpoint will be removed. Busfreq will be disabled as it needs PLL2_PFD2 to be as 396MHz to achieve low power audio freq setpoint. To enable VPU 352MHz feature, select it in menuconfig, it is disabled by default. Signed-off-by: Anson Huang <b20788@freescale.com> Conflicts: arch/arm/mach-imx/clk-imx6q.c arch/arm/mach-imx/mach-imx6q.c
2016-01-14MLK-11497-2 ARM: imx: add busfreq support for imx6q/dlAnson Huang
Add busfreq support for i.MX6Q/DL, 3 setpoints supported: HIGH: MMDC = 528MHz on i.MX6Q, = 396MHz on i.MX6DL; AHB = AXI = 24MHz; AUDIO: MMDC = 50MHz, AXI = 50MHz, AHB = 25MHz; LOW: MMDC = AXI = AHB = 24MHz. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11497-1 ARM: dts: add busfreq support for imx6q/dlAnson Huang
Add busfreq support for i.MX6Q/DL. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-10 arm: imx: add A9-M4 power managementAnson Huang
this patch adds A9-M4 power management, including below features: 1. busfreq: M4 is registered as a high speed device of A9, when M4 is running at high speed, busfreq will NOT enter low bus mode, when M4 is entering its low power idle, A9 will be able to enter low bus mode according to its state machine; 2. low power idle: only when M4 is in its low power idle, busfreq is staying at low bus mode, low power idle is available for kernel; 3. suspend: when M4 is NOT in its low power idle, when linux is about to suspend, it will only force SOC enter WAIT mode, only when M4 is in its low power idle in TCM, linux suspend can enter DSM mode. M4 can request/release wakeup source via MU to A9. as M4 can NOT switch its clk parent due to glitch MUX, to handle this case, A9 will help switch M4's clk parent, the flow is as below: M4: 1. enter low power idle, send bus use count-- to A9; 2. enter wfi and only wait for MU interrupt; 3. receive A9's clk switch ready message, go into low power idle; 4. receive interrupt to exit low power idle, send request to A9 for increase busfreq and M4 freq, enter wfi and only wait for MU interrupt; 5. receive A9 ready message, go out of low power idle. A9: 1. when receive M4's message of entering low power idle, wait M4 into wfi, hold M4 in wfi by hardware, gate M4 clk, then switch M4's clk to OSC, ungate M4 clk, send ready command to wake up M4 into low power idle; 2. when receive M4's message of exiting low power idle, wait M4 into wfi, hold M4 in wfi by hardware, gate M4 clk, then switch M4's clk to origin high clk, ungate M4 clk, send ready command to wake up M4 to exit low power idle; Signed-off-by: Anson Huang <b20788@freescale.com> Conflicts: arch/arm/mach-imx/busfreq-imx6.c arch/arm/mach-imx/pm-imx6.c
2016-01-14MLK-11488-9 arm: imx: add A9-M4 clk shared managementAnson Huang
As A9 and M4 share many resources on i.MX6SX, especially for clk and power related resource, so we need to handle the hardware conflict between these two cores, there are two cases that we need to consider currently: clk management: for every clk node, only when both A9 and M4 do NOT need it, then we can disable it from hardware; Here we use MU and hardware SEMA4 to achieve our goal, MU is for communiation between A9 and M4, SEMA4 is to protect the shared memory. For clk management, we use shared memory to maintain the clk status for both A9 and M4 side, and this shared memory is protected by hardware SEMA4, A9 and M4 will maintain their own clk tree info in their SW environment, and get other CORE's clk tree info from shared memory to decide whether to perform a hardware setting change when they plan to. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-8 arm: imx: adjust qspi device index according to dtb settingAnson Huang
When resume from DSM with Mega/Fast off, we need to restore the right QSPI module for M4, so get the qspi index from dtb file. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-7 arm: imx: add QSPI save/restore when M4 is enabledAllen Xu
As M4 is executing on QSPI2 flash, and QSPI is inside Mega/Fast domain which may lost power in DSM, so we need to do save/restore of QSPI2 controller to make sure QSPI flash can be accessed before waking up M4 after exiting from DSM. Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-6 arm: dts: imx6sx: add mu supportAnson Huang
add MU support for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-5 arm: dts: imx6sx: add m4 dts supportAnson Huang
1. add i.MX6SX SabreAuto board M4 dts support; 2. add shared memory node support for AMP clk/power management; 3. add qspi restore node for suspend/resume with Mega/Fast off when M4 is enabled and running on QSPI flash. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-4 arm: dts: imx6sx: add sema4 supportAnson Huang
add SEMA4 support for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-3 arm: imx: enable CONFIG_IMX_SEMA4 by defaultAnson Huang
enable CONFIG_IMX_SEMA4 by default. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-2 arm: imx: add HAVE_IMX_AMP for imx6sxAnson Huang
add HAVE_IMX_AMP and select by default for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11488-1 driver: char: sema4: add sema4 supportAnson Huang
- add linux sema4 driver. - use volatile types in sema4 structure. - align the port definiton a9 is 1, m4 is 2. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com>
2016-01-14MLK-11414-1 ARM: imx: add clk return check for imx6sxAnson Huang
This patch adds clk API return check for imx6sx. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-01-14MLK-11487 ARM: dts: add sound card support for imx6ul-14x14-ddr3-arm2 boardZidan Wang
add mqs, spdif and wm8958 sound card support for imx6ul-14x14-ddr3-arm2 board. Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
2016-01-14MLK-11444 ata: imx: cmd buf corruption errata bug fixRichard Zhu
errata: When a read command returns less data than specified in the PRDs (for example, there are two PRDs for this command, but the device returns a number of bytes which is less than in the first PRD), the second PRD of this command is not read out of the PRD FIFO, causing the next command to use this PRD erroneously. workaround - forces sg_tablesize = 1 - modified the sg_io function in block/scsi_ioctl.c to use a 64k buffer allocated with dma_alloc_coherent during the probe in ahci_imx - In order to fix the scsi/sata hang, when CD_ROM and HDD are accessed simultaneously after the workaround is applied. Do not go to sleep in scsi_eh_handler, when there is host failed. Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
2016-01-14mmc: host: use of_property_read_bool()Sergei Shtylyov
Use more compact of_property_read_bool() calls instead of the of_find_property() calls. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 90614cd9045dc7003913ee58cbc77950351485a0)
2016-01-14mmc: core: Fixed bug in one erase-group budget TRIMRobin van der Gracht
When requesting a trim for several bytes, everything up to the next erase-group is erased. This causes data corruption. Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 22d7e85ff8e5826845e9a4fa34b4723e5a97ee9b)
2016-01-14mmc: sdhci-esdhc-imx: change default watermark level and burst lengthHaibo Chen
By default, for all imx SoC types, the watermark level is 16, and the burst length is 8. But if the SDIO/SD/MMC I/O speed is fast enough, this default watermark level and burst length will be the performance bottleneck. For example, i.MX7D support eMMC HS400 mode, this mode can run in 8 bit, 200MHZ DDR mode. So the I/O speed improve a lot compare to SD3.0. The default burst length is 8, if we don't change this value, in HS400 mode, when we do eMMC read operation, we can find that the clock signal will stop for a period of time. This means the speed of data moving on AHB bus is slower than I/O speed. So we should improve the speed of data moving on AHB bus. This patch set the default burst length as 16, and set the default watermark level as 64. The test result is the clock signal has no stop during the eMMC HS400 operation. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit e31e67cf2578bd05e99afabb22403542306d6bed)
2016-01-14mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1Haibo Chen
Currently we find that if a usdhc is choosed to boot system, then ROM code will set the burst length enable bit of this usdhc as 0. This will make performance drop a lot if this usdhc's burst length is configed. So this patch set back the burst_length_enable bit as 1, which is the default value, and means burst length is enabled for INCR. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit fd44954e77b436673eb5221e5485a32ea6550128)
2016-01-14mmc: sdhci-esdhc-imx: add tuning-step setting supportHaibo Chen
tuning-step is the delay cell steps in tuning procedure. The default value of tuning-step is 1. Some boards or cards need another value to pass the tuning procedure. For example, imx7d-sdb board need the tuning-step value as 2, otherwise it can't pass the tuning procedure. So this patch add the tuning-step setting in driver, so that user can set the tuning-step value in dts. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit d407e30ba614b1542c8ac032f8fb2332b8071efe)
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