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Bug 913416
Change-Id: I19f45bcd2c1ef9cb625728294b1dd53695e7d64b
Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-on: http://git-master/r/69938
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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disable sensor AE/AWB and update coarse integration time
and gain settings on a mode change.
Bug 914413
Change-Id: I9121896521f47bc71f0aad9e88a1226dc8388774
Signed-off-by: Abhinav Sinha <absinha@nvidia.com>
Reviewed-on: http://git-master/r/69864
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Change-Id: I0715fc3ef5c3cb97ac317e46c63199cdae547737
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/69891
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Added support for EDP in tsensor. Since low limit
interrupts are not supported in hardware TH2 was
used for upper limit and TH0/TH1 as lower limit.
Also added generic functions to enable tsensor for
thermal refactoring.
Bug 912597
Change-Id: I8f1e126e1fe11c69aa03dee0a20a26ef2b7dc6a0
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/66554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Colin McCabe <cmccabe@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Change-Id: Idb51349471414b4ab6eb84de51a449077865021e
Reviewed-on: http://git-master/r/69872
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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With this commit below changes to ricoh583 MFD are done:
1. Updating cache copy of int enable register.
2. Changing the prototypes for bulk read & write APIs.
3. Updating rtc platform data structure.
bug 902137
Change-Id: I616d86628addaaa04f3faec035120bd6f9569603
Signed-off-by: venu byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/70010
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Enables high speed clock on mipi lanes in low power mode.
Change-Id: I3b05d7f9bc5e8f63483220100f3361904e627c52
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/69951
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Use AND operator instead of equality operator to test for
NO_UNION_NORMAL quirk. This allows devices with multiple
quirks to be properly tested against the NO_UNION_NORMAL
feature.
Change-Id: I4c6b019f161ddd91f40ad8e533cab2b435a68ddb
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: http://git-master/r/69892
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Updated i2c platform data to add i2c arb lost recovery funtion
and corresponding gpio numbers to i2c pins
This is cherry pick of change http://git-master/r/#change,47290
Change-Id: I4098a512625c16598b8596d0e46d285ca9b92d2b
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/69717
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
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Adding tegra2 null ULPI phy restore function and clean up code in usb_phy.
Bug 907350
Bug 912407
Change-Id: I93aa191cd7f9fdace7f80a66fedbf034728e2fe9
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/67189
Reviewed-by: Martin Chabot <mchabot@nvidia.com>
Tested-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Jonathan Roux <jroux@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Restore IRQ affinity to multiple CPUs after LP=>G CPU mode switch.
Change-Id: Id7c263f2a11535669d1e9988f4e15b240a7fde38
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/69329
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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GIC IRQ affinity is currently set to one CPU only - the 1st cpu in
the requested mask. This commit adds option to set IRQ affinity to
all cpus present in affinity_hint and requested masks. The option is
enabled by default on Tegra architecture starting with Tegra3.
(cherry picked from commit 09f7ef4f28a6e18188649c40848252bc18a6646c)
Change-Id: I0d655f1d39170382f3372294172ed6d02dc0ad49
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/69328
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Sample code for enabling INA230 (/ INA226) current monitor for battery
EDP capping on Enterprise
Change-Id: I2c5b919dca4c9e31aa1432cc45ae0486700e02de
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/61968
Reviewed-on: http://git-master/r/69112
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Adds support for current monitoring for battery EDP capping
Change-Id: I85fc1770013ab80b986b3b6d77ffd96e1dc4068f
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/60560
Reviewed-on: http://git-master/r/69111
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Tested-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Init code for system edp tables for Enterprise (aka battery edp
capping, aka battery peak current management); disabled by default.
Change-Id: I8cff00dba18576a3fabf5542e609bca010de9d0f
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/65612
Reviewed-on: http://git-master/r/69107
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Register the battery peak current management device, that can trigger
cpu frequency/voltage change when GPIO is triggered by battery current
monitoring device.
Change-Id: I5a79ed2d3e057a51a7dc3953b8c252f4ee5b9a6a
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/68816
Reviewed-on: http://git-master/r/69104
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Change if statement to support E1513 A01 board in E1197.
Add tegra_get_camera_board_info to parse camera module id
that is passed in from bootloader.
Bug 914552
Change-Id: I20c3bcaf181e29446aa254ea189d917bc6905488
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/69504
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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This driver reduces CPU frequency in half by setting the CCLK_DIVIDER on
GPIO level triggered event by current monitoring device. It then calls
dvfs apis to reduce cpu frequency/voltage.
Change-Id: I703e2277243df5328ee6a46478ec8b7a3dab93aa
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/68794
Reviewed-on: http://git-master/r/69103
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Change-Id: Ie87bb2e71e8ce5cd8c249d0db196bf4e5c5e2ae4
Reviewed-on: http://git-master/r/71039
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Chris Johnson <cwj@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Commit 7fbb6eaca74d961fde208be87c89d703d5eff5ad in
android-tegra-nv-2.6.39 replaced mpu3050 with inv_mpu.
The cherry-picked commit on this tree just adds inv_mpu
commit f1e961e877025f60cc409180350a3def85f26f64
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: I46194ea10cc8154c50a8b16c163bedf29a35d544
Reviewed-on: http://git-master/r/70628
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for bug 914934
Change-Id: I34892961074d5c23efb19a7e53688f227e0bf03d
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/70557
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Software SH256 Cryptographic hash algorithm is needed
to support basic software encryption functionality.
Bug 882031
Change-Id: I05c9452ee6283e2cac1cf0049e5446b2556d7dd5
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/69745
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Set tegra->irq to 0 if the ehci irq cannot be used as a wake source and
do not disable it when removing the ehci to avoid unbalanced irq wake
enable/disable problem.
Bug 884315
Change-Id: I9abf9f5f28d61b71d8a96b6ffcbb5ba6d899b3c0
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-on: http://git-master/r/69716
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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init cache values for dam/ahub/apbif register by reading
the power on reset values in respective driver probe functions
bug 911332
Change-Id: I693baeff3e076095d3c7f225f1768a4082f7d305
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/69679
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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To prevent power rail turn-off when change FPS source,
it must set power mode to NORMAL before change FPS source to NONE
from SRC_0, SRC_1 and SRC_2.
Change-Id: I02be96bd91ffb756a79a440d319fafe1739ae514
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/69566
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Fixed warning message
Bug ID: 912669
Change-Id: I3090c35a5d0725102c101b10a99914510a272fa4
Reviewed-on: http://git-master/r/69444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Registering SPI1 as slave device which will be used in
loopback tests on E1198
Bug 903874
Reviewed-on: http://git-master/r/66790
(cherry picked from commit 87d7bc65a43dbb3a745c1bcb03e53ba44f8e80e9)
Change-Id: I22aeca2457dcb38125de48275e00c268fbe8792b
Reviewed-on: http://git-master/r/69189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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3d.emc clock will be scaled proportionately to the rate chosen
for 3d.cbus clock.
Bug 911223
Change-Id: I903ad7e3f6c33c3d3119e8b9810839edb1084596
Signed-off-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-on: http://git-master/r/69021
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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bug 880495
Change-Id: Ic89487c6296b20377ee12a135d06bef5b5c8b6fa
Reviewed-on: http://git-master/r/68983
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Currently, EMC rate is mostly controlled by CPU frequency
assuming that higher CPU freqeuncy requires more mem B/W.
However, some of the 3d apps makes GPU very busy while CPU
is mostly idle. This patch changes HOST_EMC_FLOOR to UINT_MAX
allowing GPU to utilize full mem B/W when it is active.
This may be re-visited when 3d scaling is enabled since we might
be able to scale EMC rate dynamically based on 3d rate.
Bug 911223
Change-Id: I8eb7b3991abe3bd664441bfc1f43075984dafcaa
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/68650
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug 886459
Change-Id: I9ffce0e0186cace45c403ae6880f3460ed3ede47
Signed-off-by: Raj Jayaraman <rjayaraman@nvidia.com>
Reviewed-on: http://git-master/r/68307
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug 886459
Change-Id: Id6efa14da2de776208fba2fe58624c79cca809ed
Signed-off-by: Raj Jayaraman <rjayaraman@nvidia.com>
Reviewed-on: http://git-master/r/68285
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Change-Id: Ifd53d0cb0cd6022c3f526df3ba79cd4369796749
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/69783
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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If AP is set as slave set audio_sync clock as source of i2s controller
clock and use pll_a_out0 as i2s controller source in AP master mode.
This change is needed to support AP slave mode reliably on Tegra30.
Bug 911332
Change-Id: I91e54d1d297c58ad65baac86831bccfbaadf732c
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/69777
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Enable multiple contexts for MPE.
Bug 827192
Change-Id: I112ddbdc099efdce3f214161ae454bce34158dc7
Reviewed-on: http://git-master/r/69690
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Set i2s_sync clocks as parent of audio clocks in tegra_clk_init_table.
Entries are added only for active I2s ports for corresponding Tegra30
board.
Bug 911332
Change-Id: I86440cbff6432fcec3de249c9baf46aab785122f
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/69757
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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For I2s slave mode i2s clock needs to be generated from audio_sync
clock. So depending on codec master/slave mode parent of i2s clock
needs to be changed in runtime. To support this i2s_sync, audio and
audio_2x clocks needs to be accessed from I2s driver. To facilitate
accessing of all these clocks add dev_id and con_id fields for these
clocks.
Bug 911332
Change-Id: I92094ac563de8025f7d88eb47e439098c98111bb
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/69756
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
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This is a preparation change for using dev_id and con_id fields for
audio sync clocks. Use con_id field for i2s clock to get proper
clock.
Bug 911332
Change-Id: I6aa795624379c00075868d8529bff6e131299a40
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/69744
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Don't free i2s context in I2s platform driver probe failure case
since it is statically allocated.
Change-Id: Ia1fb7e17493b8906a36e658ded925f0f414aae23
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/69729
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
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when system resumes from suspend state the i2s/das/spdif registers
have power on reset values, this change restores the registers
with their prior values from cache
Bug: 904530
Change-Id: I35c14d95d2d6bf5bc116a1a80e21f4904c8969e5
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/69715
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Since front and back right camera are multiplexed,
back right camera needs to be selected on power on.
Bug 890780
Change-Id: I6c9ecb95c42b3faedfede98b7e7de7e778d720b6
Signed-off-by: Anton Kondratenko <akondratenko@nvidia.com>
Reviewed-on: http://git-master/r/69662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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If loading the normal video ucode file fails, try an alternative.
Bug 912656
Change-Id: I5de9af222e46dcec21f821e78ea115800cbf4805
Signed-off-by: Isaac Richards <irichards@nvidia.com>
Reviewed-on: http://git-master/r/68755
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-by: Mohan Nimaje <mnimaje@nvidia.com>
Reviewed-by: Mandar Potdar <mpotdar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Get timing register value from platform data
instead of timing structure.
Fix NOR device registration using tegra_nor_device.
Signed-off-by: Manoj Chourasia <mchouraia@nvidia.com>
Reviewed-on: http://git-master/r/56889
(cherry picked from commit f77e726ec89d09ba3174a395d9f98c1b02a83c58)
Change-Id: Ie5ea216a770c998dd2ce578f206f83bcbd248fd2
Reviewed-on: http://git-master/r/67710
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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set global shutdown bit to zero so that codec will shutdown in
bias off case
bug 899662
Change-Id: I86cf5d9567463166fc3ee0585083faba35dac301
Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Reviewed-on: http://git-master/r/63858
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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This patch adds NOR mapping driver for tegra2 and tegra3.
Signed-off-by: Manoj Chourasia<mchourasia@nvidia.com>
Change-Id: Ie773d024a49977e356d4a9d605910ca30f22a3f3
Reviewed-on: http://git-master/r/43566
Reviewed-on: http://git-master/r/62149
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Skip page table attribute update for carveout.
Bug 914347
Change-Id: I6a1deeadade17703e831268dc58360ebc35af915
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/69539
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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convert cpa lock to mutex from spin lock.
This is needed as page allocs, which can sleep, are happening
inside the spinlock.
Bug 913652
Change-Id: I8a31e31c2ca8f7631ec626a82a74509494f47219
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/69517
Reviewed-by: Automatic_Commit_Validation_User
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Combines i2c cmds that have sequential addresses into one bulk i2c write
cmd. This will save the overheads of slave addr + offset and the latency
time.
bug 816814
Change-Id: I7b3808e8af17dd805452672e4386033d8383fb91
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/68326
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Add kernel config flags in "tegra_defconfig" & "tegra3_defconfig" to enable
camera sensor,focuser & torch devices.
This is to enable Camera capture on L4T with T20 Ventana & T30 Cardhu.
Bug 869132 & 880107
Change-Id: Ib81908881c8936e7b3dd7ebdcfd9bba006aa343f
Cherry-picked From : f09adb0d15f0991d0e7116f7a1092339bf92f9e9
Reviewed-on: http://git-master/r/55977
Signed-off-by: Amit Pandya <apandya@nvidia.com>
Reviewed-on: http://git-master/r/68165
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Implement context switching for MPE. This allows doing multiple video
encodings at the same time.
Context switching relies on wait base being in sync with sync point. As
MPE user land does not use wait bases, the patch also enables automatic
wait base syncing.
This patch does not enable the context save/restore.
Bug 827192
Change-Id: I510c02fb6d02ffbc1b9537d33474d46022b6cf59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/66881
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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