Age | Commit message (Collapse) | Author |
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Updated several comments to make code easier to read and understand.
Also use the front_porch workaround in any case, for HDMI output
too.
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Use modedb to set mode on framebuffer/display controller for
Tegra 20 based module Colibri T20 too.
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In order to find a viable resolution we not only parse VESA mode,
we also parse CEA (multimedia) modes and our own small modedb (for
specific touch screens).
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Use new modedb based framebuffer settings by defining default_mode
in the display controllers platform data. Also impelmented the
fallback logic to this default_mode in case no kernel cmd line
parameter was set.
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Allow to specify framebufffer videomode using kernel command line
parameters. NVIDIAs binary X driver later on picks up those settings
and start X with current mode settings, if no EDID data are available.
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Disable hardware statistics monitor for AVP due to it completely
hanging upon boot on certain Colibri T20 V1.2a modules.
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Make use of the new STMPE ADC driver to expose the four free ADC
channels on the STMPE811 to userspace.
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This adds an ADC driver for the STMPE device using the industrial
input/output interface. The driver supports raw reading of values.
The driver depends on the MFD stmpe driver. If the touchscreen
block is enabled too, only for of the 8 ADC channels are available.
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In order to use the auxiliar ADC inputs of STMPE811 devices we need
to add resources for the ADC block. Also move the ADC macros from
the touchscreen driver to the general header file. We will need them
for the ADC driver in future.
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The drivers internal root_bus_nr used to be u8 which lead to a wrong
error detection in bus_to_port. Bus number can be -1 in case bus is
not scanned yet. Thanks to James pointing that out.
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The voltage table for the SM2 regulator on TPS658643 was wrong. However,
since the requested voltage of 1.8V was at the right place, the system
worked fine nonetheless.
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The port used for KEY_BACK does not support wakeup (no wake PIN). Remove
the wake flag, this prevents unbalanced irq warning messages.
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Add GPIO keyboard platform device configuration. Currently only the power key
is defined which is registred as wake key as well in order to wake the SoC when
in sleep mode (MXM3 37/WAKE1_MICO).
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After suspend, mode filter might be called with empty yres. This leads
to division by zero when checking aspect ratio. Return as invalid mode
when yres is zero.
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When enabling SATA clocks, the PCIE clocks are enabled as well since
those are the parent clocks. In order to enable this parent clocks,
the PCIE regulator avdd_plle needs to be enabled. The resume path used
to freeze because the PCIE PLL did not lock.
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SKU 0x81 is identical to 0xB1 so same can be used
for sku to speedo ID conversion.
Bug 1313434
Change-Id: I63f08522878524a05c2a6fb0a82fee90a59a99bd
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/334396
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Remove vdd_hdmi_con regulator from dc1 since we don't have a dedicated
regulator for this connector on our baseboards.
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Use TPS6591X IRQ base define to calculate correct IRQ number.
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Use TPS6591X base defines to make sure the chip gets its own irq range rather
than interfer with the STMPE chip.
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Setting the resolution to 1088p (as of now), since
there are flickers observed for 1080p and also
the encoder is not compatible with alignement of
the RM surfaces of 1080p. 1088p is a stop-gap solution
until the issues with 1080p are resolved.
Bug 1369083
Change-Id: I3e73076451e7671d90603c6496ad14733591edeb
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/309543
Tested-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaustubh Purandare <kpurandare@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Bug 1369083
Change-Id: I1a81bcb62e8f6bb654ffbebba09661187ab4b512
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/309536
Tested-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaustubh Purandare <kpurandare@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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The tweaks are only specific to r16-r2 branch
and will not go into mainline.
- Pass nvmap memory handle to the user through
the mmap'd buffer allocated by videobuf2 client.
- Allow the "user" nvmap client to access the
nvmap memory handle of "videobuf2-dma-nvmap" client.
Re-arranging the copyright message in nvmap_dev.c
for Automatic validation to pass.
Bug 1369083
Change-Id: Ia27d172253860e79557911c2e848bc9084d662d4
Signed-off-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-on: http://git-master/r/309494
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Kaustubh Purandare <kpurandare@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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This reverts commit dd9a841da571a41d43f1eeaac1785b2adb1d80f3.
The config changes (for V4L2) can be done manually as per need
basis for V4L2, followed by compiling the kernel.
Change-Id: I9174bce0f3da2974ab703b238dfb8fb3bbf607c5
Signed-off-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-on: http://git-master/r/327607
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaustubh Purandare <kpurandare@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Fix errors when registration fails, correctly unregister the
platform device.
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- Disables TEGRA_CAMERA
- Enables SOC_CAMERA and OV5640 sensor support
Bug 1369083
Change-Id: I073c226e9f04a6f4f4699051f624a755dceb36cb
Signed-off-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-on: http://git-master/r/309491
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Clean-up GPIO definitions and names (e.g. use LVDS_ defines, BKL1_ON
rather than BL_ON and HDMI1_HPD rather than hdmi_hpd).
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When hotpluging hdmi the read of edid often fails.
Add up to 4 retries with a 500ms delay before giving up.
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This gives the DDR3L memory settings for 400MHz/800MHz.
The boot memory speed must be 400MHz for this to work, i.e.
the 400MHz BCT must be used.
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If the boot console is RS232 and RX is left floating this leads
to arbitrary sys requests including reboots...
(RX is left floating on the evaluation boards if USB to serial is
jumpered but USB is not connected)
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Bug 1369083
Change-Id: I1522b688e0681e52592c0f26a8e335937372836a
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/279989
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Enable OV5650 and OV5640 sensor in Cardhu board file with the help of
Tegra V4L2 SoC camera interface.
To use V4L2 driver, we need to disable old camera HAL driver.
Bug 1240806
Bug 1369083
Change-Id: I0dc529d44fba4d80b45690e384e8bf81b29f69e5
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246266
(cherry picked from commit 6b2f7cc4117208dc992478f27d5873ea38071fdc)
Reviewed-on: http://git-master/r/279988
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Add support for dual cameras from both CSI-A and CSI-B:
- move all the CSI settings into video buffer struct
- queue the video buffer struct to a dedicated queue
- process one video buffer struct from the queue at one time
Bug 1369083
Change-Id: Ie64d69282ab991b66e97327e288a2bacde088bd6
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246269
(cherry picked from commit 228b0c2d9ae3fa1121f88836626d654ae0fc4ff0)
Reviewed-on: http://git-master/r/279987
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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soc_camera_link supports passing power on/off control callback to
soc_camera stack. So the power control can be handled by soc_camera
stack instead of our Tegra V4L2 host driver.
Also pass other platform_data fields via soc_camera_link instead of
a hacking nvhost_device_data struct.
Bug 1240806
Bug 1369083
Change-Id: I443a7d28196cc8292805da70d2d5ff1c3cd50a5d
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246267
(cherry picked from commit 9083d270bf93b583cd5bf5151a52ea250f8541a3)
Reviewed-on: http://git-master/r/279986
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Bug 1369083
Change-Id: I43acb0d1dd6ca182291895d294a8458bfc99da05
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/279985
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Use right buffer flag NVMAP_HANDLE_WRITE_COMBINE to allocate buffer,
which can be shared by VI/CSI and CPU. Don't use NVMAP_HEAP_SYSMEM.
It is validated to old T20 silicon and can't support big buffers. By
default, our nvmap_alloc() will use IOVMM to allocate buffers.
nvmap_pin() gives us IOVA for hardware engines like VI/CSI module
with IOMMU enabled in kernel. nvmap_mmap() gives us VA for CPU
read/write operations. So we need to convert VA address to physical
address of the buffer and map that buffer to user space processor's
memory space "page by page".
Bug 1369083
Change-Id: I4629eebe206c7640adf63551968fd89260dd0082
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/279984
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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- tweak offset registers
- add test mode to output color bars
- use BGGR RAW format
Bug 1369083
Change-Id: I61352c018f8ca099ff3d39158a67052a1e185eec
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/279983
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Reworked driver in order to properly support default watchdog api
such as triggering by writing a character and disable by sending
a magic character. Renamed ENABLE_ON_PROBE to ENABLE_HEARTBEAT
which triggers the watchdog using the interrupt service routine.
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Configure pll_a during boot so that
locking to pll_a does not fail
Bug 1330751
Change-Id: I188f0be211379f43770b24c5b382dec2788aefda
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/269469
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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DVFS entry is fixed for Hynix_2GB_H5TC4G83MFR-PBA
to support all emc frequencies.
Bug 1218885
Change-Id: Id9d578499e495f43db1a072cbcee25a353fa78f5
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/210653
(cherry picked from commit 688bf04ff67e2c1ff22762f4f578b925ff3b9f3c)
Reviewed-on: http://git-master/r/273530
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Initialisation of the framebuffer console on DVI-D aka HDMI always
failed on monitors which report the vertical front porch to be 1
in their EDID.
The fix now changes also the modedb and not only the list of
videomodes with a compatible timing.
This was particularly bad on Apalis T30 where this is activated
by default. On Colibri T30 this was observed when enabling it using the
fbcon=map:1 boot argument.
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Up to now only the LVDS transceiver controlling GPIOs were exported.
This patch adds the generic Apalis GPIOs to the list of via sysfs to
userspace exported ones as well.
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Initialisation of the framebuffer console on DVI-D aka HDMI sometimes
failed. This was particularly bad on Apalis T30 where this is activated
by default. On Colibri T30 this was observed when enabling it using the
fbcon=map:1 boot argument.
This fix curtsey of Bibek Basu from NVIDIA explicitly enables PLLA
during early clock initialisation which avoids a later race with the
display driver on DC1.
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fix Coverity issue
Coverity id : 13692
Bug 1046331
Bug 1049868
Change-Id: Iefa6d076d4622368534710630b89b9a15d166378
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/165864
(cherry picked from commit db33c3f3f2447a52a40f4fd001fec9a2932ee4c8)
Reviewed-on: http://git-master/r/244637
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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In preparation for the new Apalis resp. Colibri T30 production lots
with either T30IQS-P-A3 or T30MQS-P-A3 chips that due to some bug were
locked at 312 MHz force a speedo ID of 2 for now which allows regular
operation of up to 1.4 GHz (single core only).
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I211 with a blank iNVM uses a different PCI ID. Hack the driver to load
despite i211 data sheet claiming tools only, not for driver.
Please note that the existing driver hacks concerning NVM validation
skipping and Ethernet MAC address assignment equally apply.
Tested on initial samples of Apalis T30 1GB V1.0A.
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The firmware is not being in use currently.
So, turn the loading code off.
Bug 1236060
Bug 991551
Change-Id: Id41cf762b59502d0ece470e315ac75d93e3b6b39
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/218613
(cherry picked from commit f15976bdfb32d6c5e20057f6d4d57646c15a5591)
Reviewed-on: http://git-master/r/258354
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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According to Realtek, the firmware provides
power optimizations. The driver works without
the firmware. Plus, there are scenarios where
the firmware is not available, which makes the
driver wait at request_firmware call (i.e.,
60 sec wait).
Bug 1236060
Bug 991551
Change-Id: Ifcaa4b2dd48c4111ded33cf2bade7dc1f6422821
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/258353
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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