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- MX6 sololite cpu board NFS boot fails in sometimes, because MAC
cannot get any packets while sending DHCP to require IP. The
reproduce rate is 10%.
- Lan8720 phy enter a unexpected status, and need software reset
phy before transmition.
- Do some below overnight tests after add the changes, no NFS
boot issue found.
1. Kernel boot from MMC, rootfs mount from NFS.
2. Kernel boot from tftp, rootfs mount form NFS.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Previous flow when we change PLL1_SW_CLK from 400M
PFD to PLL1_MAIN_CLK is as below:
1. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK;
2. change PLL1_MAIN_CLK's freq if necessary;
There is chance that the PLL1_MAIN_CLK freq is higher
than what we want, then after step1, system may hang as
we use low voltage to run high freq.
The correct flow should be as below:
1. make sure PLL1_MAIN_CLK is enabled;
2. make sure pLL1_MAIN_CLK freq is what we want;
3. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Busfreq should be enabled at boot by default on i.MX6SL.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Set conservative governor as default governor.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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one sysfs interface for offset_discharger ,one sysfs interface for
offset_charger.
Signed-off-by: Rong Dian <b38775@freescale.com>
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- Kernel will print dma free warning when no Sipix panel
connect. Fix dma free unmatched size.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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kernel dump when do "modprobe -r mxc_v4l2_capture"
this is caused by unregister wrong v4l2 int device when rmmod
Signed-off-by: Wu Guoxing <b39297@freescale.com>
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disable imx6 usb charger default
Signed-off-by: Rong Dian <b38775@freescale.com>
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Bind usb charger with power supply, and print some attributes about
usb charger.
Signed-off-by: Rong Dian <b38775@freescale.com>
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add get_supplier_property interface.
This patch was written by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
originally.
Signed-off-by: Rong Dian <b38775@freescale.com>
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- Add variable pad speed setting per SD clk freq.
- Add SD3.0 support on SD1, SD2, and SD3.
- Enhance drive strength on SD pad to improve its compatibility.
- change the definition of pad speed changing interface
- combine pad speed setting for different SD host controllers into one function.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
Acked-by: Lily Zhang
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- Correct switcing signaling voltage sequence according to SD3.0 spec,
that turn off SD clk before switching signaling voltage.
- previous code can work on MX6Q but failed on MX6SL.
- only have sequence corrected, it can work on MX6SL.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Conflicts:
arch/arm/mach-mx6/devices-imx6q.h
drivers/power/sabresd_battery.c
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Add VDOA tiled field format support for V4L2 output driver
Also add some debug information
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Add IPU_MAX_VDI_IN_WIDTH for I.MX IPUv3 hardware
For chrome buffer address(uoff) should be offset from luma buffer address
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Remove some unused code in battery driver
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Remove redefined Item in Kconfig And Makefile for MAX11081
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Also, clear OCRAM_CTL bits to disable OCRAM read/write pipeline control.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Add support for SoC power optimization in Idle mode (1st phase):
1. ARM @ 198MHz. VDDARM_CAP @ 0.85V
2. AHB @ 24MHz, DDR @ 25MHz
3. PU regulator disabled when system is in IDLE.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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As MX6SL has replaced CAAM with DCP+RNGB, CAAM configs need to be
removed from mx6s defconfig.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Previous configuration suppressed a number of crypto API features that
caused misleading results when using the CAAM driver through the tcrypt.
Enabling the API tests eliminated this.
Also, added in other common ciphers and modes that, if lacking, would
cause confusion with tcrypt behavior.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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As Arik TO1.0 GPT use ipg_perclk as clock source, we need to
lower it to 6M before init GPT, or the clock source freq will
be wrong if we lower the ipg_perclk after GPT time already init.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Remove some unused code in battery driver
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Fix below issue:
[<c00ad820>] (wake_lock_internal+0x288/0x344) from [<c0372174>]
(power_supply_changed+0x28/0x40)
[<c0372174>] (power_supply_changed+0x28/0x40) from [<c0372d70>]
(max8903_battery_update_status+0xc4/0x120)
[<c0372d70>] (max8903_battery_update_status+0xc4/0x120) from
[<c0372fe8>] (max8903_battery_get_property+0x2c/0x1ec)
[<c0372fe8>] (max8903_battery_get_property+0x2c/0x1ec) from [<c03723f8>]
(power_supply_show_property+0x3c/0x1ac)
[<c03723f8>] (power_supply_show_property+0x3c/0x1ac) from [<c0372600>]
(power_supply_uevent+0x98/0x19c)
[<c0372600>] (power_supply_uevent+0x98/0x19c) from [<c028969c>]
(dev_uevent+0xa4/0x170)
[<c028969c>] (dev_uevent+0xa4/0x170) from [<c0240c20>]
(kobject_uevent_env+0x1b4/0x454)
[<c0240c20>] (kobject_uevent_env+0x1b4/0x454) from [<c028a2d4>]
(device_add+0x49c/0x570)
[<c028a2d4>] (device_add+0x49c/0x570) from [<c0372230>]
(power_supply_register+0xa4/0x110)
[<c0372230>] (power_supply_register+0xa4/0x110) from [<c0564300>]
(max8903_probe+0x2f8/0x688)
[<c0564300>] (max8903_probe+0x2f8/0x688) from [<c028d178>]
(platform_drv_probe+0x18/0x1c)
[<c028d178>] (platform_drv_probe+0x18/0x1c) from [<c028bebc>]
(driver_probe_device+0x98/0x1a8)
[<c028bebc>] (driver_probe_device+0x98/0x1a8) from [<c028c058>]
(__driver_attach+0x8c/0x90)
[<c028c058>] (__driver_attach+0x8c/0x90) from [<c028b708>]
(bus_for_each_dev+0x60/0x8c)
[<c028b708>] (bus_for_each_dev+0x60/0x8c) from [<c028afd8>]
(bus_add_driver+0xa0/0x234)
[<c028afd8>] (bus_add_driver+0xa0/0x234) from [<c028c64c>]
(driver_register+0x78/0x144)
[<c028c64c>] (driver_register+0x78/0x144) from [<c0040520>]
(do_one_initcall+0x34/0x17c)
[<c0040520>] (do_one_initcall+0x34/0x17c) from [<c00083e8>]
(kernel_init+0xb4/0x160)
[<c00083e8>] (kernel_init+0xb4/0x160) from [<c0047074>]
(kernel_thread_exit+0x0/0x8)
for the wake lock in power_supply_register() route is not initialized
so in wakelock_internal(), it will cause BUG(), and then system crash
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Enable MAX11081 for reading battery voltage
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Remove redefined Item in Kconfig And Makefile for MAX11081
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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When bus freq is changed, we need to update periph
clk's parent, better to use clk_set_parent API instead
of changing the parent directly.
Signed-off-by: Anson Huang <b20788@freescale.com>
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interface and modify driver
1.add battery sample voltage offset sysfs interface.
2.add usb charger powersupply from max8903 UOK.
3.modify battery max coulomb data to 99% in charger full stage and
modify battery max coulomb data to 100% in discharger stage,because
hardware cannot support battery internal resistance and coulomb
calculation.Battery voltage and coulomb may increase a bit in charger
stage,so keep max coulomb data 99% in charger full stage.
Signed-off-by: Rong Dian <b38775@freescale.com>
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Fix:
WARNING: vmlinux.o(.data+0x8c28): Section mismatch in reference from the
variable mx6_gpmi_nand_platform_data to the function
.init.text:gpmi_nand_platform_init()
The variable mx6_gpmi_nand_platform_data references
the function __init gpmi_nand_platform_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add ELAN capacitive TS support on EINK-DC3 stacked on MX6SL_ARM2 board
- configure the iomux setting (need 4.7K Ohm pull up on 'touch_int_b')
- configure the i2c slave addr
- configure the GPIO setting for ELAN ce/int/rst
- update the defconfig
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add the support for keypad on EINK-DC3 board which is stacked on ARM2 board.
- configure the iomux setting
- add dummy kpp clock to fool imx_keypad driver
- add platform device for keypad
- add key mapping (4x4 array) used on EINK-DC3
- update the defconfig for keypad driver
Signed-off-by: Robby Cai <R63905@freescale.com>
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The origin ASRC driver did not support input and output wordwidth
config but an total wordwidth config instead. And the input wordwith
and output wordwidth are all fixed to 24 bit.
In this path, we do things below:
1 Update to use input wordwidth and output wordwidth config seperately
instead of an total wordwidth config.
2 Set corresponding DMA(input/output) buswidth according ASRC's input
and output wordwidth config.
3 Support 16/24 bit input wordwidth and 24 bit output wordwidth.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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this patch add more iomux strength to mx6dl's emmc.
otherwise, -110 error when access emmc will occures.
current test show this patch can improve on this issue.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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this patch add more iomux strength to mx6dl's emmc.
otherwise, -110 error when access emmc will occures.
current test show this patch can improve on this issue.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Previous voltage for 672M is 1.05V, normal test is OK,
but if CPU is busy in background and do the CPUFreq change
as well, always fail the stress test at 672M setpoint, after
increase it to 1.1V, stress test is OK.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Not update FB var if video mode same as last HDMI cable plugout.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Use allocated GPU resource to enable GPU.
Memroy address on imx6sl board starts from 0x80000000
and GC320 can access [baseAddress, baseAddress + 2G) only without MMU.
So to make GC320 work, baseAddres must be set to 0x80000000, and all
address sent to GC320 must be a offset to baseAddress. GC355 doesn't
need this baseAddress, that means it needs a real physcial adress,
rather than the offset to baseAddress.
Original code always change phsysical address to 'offset' before use it,
no matter it is used by GC355 or GC320, so only one of them can work.
Solution is to move address adjustion to arch specific part. So each
core can get what it wants.
Signed-off-by: Larry Li <b20787@freescale.com>
Acked-by: Lily Zhang
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Prepare resourec such as memory, interrupt, clock, regester address
needed by GPU.
Signed-off-by: Larry Li <b20787@freescale.com>
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Using small setting when switch from VGA to QVGA to take picture
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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set default volume for playback and record
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Remove in_interrupt() check in _ipu_get/_ipu_put, since clk_enable and
clk_disable should not happen in interrupt context.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Clean up the fb driver for maintainability:
1. Use completion instead of semaphore API interface.
2. Use IPU oneshot interrupt mode and remove ipu_disable_irq()
function call in interrupt handler.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Add IPU oneshot interrupt mode: IPU_IRQF_ONESHOT.
Interrupt is not reenabled after irq handler finished.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Add IPU oneshot interrupt mode: IPU_IRQF_ONESHOT.
Interrupt is not reenabled after irq handler finished.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Delete VGA_2_VGA workflow and using 15fps VGA setting when set
this mode.
Add XGA@15fps, XGA@30fps setting.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Add battery support for sabresd_6dq
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Use allocated GPU resource to enable GPU.
Memroy address on imx6sl board starts from 0x80000000
and GC320 can access [baseAddress, baseAddress + 2G) only without MMU.
So to make GC320 work, baseAddres must be set to 0x80000000, and all
address sent to GC320 must be a offset to baseAddress. GC355 doesn't
need this baseAddress, that means it needs a real physcial adress,
rather than the offset to baseAddress.
Original code always change phsysical address to 'offset' before use it,
no matter it is used by GC355 or GC320, so only one of them can work.
Solution is to move address adjustion to arch specific part. So each
core can get what it wants.
Signed-off-by: Larry Li <b20787@freescale.com>
Acked-by: Lily Zhang
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Prepare resourec such as memory, interrupt, clock, regester address
needed by GPU.
Signed-off-by: Larry Li <b20787@freescale.com>
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This reverts commit 019467e88eb148064726fe1b2941c71b5aea8601.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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