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2014-02-21ARM: dts: imx6q-phytec: Added SATA Supportimx6-dt-3.15-2Ashutosh singh
This patch adds support for SATA on Phytec phyFLEX-i.MX6 Quad module. Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-21ARM: dts: imx6q-phytec: Added GPMI-NAND SupportAshutosh singh
This patch adds support for GPMI-NAND on Phytec phyFLEX-i.MX6 Quad module. Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-21ARM: dts: imx6q-phytec: Added USB_HOST SupportAshutosh singh
This patch adds support for USB_HOST on Phytec phyFLEX-i.MX6 Quad module. Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-21ARM: dts: imx6q-phytec: Added USB_OTG SupportAshutosh singh
This patch adds support for USB_OTG on Phytec phyFLEX-i.MX6 Quad module. Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-20ARM: dts: imx6sl-evk: Keep VGEN1 regulator always enabledFabio Estevam
On imx6sl-evk board the VGEN1 regulator powers up the NVCC_1P2V domain of the imx6sl SoC, so we need to keep it always powered. According to imx6sl datasheet the GPIO block has three supplies: NVCC33_IO, NVCC18_IO and NVCC_1P2V and it states that: "All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not" This problem has been observed by the fact that a GPIO connected to an LED could not work when the PMIC driver was enabled. Keeping VGEN1 regulator always enabled fixes the problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-20ARM: dts: imx6qdl-sabreauto: Support debug LEDLiu Ying
The D9 LED controlled by gpio on the imx6qdl-sabreauto CPU board is a debug LED according to the board design. This patch adds the relevant device tree nodes to the imx6qdl-sabreauto device tree file to support this LED. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-13ARM: dts: imx6q: add 852MHz setpoint for CPU freqAnson Huang
According to datasheet, i.MX6Q has setpoint of 852MHz which is exclusive with 996MHz, the fuse map of speed_grading defines the max speed of ARM, here we add this 852MHz setpoint opp info, kernel will check the speed_grading fuse and remove all illegal setpoints. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-wandboard: use GPIO_6 for FEC interruptSascha Silbe
Apply the same work-around for i.MX 6D/Q erratum 006687 as used for Sabre Lite for the Wandboard Dual / Quad. Like on the Sabre Lite, GPIO6 is used as a power down output for camera expansion boards. However, these expansion boards do not work with mainline yet anyway. Tested on a Wandboard Quad. Before the patch: root@arm:~# ping -q -f -c 10000 192.168.2.1 PING 192.168.2.1 (192.168.2.1) 56(84) bytes of data. === 192.168.2.1 ping statistics === 10000 packets transmitted, 10000 received, 0% packet loss, time 97363ms rtt min/avg/max/mdev = 0.290/9.586/10.198/1.432 ms, pipe 2, ipg/ewma 9.737/9.672 ms After the patch: root@arm:~# ping -q -f -c 10000 192.168.2.1 PING 192.168.2.1 (192.168.2.1) 56(84) bytes of data. === 192.168.2.1 ping statistics === 10000 packets transmitted, 10000 received, 0% packet loss, time 4810ms rtt min/avg/max/mdev = 0.246/0.355/0.863/0.044 ms, ipg/ewma 0.481/0.319 ms Signed-off-by: Sascha Silbe <x-linux@infra-silbe.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6sl-evk: Add debug LED supportFabio Estevam
GPIO3_20 is connected to a debug LED. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-sabreauto: Add PFUZE100 supportFabio Estevam
mx6 sabreauto boards have Freescale PFUZE100 regulator, so add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6sl-evk: Add audio supportFabio Estevam
imx6sl-evk has a wm8962 codec. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6sl-evk: Add PFUZE100 supportFabio Estevam
imx6sl-evk board has Freescale PFUZE100 regulator, so add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-sabresd: correct gpio key's active stateAnson Huang
From schematic, the power, vol+/- key's active state is low, so we need to set the gpio flag to active low. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6q: Add support for Zealz GK802imx6-dt-3.15Sascha Hauer
Add support for the GK802 'QUAD CORE Mini PC', which seems to be loosely based on the Freescale i.MX6Q HDMI dongle reference design. It is supposedly identical to the Hiapad Hi802. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6: Add DFI FS700-M60 board supportSascha Hauer
The DFI FS700-M60 is a q7 board with i.MX6 quad, dual, duallite or solo SoC. This adds support for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6: use imx51-ssiMarkus Pargmann
imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online reconfiguration and needs this for correct interaction with SDMA. This patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl: Add mmc aliasesSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6q: Add spi4 aliasSascha Hauer
The quad version has a SPI controller more than the other versions. Add an alias for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-sabreauto: Add LVDS supportFabio Estevam
Add LVDS support for mx6 sabreauto boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6sl: add keypad support for i.mx6sl-evk board.Anson Huang
i.MX6SL EVK board has a 3*3 keypad matrix to support 8 keypads, enable them, the keymap is as below: SW6: MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ SW7: MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ SW8: MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ SW9: MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ SW10: MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ SW11: MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ SW12: MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ SW13: MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6sl: add ocram device supportAnson Huang
Add ocram device support on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl: enable dma for spiFrank Li
Enable dma support for espci controller Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-sabresd: Add PFUZE100 supportFabio Estevam
mx6 sabresd boards have Freescale PFUZE100 regulator, so add support for it. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6: add mxs phy controller idPeter Chen
We need to use controller id to access different register regions for mxs phy. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6: add anatop phandle for usbphyPeter Chen
Add anatop phandle for usbphy Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6q-arm2: use GPIO_6 for FEC interrupt.Troy Kisky
This works around a hardware bug. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-sabreauto: use GPIO_6 for FEC interrupt.Troy Kisky
This works around a hardware bug. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.Troy Kisky
This works around a hardware bug. From "Chip Errata for the i.MX 6Dual/6Quad" ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode. The ENET block generates many interrupts. Only one of these interrupt lines is connected to the General Power Controller (GPC) block, but a logical OR of all of the ENET interrupts is connected to the General Interrupt Controller (GIC). When the system enters Wait mode, a normal RX Done or TX Done does not wake up the system because the GPC cannot see this interrupt. This impacts performance of the ENET block because its interrupts are serviced only when the chip exits Wait mode due to an interrupt from some other wake-up source. Before this patch, ping times of a Sabre Lite board are quite random: ping 192.168.0.13 -i.5 -c5 PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data. 64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=15.7 ms 64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=14.4 ms 64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=13.4 ms 64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=12.4 ms 64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=11.4 ms === 192.168.0.13 ping statistics === 5 packets transmitted, 5 received, 0% packet loss, time 2004ms rtt min/avg/max/mdev = 11.431/13.501/15.746/1.508 ms ____________________________________________________ After this patch: ping 192.168.0.13 -i.5 -c5 PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data. 64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=0.120 ms 64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=0.175 ms 64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=0.169 ms 64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=0.168 ms 64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=0.172 ms === 192.168.0.13 ping statistics === 5 packets transmitted, 5 received, 0% packet loss, time 1999ms rtt min/avg/max/mdev = 0.120/0.160/0.175/0.026 ms ____________________________________________________ Also, apply same change to imx6qdl-nitrogen6x. This change may not be appropriate for all boards. Sabre Lite uses GPIO6 as a power down output for a ov5642 camera. As this expansion board does not yet work with mainline, this is not yet a conflict. It would be nice to have an alternative fix for boards where this is a problem. For example Sabre SD uses GPIO6 for I2C3_SDA. It also has long ping times currently. But cannot use this fix without giving up a touchscreen. Its ping times are also random. ping 192.168.0.19 -i.5 -c5 PING 192.168.0.19 (192.168.0.19) 56(84) bytes of data. 64 bytes from 192.168.0.19: icmp_req=1 ttl=64 time=16.0 ms 64 bytes from 192.168.0.19: icmp_req=2 ttl=64 time=15.4 ms 64 bytes from 192.168.0.19: icmp_req=3 ttl=64 time=14.4 ms 64 bytes from 192.168.0.19: icmp_req=4 ttl=64 time=13.4 ms 64 bytes from 192.168.0.19: icmp_req=5 ttl=64 time=12.4 ms === 192.168.0.19 ping statistics --- 5 packets transmitted, 5 received, 0% packet loss, time 2003ms rtt min/avg/max/mdev = 12.451/14.369/16.057/1.316 ms Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl: use interrupts-extended for fecTroy Kisky
We need to be able to override interrupts in board file to workaround a hardware bug for ethernet interrupts waking the processor by using interrupts-extended. So, use interrupts-extended here as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQTroy Kisky
From "Chip Errata for the i.MX 6Dual/6Quad" ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode. The ENET block generates many interrupts. Only one of these interrupt lines is connected to the General Power Controller (GPC) block, but a logical OR of all of the ENET interrupts is connected to the General Interrupt Controller (GIC). When the system enters Wait mode, a normal RX Done or TX Done does not wake up the system because the GPC cannot see this interrupt. This impacts performance of the ENET block because its interrupts are serviced only when the chip exits Wait mode due to an interrupt from some other wake-up source. Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to workaround this problem. The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ. The mux reg value is 0x11, so that the observable mux is routed to this pin and to the gpio controller(sion bit). These magic values come from Ranjani Vaidyanathan's patch: "ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active" Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6q-sabrelite: PHY reset is active-lowPhilipp Zabel
Note that the fec driver code currently hard-codes an active-low reset, regardless of the flags in the device tree. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6: Use 'vddarm' as the regulator nameFabio Estevam
Instead of calling the regulator for the ARM core as 'cpu', let's rename it as 'vddarm', so that we keep a better consistency with the other internal regulators: vdd1p1: 800 <--> 1375 mV at 1100 mV vdd3p0: 2800 <--> 3150 mV at 3000 mV vdd2p5: 2000 <--> 2750 mV at 2400 mV vddarm: 725 <--> 1450 mV at 1150 mV vddpu: 725 <--> 1450 mV at 1150 mV vddsoc: 725 <--> 1450 mV at 1200 mV Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabresd: Add power key supportAnson Huang
This patch adds support for imx6qdl-sabresd board's power key, the key is named "SW1" on board, press it can wake up system from suspend. Add a new pinctrl entry for gpio keys and move all gpio keys pin to this entry. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6sl: Adding cpu frequency and VDDSOC/PU table.John Tobias
Device tree for iMX6SL doesn't have an existing cpu frequency table as well as the VDDSOC/PU. Signed-off-by: John Tobias <john.tobias.ph@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl: add necessary thermal clkAnson Huang
Thermal sensor needs pll3_usb_otg when measuring temperature, so we need to pass clk info to thermal driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6dl: enable cpufreq supportAnson Huang
This patch adds cpufreq dts for i.mx6dl to support cpufreq driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6q: add vddsoc/pu setpoint infoAnson Huang
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq is changed, each setpoint has different voltage, so we need to pass vddarm, vddsoc/pu's freq-voltage info from dts together. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6q: update setting of VDDARM_CAP voltageAnson Huang
According to datasheet, VDD_CACHE_CAP must not exceed VDDARM_CAP by more than 200mV, as all of i.MX6Q boards' VDD_CACHE_CAP currently are connected to VDDSOC_CAP, so we need to follow this rule by increasing VDDARM_CAP's voltage. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: add gpio-keysTroy Kisky
Add power, menu, home, back, volume up, and volume down buttons. Also, apply same changes to imx6qdl-nitrogen6x. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx: add nitrogen6x boardTroy Kisky
Add file imx6q-nitrogen6x.dts, imx6dl-nitrogen6x.dts, imx6qdl-nitrogen6x.dtsi And add board to makefile. Eric Nelson created a web page to show the differences between Nitrogen6x and Sabre Lite boards. http://boundarydevices.com/differences-sabre-lite-nitrogen6x Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: Add over-current pin to usbotgTroy Kisky
KEY_COL4 is over-current for usbotg on Sabre Lite. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: fix ENET groupTroy Kisky
GPIO16 is used for I2C3, not ENET_REF_CLK. Also, remove pull-ups from tx pins, and ENET_MDIO which has an external pull-up. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: add skews for Micrel phyTroy Kisky
Set the data delays to min, and clock delays to max because the traces are equal length on pcb. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: add pwms for backlightsTroy Kisky
add pwm1 for lcd backlight add pwm4 for lvds backlight add pwm3 for ov5640 mipi clock Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: explicitly set pad for SGTL5000 sys_mclkTroy Kisky
Explicitly sets the pad GPIO_0 (sys_mclk) to 0x030b0. Before this patch, it has the value 0x130b0 if using mainline u-boot. So this patch also removes hysteresis. The 100k pulldown remains so that a disabled clock will be low. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: move phy reset to pinctrl_enetTroy Kisky
This patch moves pin EIM_D23 (phy reset) from pinctrl_hog to pinctrl_enet. It also explicitly sets the pad to 0x000b0. Before this patch, it has the value 0x1b0b0 if using mainline u-boot. So this patch also removes hysteresis and a 100K pullup since the pad is always an output. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: move usbotg power enable to pinctrl_usbotgTroy Kisky
This patch moves pin EIM_D22(power enable) from pinctrl_hog to pinctrl_usbotg. It also explicitly sets the pad to 0x000b0, which is also the value that it has before this patch if using mainline u-boot. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: move spi-nor CS to pinctrl_ecspi1Troy Kisky
This patch moves pin EIM_D19 (CS) from pinctrl_hog to pinctrl_ecspi1. It also explicitly sets the pad to 0x000b1. Before this patch, it has the value 0x100b1 if using mainline u-boot. So this patch also removes hysteresis since the pad is always an output. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: move USDHC3 CD/WP to pinctrl_usdhc3Troy Kisky
This patch moves pin SD3_DAT5/4 (CD/WP) from pinctrl_hog to pinctrl_usdhc3. It also explicitly sets the pad SD3_DAT5 to 0x1b0b0, which is also the value that it has before this patch if using mainline u-boot. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6qdl-sabrelite: move USDHC4 CD to pinctrl_usdhc4Troy Kisky
This patch moves pin NANDF_D6 (CD) from pinctrl_hog to pinctrl_usdhc4. It also explicitly sets the pad to 0x1b0b0, which is also the value that it has before this patch if using mainline u-boot. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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