Age | Commit message (Collapse) | Author |
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Because the 1588 stack and STP stack need to know the phy status,
added phy support for switch port1 and port2.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
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In Switch mode, The ENET-MAC interrupts are enabled and can
be used to monitor the line activity.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
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When enable fec0 and fec1 1588 timer in the same time,
enalbe fec1 1588 timer to FRC_SLAVE mode in i.MX28.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
(cherry picked from commit e90197be678342bf9a09c4f64f5fe25a84cf75c7)
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The problem is caused by:
ubi double free ubiblk_dev structrue, cause the list and memory mess up.
This patch changes field `m` in the ubiblk_dev{} from the mtd_blktrans_dev{}
to pointer.
Also add a mutex for protecting the global ubiblk_devices.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Reslove the pcm read error when opening arecord and aplay at the
same time.
Signed-off-by: Lionel Xu <r63889@freescale.com>
(cherry picked from commit c8d1b31e0fde30874d352c216a44ec1ad05424e1)
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Should not read usb registers when usb is in low power mode,
or it will cause usb system hang or getting the wrong registers value
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Set USB VBUS on when host only controller probed. Only DR OTG host
doesn't set vbus on when platform driver probed.
Signed-off-by: Zhang Yan <b34916@freescale.com>
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- Changed default update scheme to SNAPSHOT
- Added panning offset info for each update
- Added merge check against panning offset
- Fixed conditions for merging
Signed-off-by: Danny Nold <dannynold@freescale.com>
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If it return failure in erasing a block, mark the block bad
in the bbt table.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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[1] Add the initializtion for TOGGLE nand.
[2] chang the is_onfi_nand() to is_ddr_nand().
[3] add NAND_LOCK in the send_command()
Signed-off-by: Huang Shijie <b32955@freescale.com>
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change the function name is_onfi_nand() to is_ddr_nand().
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Add the TOGGLE nand device infomation to the table.
And change the `is_onfi_nand` to `is_ddr_ok`.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The ONFI NAND and TOGGLE NAND both support the DDR.
So merge the same attribution to a new field `is_ddr_ok`.
Also add a inline function to judge the DDR nand.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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add the BCH clock setting, and keep them work in the same
frequncy.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Change the DDR freq to 133MHz from 266Mhz (or 200MHz) when the AHB
is dropped to 66.5MHz. The DDR freq change will be initiated only
when the EPDC clock is not active. So there will be brief periods of time
when DDR is at 266Mhz even when AHB is at 66.5Mhz and DDR will be at 133Mhz
even when AHB is at 133Mhz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The root cause is list_del() are called twice on same entry in pxp irq handler.
Remove latter one fixes this issue.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Register SPI device first so that it will be the last device
to be suspended and first device to be resumed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fixed the SPI driver suspend/resume code. The SPI driver was missing
releasing the spin lock in certain conditions.In the resume code,
the master bit needs to be set while re-enabling the spi.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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By default, dynamic ZQ calibration runs by interval of 10 seconds.
This interval can be changed via Sys, for example 5 seconds,
echo 5 > /sys/devices/platform/mxc_zq_calib/interval
Signed-off-by: Robby Cai <R63905@freescale.com>
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need to make sure last ZQ calib run completed and no more ZQ calib to be run
during suspend, and resume ZQ calib until the system resumes.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Set carrier flag to off when suspend,
to avoid kernel warning about sending timeout.
Reported-by: Peter Chen <peter.chen@freescale.com>
Tested-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
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Fec phy state changing occurs in delay works, which in normal task context.
And package sending mostly happens in softirq context, only happens in ksoftirq
while network traffic is heavy and some _many retries_ situation.
Linux network qdisc code keep raising NET_TX_SOFTIRQ softirq if package
not send out when netdev queue set to start. And the subsequenece process
will loop in softirq context for 10ms. Since Imx28 HZ set to 100Hz, the next
timer interrupt will trigger softirq again. this loop prevent network link
changing to up status. And cause a chicken-egg problem.
To break this loop, we need to set netdev transmit queue stop when link is down,
and start it when link becomes up.
commit 757bfe446bab7661d12a8772ca10b7a490c8aa47 try to resolve this problem,
but hand-merge mistake introduce a power resume bug.
Reported-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
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Use pgprot_writethru() instead of pgprot_noncached()
Signed-off-by: Robby Cai <R63905@freescale.com>
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Added pgprot_writethru(), to set the buffer's cache property as
writethrough.
Signed-off-by: Robby Cai <R63905@freescale.com>
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For boards that use the SMSC 911x ethernet driver, the MAC ID for
the ethernet controller was randomly being generated. It should get
the MAC ID from the IIM fuses that are blown to show the correct MAC ID.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
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Setting DSE to high and ODE bits in I2C3_SDA IOMUX pad causes WVGA to fail.
Fix is to use the default values for pad control.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Problem
========
In suspend/resume cycle, info->var.xoffset and info->var.yoffset
will be reset to 0 (in function fbcon_switch). After reume, if the
xoffset/yoffset of update region happens to be 0/0, this region will
not be displayed.
Resolution
==========
Should not compare new offset with previous offset, but compare
new panning/offset state with previous state in pan_display function
to determine whether need to update fb_offset.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Fix keypad can't wake up system
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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DHCP fail when enable NO_HZ and preempt at mx28evk
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Changed DLL delay from 0x14 to 0x0b
Swapped pu and (pu+1), pd and (pd+1) assignment in CFG1 and CFG2.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Also fix the suspend/resume issue when CPU running @261818000Hz
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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- Created a worker thread to centralize all update requests (new and collisions)
- Added routine to merge compatible updates
- Separated PXP processing from update ioctl and ISR flows into workqueue flow
- Added IOCTL to turn control the update scheme. Supported schemes
are snapshot mode (the old update scheme), queued mode, and queued mode
with combining.
- Added collision-handling refinement based on update submission order
- Added support for 8bpp setting from kernel command line option
Signed-off-by: Danny Nold <dannynold@freescale.com>
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LPDDR2 ZQ calibration is different from mDDR/DDR2 in this version.
The patch added a workaround to get appropriate pu/pd value for h/w.
Signed-off-by: Robby Cai <R63905@freescale.com>
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1. Using the UDP dest port to identifying an event message.
2. Add related information checking for getting rx/tx timestamp.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
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Here 'kick' means start the timer or postpone the timer.
By only kicking the timer in irq handler only when no task pending
in the queue, rather than each time we submit a new task, it should
perform better.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Usage (timeout in millisecond, default is 600):
echo 2000 > /sys/devices/platform/mxc-pxp/clk_off_timeout
Signed-off-by: Robby Cai <R63905@freescale.com>
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This patch remaps user defined size of IIM registers from
IIM base address.
Signed-off-by: Liu Ying <b17645@freescale.com>
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LTC3589: Changed R2 value for reulator SW2 and LDO2.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Changed VDDGP voltage to 1.0V as CPU freq is 160MHz.
2. Changed suspend values of VDDGP and VCC back to 0.95V
as HW issue has been resolved.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Register the PWRON3 event when probe the power key device.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Enable the PWRON3 event in mc13892.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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For timer based power autogating, we have to move clk_enable/disable out of
timer handler, because they become may sleep.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
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At usb otg mode, the fsl_udc_resume will be called at otg_set_host and
otg_set_peripheral. So we needs to add mutex_lock for fsl_udc_resume to
protect being called at the same time.
Besides, the fsl_udc_resume should not be called continuous twice, or the
udc->suspended will be wrong
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Fix MX53 boot issue caused by the changes made to bus_freq driver.
Ensure that all MX5x platforms can enter/exit various low power modes.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Enable NO_HZ and PREEMPT as default config for mx28
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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mdelay(10) actually delay 50ms before fix timer issue.
After fix timer issue. It should set to 50ms
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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It should be match = current - delta.
Original code is match = last_match -delta.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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In the probe function of LDB framebuffer driver, we will
try to match the LVDS video modes defined in the driver.
For LDB separate mode, we need to find two video modes matched,
whereas, for other LDB modes, we need to find only one video
mode matched.
Signed-off-by: Liu Ying <b17645@freescale.com>
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Add the capability to change the bus clocks at half the max frequency based on
which modules are active. AHB_CLK, AXI_A and AXI_B clock are at half the max.
DDR is left at 266MHz(LPDDR2)/200MHz (mDDR).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Some GPC bits were getting set twice, fixed the issue. Protected the section where CPU
frequency is changed. For MX50, increase the cpu frequency along with increasing
the bus frequency.
Fixed the test conditions under which bus frequency should be set to low, medium or high
setpoint.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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