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2012-04-30ENGR00181201 mx6x HDMI audio add IEC head optimization with C coderel_imx_3.0.15_12.04.013.0-imx6-201204281855Sandor Yu
mx6x HDMI audio add IEC head optimization with C code Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-04-30ENGR00180103-3 V4L2: HDMI display error when dual display with LVDS panelWayne Zou
Restore fb_var_screeninfo when finishing video playback Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-30ENGR00180103-2 V4L2: remove GFP_DMA flag when alloc dma memoryWayne Zou
Remove GFP_DMA flag when alloc dma memory. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-30ENGR00180103-1 V4L2: use copy_from/to_user() for user space pointerWayne Zou
V4L2: use copy_from/to_user() for user space pointer Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-28ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400MWayne Zou
On mx6dl, set ipu2_clk's parent from pll2_pfd_400M. On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-28ENGR00181188 Added miss file hdmi_cpm.S for patch ENGR00181130Sandor Yu
Added miss file hdmi_cpm.S for patch ENGR00181130 Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-04-28ENGR00181130 Optimizate HDMI audio mmap to fix HDMI audio alsa underrunSandor Yu
HDMI audio DMA FIFO size is setting to 126, and use INCR4 mode to fix FIFO overflow issue. Added Neon code for PCM data IEC head and data copy. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-04-28ENGR00181107 add dma_alloc_writethrough functionSandor Yu
add dma_alloc_writethrough function to dma_mapping.c Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-04-27ENGR00180424: Changed iomux ID pinGuillermo
Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID Signed-off-by: Guillermo <b12356@freescale.com>
2012-04-27ENGR00180076: prompt "mmc0: error -110 during resume" with atheros wifi cardjustin.jiang
* only happend on sabre-auto board,atheros sdio wifi card can't be used after suspend/resume * Fix by keeping sdio power at suspend. Signed-off-by: justin.jiang <b31011@freescale.com>
2012-04-27ENGR00175084 IPU-FB: change dma memory alloc gfp flags to GFP_KERNELWayne Zou
We only needs the dma buffer, don't care if it is from DMA Zone on i.mx SOC. To fix the following bug: mxc_ipudev_test: page allocation failure: order:13, mode:0x1 [<80042e08>] (unwind_backtrace+0x0/0xfc) from [<800b4dd8>] (warn_alloc_failed+0x9c/0x118) [<800b4dd8>] (warn_alloc_failed+0x9c/0x118) from [<800b5ac4>] (__alloc_pages_nodemask+0x494/0x6ec) [<800b5ac4>] (__alloc_pages_nodemask+0x494/0x6ec) from [<80046154>] (__dma_alloc+0xd4/0x2fc) [<80046154>] (__dma_alloc+0xd4/0x2fc) from [<800463a0>] (dma_alloc_writecombine+0x24/0x2c) [<800463a0>] (dma_alloc_writecombine+0x24/0x2c) from [<8024be34>] (mxcfb_set_par+0x3e4/0x4c0) [<8024be34>] (mxcfb_set_par+0x3e4/0x4c0) from [<80235f08>] (fb_set_var+0x168/0x2a4) [<80235f08>] (fb_set_var+0x168/0x2a4) from [<802363f8>](do_fb_ioctl+0x3b4/0x5f0) [<802363f8>] (do_fb_ioctl+0x3b4/0x5f0) from[<800f58d0>](do_vfs_ioctl+0x80/0x5e4) [<800f58d0>] (do_vfs_ioctl+0x80/0x5e4) from [<800f5e6c>] (sys_ioctl+0x38/0x60) [<800f5e6c>] (sys_ioctl+0x38/0x60) from [<8003d500>] (ret_fast_syscall+0x0/0x30) mxc_sdc_fb mxc_sdc_fb.0: Unable to allocate framebuffer memory detected fb_set_par error, error code: -12 Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-26ENGR00180236-2: spdif clk usecount is 1 when not in useAdrian Alonso
* Move spdif_core_clk enable from spdif_probe to spdif_startup function in order to avoid initializing the core clock when module is not in use. * At spdif_shutdown disable spdif core_clk. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-04-26ENGR00180236: mxc_spdif add spdif_clk error checkAdrian Alonso
* Add get_clk clock error check abort driver probe if wrong clock. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-04-26ENGR00180882- MX6DL Add bus frequency scaling support.Ranjani Vaidyanathan
Added support for changing DDR frequency on MX6DL. During system IDLE, DDR freq can drop down to 24MHz if none of the devices that need high AHB frequency are active. Changed the DDR code to handle both MX6Q and MX6DL DDR and IOMUX settings. Fixed bug associated incorrect IRAM memory allocation used to store DDR and IOMUX data. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-26ENGR00180185: MX6-Add support for low power audio playbackRanjani Vaidyanathan
The DDR frequency needs to be at 50MHz for low power audio playback. So added a new low power mode for audio. Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-24ENGR00180297 WM8962: stereo record on AMICGary Zhang
Implement stereo recording feature on analog mic Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-20ENGR00180412 MX6 SATA: Enable PHY in the SATA initilizationRichard Zhu
iENGR00179574: MX6- Add bus frequency scaling support disable SATA PHY defaultly Enable PHY in the SATA initilization, make sure the SATA work well. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-20ENGR00180229-2 VDOA: disable vdoa clock when no usedWayne Zou
Disable vdoa clock when no used Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-20ENGR00180229-1 V4L2: Fix a bug when doing tiled format deinterlacedWayne Zou
Initialize paddr_n when doing vdoa+vdi deinterlaced, when doing tiled format deinterlaced. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-20ENGR00172292 usb otg: enable dtds postpone free on mx6Xinyu Chen
We found this bug occurs again on mx6 when running CTS with ADB over USB. The system will hang without any log, and screen a little mess. It's proved to be a known USB IP issue: USB controller may access a wrong address for the dTD and then hang. Re enable this workaround to avoid any system unstability. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-04-19ENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1Richard Zhu
* Adjust the parameters, enlarge the eye diagram. * Force to the PCIE GEN1 speed. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-19ENGR00180096 change NAND clock source to pll2_pfd_400MAllen Xu
change clock source explicitly by calling set_parent() function Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-17ENGR00179800 V4L2: Add VDOA tiled format post-processing supportWayne Zou
Add VDOA tiled format post-processing support Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-17ENGR00179725 WM8962: remove 64KHz sample rate supportGary Zhang
because wm8962 codec does not support 64KHz sample rate, no longer declare to support 64KHz: Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-17ENGR00179804 change NAND clock source from pll2_pfd_352M to pll2_pfd_400MAllen Xu
Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to pll2_pfd_400M. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-17ENGR00179685 MX6 clock:Cleanup LDB DI parent clockLiu Ying
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1. However, MX6DL uses mmdc_ch1 as LDB DI parent clock. This patch corrects the LDB DI parent clock setting. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-04-16ENGR00179747: MX6DL-Fix boot failureRanjani Vaidyanathan
Fix the boot failure caused by: 8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab MX6- Add bus frequency scaling support There is no SATA on MX6DL. Accessing SATA PHYs early in the boot process causes the system to crash. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-16ENGR00179696 MX6Q/UART : fix the wrong DMA tranfer direction.Huang Shijie
The current SDMA use the new DMA tranfer direction. But the UART still uses the old. This cause the RX failed. So use the new DMA transfer direction for UART. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-04-16ENGR00179679 Fix usb gadget suspend issue connected to usb chargerTony LIU
- the root cause of this issue is during resume process, USB clock is not turned on for this USB charger case so that the second suspend is processed without USB clock, it cause system hang - in udc resume process, at this situation, we should exit low power mode to enable the b session valid intrrupt to close the usb clock when detach from usb charger Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-04-16IMX/DMA : set the DMA direction in the sdma_control()Huang Shijie
Set the right DMA direction in the sdma_control(), else we will get the wrong log when enable the DYNAMIC_DEBUG. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-04-16ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1Liu Ying
This patch corrects LDB DI clock's parent clock to be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0 according to ticket TKT071080(0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1). Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-04-13ENGR00179575 only set color depth if TV supports deep colorAlan Tull
If TV's EDID indicates that deep color is not supported, then write color depth field of HDMI_VP_PR_CD register to zero. Signed-off-by: Alan Tull <r80115@freescale.com>
2012-04-13ENGR00179601 Synopsys approved hdmi fifo workaround - rev 3Alan Tull
This patch includes some of the clk enable/disable changes from rev2 Check the version of the HDMI IP to determine whether the fifo threshold needs to be high. The i.Mx6dl version of the HDMI doesn't need the workaround. All other parts of the workaround are used for both parts for code simplicity. ---------------------------------------------------------- For i.Mxq, set the Threshold of audio fifo as: FIFO depth - 2 (fixed and independent of the number of channels actually used). Use unspecified length ahb bursts (using fixed INCRx will make the audio dma fail). Additionally and in order to get it working on all conditions it will be necessary to run the following sw steps at startup of video and audio (or when video changes or audio changes): 1-Configure AUD_N1 and AUD_CTS1 registers with final value and let the AUD_N2, AUD_N3, AUD_CTS2 and AUD_CTS3 to 0s. 2-Configure start and end addresses of audio DMA registers. 3-Start DMA operation 4-Configure the AUD_CTS2 and AUD_CTS3 with the final value. 5-Configure the AUD_N2 and AUD_N3 with final value. Signed-off-by: Alan Tull <r80115@freescale.com>
2012-04-13ENGR00179574: MX6- Add bus frequency scaling supportRanjani Vaidyanathan
Add support for scaling the bus frequency (both DDR and ahb_clk). The DDR and AHB_CLK are dropped to 24MHz when all devices that need high AHB frequency are disabled and the CORE frequency is at the lowest setpoint. The DDR is dropped to 400MHz for the video playback usecase. In this mode the GPU, FEC, SATA etc are disabled. To scale the bus frequency, its necessary that all cores except the core that is executing the DDR frequency change are in WFE. This is achieved by generating interrupts on un-used interrupts (Int no 139, 144, 145 and 146). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-13ENGR00179582 MX6: Bypass PLL1 during WAITRanjani Vaidyanathan
When system is going to enter WAIT mode, set PLL1 to 24MHz so that ARM is running at 24MHz. This is a SW workaround for the WAIT mode issue. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-13ENGR00179513-3 V4L2: Add VDOA tiled format supportWayne Zou
Support for VDOA tiled format IPU_PIX_FMT_TILED_NV12 up to 1080p progressive streams, and IPU_PIX_FMT_TILED_NV12F tiled format up to xga interlaced streams currently. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-13ENGR00179513-2 IPU: Add TILED_NV12_FRAME_SIZE macro for consistencyWayne Zou
VPU needs 4K align buffer address for tiled format data output. Use this macro for IPU/V4L2/Apps to calculate the frame/field size. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-13ENGR00179513-1 VDOA: update software state before start vdoaWayne Zou
Fix a bug when vdoa interrupt happens before software state updated. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-13ENGR00179631 MX6 SabreSD: Add MIPI DSI Display supportWayne Zou
Add MIPI DSI Display support on mx6 SabreSD board. MIPI DSI needs pll3_pfd_540M clock source for 540MHz. if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz. So add command line option disable_ldb when using MIPI DSI display. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-13ENGR00179628-2 MX6: add ssi info in sdmaGary Zhang
add ssi dual-fifo info in sdma structure Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-13ENGR00179628-1 SSI: enable dual-fifo feature as defaultGary Zhang
enable SSI dual-fifo feature as default setting Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-13ENGR00179621 MX6 PCIE: bring up PCIE on i.MX6 SD boardRichard Zhu
* Bring up the PCIE on i.MX6 SD board * Add the PCIE PHY access routines * Wrapper the board related codes by register one platform driver and data Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-13ENGR00179498-2 SDMA: fix p2p sdma script errorChen Liangjun
Update p2p script firmware address in plat-imx-dma.c for MX6Q. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-04-13ENGR00179498-1 SDMA: fix p2p sdma script errorChen Liangjun
The p2p script in SDMA binary file is invalid. The ESAI call ASRC can't work properly with this firmware. Update the firmware and script address. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-04-13ENGR00179485 fix CTS hang up issueRichard Liu
fix random hang up issue especially run CTS provided by Viv Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Lily Zhang
2012-04-12ENGR00179510 ipu capture: fix system hang when running captureYuxi Sun
Add _ipu_get() and _ipu_put() when calling ipu_csi_get_sensor_protocol function. Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-04-12ENGR00179284-4 support ONFI NAND device on mx6q_arm2_pop boardAllen Xu
if the NAND chip supports ONFI feature and the board supports ONFI DDR transfer mode, users could enable ONFI DDR transfer by add command line parameter "onfi_support" Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-12ENGR00179284-3 support ONFI NAND device on mx6q_arm2_pop boardAllen Xu
Add bch and gpmi register define for ONFI ddr feature Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-12ENGR00179284-2 support ONFI NAND device on mx6q_arm2_pop boardAllen Xu
enable ONFI NAND feature by command line parameter "onfi_support" Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-12ENGR00179284-1 support ONFI NAND device on mx6q_arm2_pop boardAllen Xu
Add a platform data to indicate whether the board support ONFI nand Signed-off-by: Allen Xu <allen.xu@freescale.com>
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