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Wrongly release mutex lock during otg_statemachine may result in re-enter
otg_statemachine, which is not allowed, we should do next state transtition
after previous one completed.
Signed-off-by: Li Jun <jun.li@freescale.com>
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After device power up, insert usb OTG ID cable, otg fsm from undefined state
to a_idle, the BSV cannot be disabled, this will result BSV irq generated but
which is actually only for B device.
Signed-off-by: Li Jun <jun.li@freescale.com>
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Current otg fsm timers are using controller 1ms irq and count it, this patch
is to replace it with hrtimer solution, use one hrtimer for all otg timers.
Signed-off-by: Li Jun <jun.li@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit 0433eb3101c967783d1231c0431587a49298bc1c)
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B_DATA_PLS(data-line pulse time) and B_SSEND_SRP(session end to SRP init) are
also from OTG&EH 2.0 Specification and they are not chipidea specific.
Signed-off-by: Li Jun <jun.li@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit f64f023d3c4899c029a167345350651872271a2c)
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This patch sets LDB_DI[0/1]_SEL clock parent to be PLL2_PFD0_352M
clock for i.MX6QP so that we may get correct 65MHz pixel clock rate
for Hannstar LVDS panel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c163cfce94d6a07dea18703407a4068648424a46)
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Set the IPU channel priority to high for the second CSI
capture channel.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
(cherry picked from commit 51d628d057ddfd96321608ca3c639c46e43b996a)
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The mxc vout driver is likely to set framebuffer to a RGB pixel format
via fbvar->nonstd field when PRE is enabled. This would cause the PRE
driver report the prefetch input pixel format is invalid. This patch
specifies some prefetch input RGB pixel formats in the PRE driver to
address this issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit d6fc5d853d05765638e3910be911d18c7c14eabe)
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We need to use IPUv3 platform information to set IDMAC_CONF used bufs stuffs for
different IPUv3 variants.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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We need to use IPUv3 platform information to set IDMAC0/23/27/28 AXI ID for
different IPUv3 variants.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The system sleep power management hooks ipu_suspend/ipu_resume are actually
doing nothing, so let's remove them.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Let's replace the ulgy global variable g_ipu_hw_rev with the ipu->devtype.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The driver doesn't have functional support for IPU_DISP0/1_BASE,
IPU_ISP_REG_BASE, IPU_DP_REG_BASE, IPU_IRT_REG_BASE, IPU_LUT_REG_BASE,
and IPU_ISP_TBPR_REG_BASE. Let's remove them to save some lines.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The commit c01cdab21b1e3cc045f40f29ca0d9292d238ffda introduced a different
configuration for rotation case in PxP driver, that is, it requires the rotated
width and height value. Thus EPDC driver, the user of PxP driver should also
adjust accordingly.
Signed-off-by: Robby Cai <r63905@freescale.com>
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Add uart5 DTE pin setting.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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The issue is introduced by the commit:
2b640b0f16e4b6b549ae466011ab9b96778162c9
Correct uart6 assigned clock parent, otherwise the default parent clock
is 24Mhz.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Remove imx7d enet 1588 clock parent init from imx7d clock file since
1588 clock parent and rate is set in dts file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Set enet 1588 clock parents and rate from dts.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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The PRE interrupt handler is protected by the spin lock pre->lock.
The spin lock is also locked/unlocked in non-interrupt contexts.
So, we need to use spin_lock_irqsave() and spin_unlock_irqrestore()
primitives in the non-interrupt contexts to avoid deadlock in the
interrupt handler.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The i.MX6QP IOMUX_GPR5 PRE_PRG_SEL0/1 fields control the PRE/PRG muxing.
The muxing could be described by the following table.
------------------------------------------------------------------
|\ | PRG0/IPU0 | PRG1/IPU1 |
| mux |-----------------------------------------------------------|
| \ |ch0/ch23 |ch1/ch27 |ch2/ch28 |ch0/ch23 |ch1/ch27 |ch2/ch28 |
|------------------------------------------------------------------|
| PRE0 | fixed | n/a | n/a | n/a | n/a | n/a |
|------------------------------------------------------------------|
| PRE1 | n/a | A(2b'00)| A(2b'01)| n/a | A(2b'10)| A(2b'11)|
|------------------------------------------------------------------|
| PRE2 | n/a | B(2b'00)| B(2b'01)| n/a | B(2b'10)| B(2b'11)|
|------------------------------------------------------------------|
| PRE3 | n/a | n/a | n/a | fixed | n/a | n/a |
------------------------------------------------------------------
(Note - A: GPR5 bit12-13, B: GPR5 bit14-15)
We should bind PRG[x] channel[y] with IPU[x] channel[y+26] statically
instead of dynamically, where x=0or1, y=1or2. Also, the values for A/B
cannot be the same due to a SoC design requirement(even if one of the
PRE1/PRE2 is disabled, the two values cannot be the same). This patch
fixes the PRE/PRG muxing logic.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Using new wake up mode in gpcv2 bring in system issue, USB and AUDIO
meet stress test issue, design team is still checking the root
cause, let's use previous work around of GPC wake up to make sure
system is stable currently.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add 96k and 192k sample rate support for hdmi audio.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Add 96k and 192k sample rate support.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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- add the perst for imx pcie because that this signal
is mandatory required to be asserted/de-asserted
during suspend/resume.
Otherwise, pcie ep maybe failed to resume back.
- for imx7 pcie
- use the external osc, otherwise the internal pll
- adjust the ltssm de-assert
- change the init of pcie to late_initcall, because
the expansion spi gpio is used as pcie_rst_b and
pcie_dis_b on imx7d/imx6qp boards, and pcie driver has
to be loaded after spi/i2c driver is probed.
- cansleep set value function should be used to
manipulate the expansion gpios.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Since the spi expansion gpio maybe manipulated,
during spi driver is suspend.
Such as the PCIE_RST_B on imx7d sdb board.
Add runtime pm into spi expansion gpio driver
Signed-off-by: Gao Pan <b54642@freescale.com>
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- HW rework, enable the perst for imx7d 12x12 arm2 board,
because that this signal is mandatory required
to be asserted/de-asserted during suspend/resume.
Otherwise, pcie ep maybe failed to resume back.
- unfortunately, cspi3 has pin conflicts with pcie_rst_b,
create one imx7d-xxx-pcie.dts, disable cspi3 and enable
pcie in it.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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* Fix pinctrl-imx suport for iomuxc-lpsr daisy chain configuration
* Add SHARE_INPUT_SELECT_REG to indicate that iomuxc-lpsr shares
input select config register from iomuxc controller to properly
set up iomuxc-lpsr pads than need daisy chain setup.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
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* imx7d-pinfunc fix uart input sel option value to correctly set
daisy chain to support UART ALT mode.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
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For those SoCs which have no PRE engines embedded, users may try to call
the ioctrl MXCFB_SET_PREFETCH to enable the PRE. The ioctrl sets the flag
mxcfbi->prefetch to be true to go for PRE allocation. It is doomed to fail
and the users will have no chance to set the flag back to false. As a result,
the framebuffer will not be responsive to the users' set_par ioctls. Let's
set the current prefetch flag back to the prefetch flag in that case to avoid
the situation.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The usual sequence[1] to enable/disable a display channel is
1) ipu_init_channel()
2) ipu_init_channel_buffer()
3) ipu_enable_channel() -> enable pixel clock
4) ipu_disable_channel()
5) ipu_uninit_channel() -> disable pixel clock
We currently enable pixel clock in ipu_enable_channel() while disable it
in ipu_uninit_channel() to meet some critical pipeline on/off sequence.
This will make the bail-out path for [1] fail to balance pixel clock
enable/disable count if there is no flag to reflect the clock's status.
For example, if we bail out after 1) by calling 5), we has the risk to
additionally disable pixel clock for one time. This patch adds the
pixel_clk_en[2] flags to help balance the count.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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We should uninitialize ipu channel only for !on_the_fly cases in the bail-out
path of _setup_disp_channel2() in ->fb_set_par(), because we should be able to
keep the display path un-touched or un-impacted in the on_the_fly cases even if
we return failure from _setup_display_channel2().
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The output image area bounds check should be moved to
where the 'l', 't', 'w' and 'h' are finalized to avoid
the drect area beyond the maximum fb display area which
may cause overflow issue when calculating the PXP PS LRC
or ULC.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The FEC modules used on i.MX28 and newer have a register to tune the MDIO
output hold time that should be at least 10 ns. Up to now this value was not
explicitly set and so resulted in less hold time if the fec clock was
faster than 100 MHz.
This was noticed on an i.MX28 machine that uses an input clock of ~150
Mhz which resulted in unreliable communication with a Marvell switch.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
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When the driver is removed (e.g. using unbind through sysfs), the
clocks get disabled twice, once on fec_enet_close and once on
fec_drv_remove. Since the clocks are enabled only once, this leads
to a warning:
WARNING: CPU: 0 PID: 402 at drivers/clk/clk.c:992 clk_core_disable+0x64/0x68()
Remove the call to fec_enet_clk_enable in fec_drv_remove to balance
the clock enable/disable calls again. This has been introduce by
e8fcfcd5684a ("net: fec: optimize the clock management to save power").
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch initialises the fep->netdev pointer. This pointer was not
initialised at all, but is used in fec_enet_timeout_work and in some
error paths.
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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In megafix mode, enable uart3, uart5, uart6, enet1, enet2 wake up irq in GPC.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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* Add new dts file to support mx7d_12x12_ddr3_arm2 target boaard
* Initial support enable base hardware support
* V2: update ecspi4 and i2c pad settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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The output channel support two planes YUV formats.
So the output UV buffer should also be configured
in this case.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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Add 'NV21' format support in pxp-v3 driver to fix
some display issue in some test cases.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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The output channel support two planes YUV formats.
So the output UV buffer should also be configured
in this case.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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Add 'NV21' format support in pxp-v2 driver to fix
some display issue in some test cases.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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Currently we find that if a usdhc is choosed to boot system, then ROM
code will set the burst length enable bit of this usdhc as 0.
This will make performance drop a lot if this usdhc's burst length is
16. So this patch set back the burst_length_enable bit as 1, which is
the default value, and means burst length is enabled for INCR.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
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Looks the below patch was applied wrongly indeed by 'git am', although there
is no any error or warning reported when do 'git am'. Not sure the root cause,
just take it back.
commit e66a17dc5c68e37ea110d171ba7ed94c02f9d7ce
Author: Robin Gong <b38343@freescale.com>
Date: Thu Apr 16 10:54:18 2015 +0800
spi: check tx_buf and rx_buf in spi_unmap_msg
Signed-off-by: Robin Gong <b38343@freescale.com>
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i.MX7D pin header file some uart pins setting are not correct, correct them.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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megafix power off
In megafix power off, the driver save necessary registers in suspend, and resotre the
registers in resume, but access registers need ipg clock gate on, so the patch make sure
ipg clock gate is on before save/restore the uart registers.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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As we have to flush L2 cache before entering DSM
on i.MX7D whose L2 controller is integrated into
ARM core, so we can disable L2 PGE along with SCU
to save power, it can save ~0.5mW on VDDARM, and
we can even power down VDDARM during DSM now.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Correct the GPL license to v2, not V2. Otherwise
this driver is GPL-incompatible, and can't be make
as module.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
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Some spi device drivers use the same tx_buf and rx_buf repeatly for better
performance such as driver/input/touchsreen/ads7846.c, but spi core grab tx_buf
/rx_buf of transfer and set them as dummy_tx/dummy_rx once they are NULL. Thus,
in the second time the tx_buf/rx_buf will be replaced by dummy_tx/dummy_rx and
the data which produced by the last tx or rx may be wrongly sent to the device
or handled by the upper level protocol. This patch just keep the orignal value
of tx_buf/rx_buf if they are NULL after this transfer processed.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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There's an error message when boot kernel.
...
i2c i2c-0: IMX I2C adapter registered
max732x 2-0068: failed reading
i2c i2c-2: Failed to register i2c client max17135 at 0x48 (-16)
i2c i2c-2: of_i2c: Failure registering /soc/aips-bus@30800000/i2c@30a40000/max17135@48
...
This error is introduced by touch driver patch. The reason is that
the TSC2007(touch) has the same I2C slave address as MAX17135 (Eink display
PMIC). This will cause that MAX17135 can not be detected.
The board has to be done with a rework (populate R172), and thus TSC2007's
slave address changes to 0x49. This patch updates the address to 0x49.
Signed-off-by: Robby Cai <r63905@freescale.com>
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change the maximum chips for i.MX7D, this part was missed when adding
i.MX7D NAND support.
Signed-off-by: Han Xu <b45815@freescale.com>
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