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2012-09-10tegra: dc: Fix div by zero in frame time computation.Raghavendra VK
- Set frame duration to 0 in NULL modeset. bug 1039104 Reviewed-on: http://git-master/r/127603 (cherry picked from commit 604cda21d79ed168e9863f0122eb0c23fa1a901b) Change-Id: I0be1b96529e40a374e4507ecd3da990677d4cbd4 Signed-off-by: Raghavendra VK <rvk@nvidia.com> Reviewed-on: http://git-master/r/130943 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10ARM: mutex: use generic atomic_dec-based implementation for ARMv6+Will Deacon
Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+") removed the barrier-less, ARM-specific mutex implementation in favour of the generic xchg-based code. Since then, a bug was uncovered in the xchg code when running on SMP platforms, due to interactions between the locking paths and the MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place lock in contended state after fastpath_lock failure"), however, the atomic_dec-based mutex algorithm is now marginally more efficient for ARM (~0.5% improvement in hackbench scores on dual A15). This patch moves ARMv6+ platforms to the atomic_dec-based mutex code. Change-Id: I8f64e98ccb61cc1cb9cb68ee15e55d8a792792f5 Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-on: http://git-master/r/130941 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+Will Deacon
The open-coded mutex implementation for ARMv6+ cores suffers from a severe lack of barriers, so in the uncontended case we don't actually protect any accesses performed during the critical section. Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec code but optimised to remove a branch instruction, as the mutex fastpath was previously inlined. Now that this is executed out-of-line, we can reuse the atomic access code for the locking (in fact, we use the xchg code as this produces shorter critical sections). This patch uses the generic xchg based implementation for mutexes on ARMv6+, which introduces barriers to the lock/unlock operations and also has the benefit of removing a fair amount of inline assembly code. Change-Id: I58e3ca4d2740a834d30b54fc35742fa2df7792ad Cc: <stable@vger.kernel.org> : 0bce9c46: mutex: Place lock in contended... Cc: <stable@vger.kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Pitre <nico@linaro.org> Reported-by: Shan Kang <kangshan0910@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-on: http://git-master/r/130940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10Merge remote branch 'origin/rel-16r5' into rel-16r5-null-mergeRohan Somvanshi
2012-09-06rtc: max77663: fix alarm reading bugDaniel Fu
When reading alarm of RTC-max77663, it didn't set alrm->enabled correctly, if irq is masked, means disable alarm, alrm->enabled should be set to 0, else it should be 1. Change-Id: Id0b1ffd9a816643712f33624d7d52cbe7b66b3c3 Signed-off-by: Daniel Fu <danifu@nvidia.com> Reviewed-on: http://git-master/r/129593 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-09-06arm: tegra: xmm: add post_resume phy callbackVinayak Pane
phy post_resume is called when usb port+hub is resumed, check if modem has finished resume by then. Notify modem about post resume by setting bb_wake to low. Modify check for CP initiated wakeup to read current modem state (ap_wake). Bug 1034420 Change-Id: Ie9a3aa581bd7660183464e3fc2554ceb055b69b2 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/129533 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-09-06security: tf_driver: integrate latest TL releaseHyung Taek Ryoo
Tegra 3 version: TF_TEGRA3_AB01.16.37161 Improvements in maintenance operations of L2 Cache Controlller. Change-Id: Iddbd61b21b6d83548d5a8c636e26b07b3b4f1385 Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/128948 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: James Zhao <jamesz@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Wen Yi <wyi@nvidia.com>
2012-09-06arm: tegra: secureos: disable L2 as part of sleep CPU SMCChris Johnson
This is an alternate way to have the L2 disabled available with later TL secureos versions. In this version, the sleep CPU SMC which is the last one issued before entering LP2 on CPU0, will also disable the L2 without a flush of the secureos workspace. Change-Id: I61c3caade6cb6f922b9d9f9ca0739bc6ae4e78cd Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/128951 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: James Zhao <jamesz@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-09-05ARM: tegra: enterprise: enable wl18xx wireless module supportRakesh Goyal
Bug 990784 Change-Id: I173df3f7244e7d0b40ae5aad98c72885ff42fdab Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-on: http://git-master/r/129103 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-05ARM: tegra: tai: fix gpio number for nfc and bluetoothRakesh Goyal
NFC use GPIO4 for download firmware BT_RST is required to make bluetooth on/off Bug 1002637 Change-Id: Ic49a3fe606de618dfafdf0bc35b6a6fc1ac12cdd Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-on: http://git-master/r/128612 Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-05arm: tegra: kai: update memory timingsKerwin Wan
bug 947148 Change-Id: Icc9711e44375dee9346cbe2cb8af090286a244a2 Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/126834 (cherry picked from commit 90ec2d7e47927723f8c088c178bb560828fac622) Reviewed-on: http://git-master/r/129571 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-09-05drivers:video:tegra: Fix CDMA timeout recoveryArto Merilainen
This patch fixes wait base handling in CDMA timeouts. Bug 1025617 Change-Id: Ia93e55631c1159da161d5c4f257d3beebf0d3149 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/129278 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2012-09-05arm: tegra: phy: enable wakeup event for usb phyRakesh Bodla
If usb device already connected, should disable WKCN in USB2D_PORTSC1, and enable WKDS in USB2D_PORTSC1, during utmi phy power off. All the wakeup resource should be cleared after the event happened. Bug 1020021 Bug 1028429 Change-Id: I807ca76d4392318adf6adb808cb2bf290cd0d60c Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/128547 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-09-05video: tegra: dc: fix boot issue with HDMIDeepak Nibade
Set default mode for probe and resume to enable initialization of dc.1 Skipping this initialization results in hard system hang. bug 1030415 Reviewed-on: http://git-master/r/124001 (cherry picked from commit 50fa5e50b74a0534d7524fb6d7dcaa65b2e6e74c) Change-Id: Id9ad95e114a27c1667f0286443534a23b7fa64d4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/128533 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-09-05video: tegra: dc: move set default videomode out of _tegra_dc_enable.Marvin Zhang
Set default videomode happens during probe and resume. _tegra_dc_enable is also called during hotplug, setting default videomode there causes hdcp test failure. Bug 991805 Reviewed-on: http://git-master/r/121052 (cherry picked from commit 7d4e0461a88b8cf638963e69829274824fecc38b) Change-Id: I98be07e883699ba9fa6e222bb1d8ea68d199dfc6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/128532 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-09-05rtc: max77663: Set Alarm wday to its reset valueDaniel Fu
The wday is configured only when disabled alarm. When enable alarm, set it to its default reset value 0x01, and not enable it, to prevent an error happened when re-read the alarm value into the virtualized generic layer at boot up in reading alarm setting of RTC. Bug 1034871 Change-Id: I8bfa997653edaaa286cf768c1827b5ab986f52cc Signed-off-by: Daniel Fu <danifu@nvidia.com> Reviewed-on: http://git-master/r/129398 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>
2012-09-05ARM: tegra: kai: adjust ov2710 power sequenceSang-Hun Lee
Update the power sequence to match the specification Bug 1031318 Reviewed-on: http://git-master/r/124496 (cherry picked from commit d2b1e1ddb2e65482eb15698b925471daf573a7ba) Change-Id: I837cafb494571816ee6ef25ea8159fc0de9fb2f5 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/128945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-04usbnet: fix skb traversing races during unlink(v2)Ming Lei
Commit 4231d47e6fe69f061f96c98c30eaf9fb4c14b96d(net/usbnet: avoid recursive locking in usbnet_stop()) fixes the recursive locking problem by releasing the skb queue lock before unlink, but may cause skb traversing races: - after URB is unlinked and the queue lock is released, the refered skb and skb->next may be moved to done queue, even be released - in skb_queue_walk_safe, the next skb is still obtained by next pointer of the last skb - so maybe trigger oops or other problems This patch extends the usage of entry->state to describe 'start_unlink' state, so always holding the queue(rx/tx) lock to change the state if the referd skb is in rx or tx queue because we need to know if the refered urb has been started unlinking in unlink_urbs. The other part of this patch is based on Huajun's patch: always traverse from head of the tx/rx queue to get skb which is to be unlinked but not been started unlinking. Signed-off-by: Huajun Li <huajun.li.lee@gmail.com> Signed-off-by: Ming Lei <tom.leiming@gmail.com> Cc: Oliver Neukum <oneukum@suse.de> Cc: stable@kernel.org Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit 5b6e9bcdeb65634b4ad604eb4536404bbfc62cfa) Bug 1040642 Change-Id: I1a8c248016529bebf71d540738ad4726cf3f59b7 Signed-off-by: Steve Lin <stlin@nvidia.com> Reviewed-on: http://git-master/r/128693 GVS: Gerrit_Virtual_Submit
2012-09-04ASoC: Tegra: Add ALSA ctl to set DMA addressSumit Bhattacharya
Add support for setting of DMA address through alsa control for AVP rendering. This is required to directly do DMA from IRAM to I2S. Bug 1024403 Change-Id: I6b79ae6e9a562160a19d238b817e1a8b407ac208 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/127436 (cherry picked from commit f270f46bef98a56f44432e608041adb617c22559) Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Change-Id: I195aae9043f967273283579f44d5367fe73d542f Reviewed-on: http://git-master/r/129159 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-09-04ASoC: dapm: Use DAPM mutex for DAPM ops instead of codec mutexLiam Girdwood
It has now become necessary to use a DAPM mutex instead of the codec mutex to lock the DAPM operations. This is due to the recent multi component support and forth coming Dynamic PCM updates. Currently we lock DAPM operations with the codec mutex of the calling RTD context. However, DAPM operations can span the whole card context and all components. This patch updates the DAPM operations that use the codec mutex to now use the DAPM mutex PCM subclass for all DAPM ops. We also add a mutex subclass for DAPM init and PCM operations. Signed-off-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit a73fb2df01866b772a48fab93401fe3edbe0b38d) Updated call sequences Bug 1039523 Change-Id: If079bbe5032971251d6b5426c752cbcc6ad6bcf5 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/128937 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-03ARM: tegra: cardhu: set I2S as slave modeChandrakanth Gorantla
enable slave mode for cardhu platform. BUG 998682 Change-Id: Iad330677154af417e0848059536581bcabdd98bc Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Reviewed-on: http://git-master/r/128734 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-09-03video: tegra: dc: support for vblank syncRakesh Iyer
Add wait for vsync support for one-shot panels. The code supports extension of this feature to other panels. Bug 1033411. Change-Id: Ie4d6cb45e5de81083458169ccdfa33230235ed72 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/128927 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2012-08-31enterprise pinmux: set the pinmux for audio portsNikesh Oswal
Bug: 1039342 Reviewed-on: http://git-master/r/127868 (cherry picked from commit 92f2d2099e3411dfa1966e8ead58dc5654f3124c) Change-Id: Ibe7dd39a06170766ec043ccbf18df0078ee9e7cb Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/128508 Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-08-29spi: tegra: Add stub runtime power managementLaxman Dewangan
Add stub runtime_pm calls which go through the flow of enabling and disabling but don't actually do anything with the device itself as there's nothing useful we can do. This provides the core PM framework with information about when the device is idle, enabling chip wide power savings. Change-Id: Ie795c16840ccbe07e1a8bfac1a1c5a87281e6849 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128184 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-08-29i2c: tegra: Add stub runtime power managementLaxman Dewangan
Add stub runtime_pm calls which go through the flow of enabling and disabling but don't actually do anything with the device itself as there's nothing useful we can do. This provides the core PM framework with information about when the device is idle, enabling chip wide power savings. The change is based on change done by Mark Brown for s3c2410 i2c bus driver. ---------- Author: Mark Brown <broonie@opensource.wolfsonmicro.com> i2c-s3c2410: Add stub runtime power management ---------- Change-Id: Icb92129c4f79a1642b2b73d14578b05928d745a8 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128151
2012-08-29i2c: tegra: rename fast clock and div clockLaxman Dewangan
Rename fast clock to "fast-clk" and div clock to "div-clk" in driver and clock table to have aligned with mainline as: This is based on change: --------- commit f16e6e77a105ec53496f0d8343895da342917873 Author: Laxman Dewangan <ldewangan@nvidia.com> i2c: tegra: pass proper name for getting clock --------- Change-Id: Ie9a1972a18e2e60ac7c84c4509860cf72405ef16 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128150
2012-08-29i2c: tegra: remove support for I2C_M_REV_DIR_ADDRLaxman Dewangan
The Tegra i2c controller actually can not support the reverse of direction address (toggling r/w bit of address) as controller take 7 bit address from configuration and HW make it 8 bit address based on read/write flag. Hence reverting this protocol mangling support. Change-Id: I987b2be343d535c078e27b44575717a209d15584 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128149
2012-08-29video: tegra: host: Use unsigned integer in sysfsTerje Bergstrom
Sync point values are unsigned, but sysfs creates the text representation as signed. Correct to use unsigned representation. Bug 1039058 Change-Id: I96de13952eeeba9510bae179a036459ddee18dcd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/128075 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Michal Pecio <mpecio@nvidia.com>
2012-08-29arm: tegra: tai: keep smps4 ONSeema Khowala
Bug 1029431 Change-Id: I79ba7e363feeaec86912445ce005ea65a3960718 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127994 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29ARM: tegra: tai: Add tai machine numSeema Khowala
http://www.arm.linux.org.uk/developer/machines/list.php?id=4311 Bug 1002637 Change-Id: Id52214c1780294e4e4a6607b954c05e9be950fdd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127978 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: config: Add TaiSeema Khowala
Bug 1002637 Change-Id: I33d38ab3a5395f85564ef9a3282db152b4d79113 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127974 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29chromeos: config: armel: enable full L2 maintenanceKirill Artamonov
When allocation is bigger than L2 size it is more optimal to flush or writeback whole L2 instead of doing maintenance for each allocated page. bug 983964 Change-Id: Ibb3609be71621ff9ab75bea9146bfe7578f9315a Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/127835 Reviewed-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-08-29arm: cardhu: change parameters for emc 266.5mhzWen Yi
The EmcTclkStable is set to 0x00000004 and McEmemArbOutStandingReq is set to 0xc0000030 Bug 1030392 Bug 1039060 Reviewed-on: http://git-master/r/122302 (cherry picked from commit a3a1d1797e310d61204256af8be995f9396c22e7) Change-Id: Ic65334a6573582ae99d05a8f6f8290096755827e Signed-off-by: Wen Yi <wyi@nvidia.com> Reviewed-on: http://git-master/r/127458 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: cardhu: correct EMEM_ARB_CFG in emc dfs tableWen Yi
The memory frequencies 266.5mhz and 437mhz have incorrect EMEM_ARB_CFG set in emc table of Samsung part. That resulted in emc scaling completely disabled and emc runs at 533mhz all time. The settings have been corrected to 0x00000008 and 0x0000000D. Bug 1030392 Bug 1039060 Reviewed-on: http://git-master/r/122163 (cherry picked from commit f691268c138b9ed31b3867b049e64c121ecb188e) Change-Id: I13f89c19af5391743aeba348f4a3ca4a73307bdf Signed-off-by: Wen Yi <wyi@nvidia.com> Reviewed-on: http://git-master/r/127429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
2012-08-29video: tegra: host: Disable irq when clock gatingTerje Bergstrom
Disable host1x interrupts when clock gating host1x. This fixes a race where host1x interrupt was raised at the same time when host1x clock is turned off. Bug 1031724 Change-Id: I169cd5796608b8888a6b48ed99bb5da754559b2c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/125129 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-08-29arm: tegra: Enable LP1_950 configKarthik Ramakrishnan
Enable LP1 Core voltage settings to 950mV The feature is added in the below change. Refer to http://git-master/r/#change,124135 for more details. Bug 1035684 Change-Id: I922efff17797f4666fd6ed069a8523c164445842 Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit 0f5d34db547ca6bfb9c0bae0b0048f58ba71c833) Reviewed-on: http://git-master/r/124781 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: Board files settings for LP1 0.95V CoreVKarthik Ramakrishnan
Set the register values for each of the board files to keep the Core voltage to 0.95V in LP1. This change is only for those platforms where LP1 is supported. Enterprise and Kai are the main platforms for this change. There is no support for Cardhu for LP1 and so is left blank and the feature will be skipped for Cardhu platforms, except for AP37. AP37 with a PM269 board needs this change and so Cardhu board file is updated with the values specific to AP37. This change is part of the feature to set VCore to 0.95V Refer to http://git-master/r/124135 for more details Bug 1035684 Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a) Reviewed-on: http://git-master/r/124780 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29video: tegra: fb: Default stride from HWChristopher Freeman
This patch adds: 1. line_stride value is honored in fb_set_par routine 2. Hardware value for line_stride is used in fb_register Bug 1025739 Change-Id: Ic37c4c90911c2c70e74b8d5609f3b32b521772ff Signed-off-by: Christopher Freeman <cfreeman@nvidia.com> Reviewed-on: http://git-master/r/127690 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-08-28Revert "Revert "ARM: tegra: enterprise: update memory timings""Simone Willett
This reverts commit 0405128605ed7a858aecb8fb9aaaf80e0e44c4b8 Change-Id: I3a0ee9b0079b884d53c43323e21b472a40c31bb7 Reviewed-on: http://git-master/r/125323 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
2012-08-28video: tegra: cardhu: Default bpp from hardwareChristopher Freeman
This patch adds: 1. A kernel config option that hints to DC driver to use the current value of the color depth register as the default for initializing the FB driver. 2. Checks to see if DC is enabled before reading off the color depth register in tegra_dc_probe. Change-Id: I852cc1328fcf42f33052f46b86d753e691744329 Signed-off-by: Christopher Freeman <cfreeman@nvidia.com> Reviewed-on: http://git-master/r/127297 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-08-28arm: tegra: p1852: set FPDLink latch clock edgeDongfang Shi
Make parallel data strobed on rising clock edge For SKU2 MODS get correct CRC. Bug 995623 Change-Id: I70f4b87e781821cf4ff8370c17b79f5bea7dc55c Signed-off-by: Dongfang Shi <dshi@nvidia.com> Reviewed-on: http://git-master/r/121824 (cherry-pick from 5200d0f10b936e00dbc2a946eed8c2e48b039943) Reviewed-on: http://git-master/r/122537 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-08-28E1853 BRINGUP Linux Snor: Micron SupportBob Johnston
Expanding NOR functionality to work with ADMUX and Burst mode for Micron Support in E1853. Bug 989919 Bug 966833 - Adding fields for picking MUX vs NONMUX and picking Async, Paging, Burst mode for reads - Added run time decision between them - 1853 specific settings for Async NOR - 1852 specific settings for NOR - 1853 NOR timings changed Reviewed-on: http://git-master/r/122286 (cherry picked from commit a242e7194c7de559d22fe5b275a8782086f10e50) Change-Id: I79de1d52d4c7199c83b380c2fa6d8cae6b35f09d Signed-off-by: Bob Johnston <BJohnston@nvidia.com> Reviewed-on: http://git-master/r/124946 Tested-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-08-28enterprise pinmux: set the pinmux for audio portsNikesh Oswal
Bug: 1039342 Change-Id: Ic1f0e9fa8c8d9e69b7fb9cd35d2cbbf578c579e5 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/127868 Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-08-28video: tegra: nvmap: implement full L2 clean/flushKirill Artamonov
When allocation is bigger than L2 size it is more optimal to flush or writeback whole L2 instead of doing maintenance for each allocated page. bug 983964 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: Ieaa70875b92920567ad7cd75eca6eac8197f46de Reviewed-on: http://git-master/r/108511 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-08-28ARM: tegra: enable errata 727915 for Tegra3Kirill Artamonov
By-way maintenance doesn't reliably work with enabled lp2_in_idle on Tegra3 platform which uses R3P1_50 revision of pl310. Enable errata 727915 for Tegra3 to avoid system hang. Change-Id: Ia296c1d5b35b8f28353c15d1e4622686bc7d3beb Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/127225 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-08-28ARM: cache-l2x0: fix L2 maintenance for R3P1_50Kirill Artamonov
Do flush and clear by set/way instead of by-way by enabling errata 727915 for pl310 revision R3P1_50. By-way maintenance doesn't work with enabled lp2_in_idle on Tegra3 platform using R3P1_50 revision of pl310. Debug register access causes hang when CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined. bug 983964 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6 Reviewed-on: http://git-master/r/125153 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Tested-by: Antti Miettinen <amiettinen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2012-08-28arm: tegra: tai: correct gpio for voice callSeema Khowala
Bug 1031990 Change-Id: I9410bc0347544701a753287713f9537710e7533f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127620 Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com>
2012-08-28Revert "video: tegra: hdcp: Fix Locking Issue"Matt Wagner
This reverts commit 51f746421b73f8f378bd7908b35fd6c79687e239. Bug 1030468 Bug 1030415 Signed-off-by: Matt Wagner <mwagner@nvidia.com> Change-Id: If9b5febd812e84848913431dcaf0bdefc518e5d1 Reviewed-on: http://git-master/r/126948 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-08-28Revert "video: tegra: hdcp: Add Missing Lock"Matt Wagner
This reverts commit 77c8da0aa18fad9e33fd8b1afb2013b1a476d74e. Bug 1030468 Bug 1030415 Signed-off-by: Matt Wagner <mwagner@nvidia.com> Change-Id: I2b85159dfcfc40b3a3632dc1300c729e0977a18f Reviewed-on: http://git-master/r/126946 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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