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2012-07-12ARM: Tegra: cardhu: No longer invert backlight on PM313Graziano Misuraca
Backlight value was inverted for panels with PM313. This assumed the panel was the 15", but because the 10.1" (AUO) is more prevalent and doesn't have the inverted backlight signal we no longer need to invert it. Note this will fix the backlight issue for AUO E1198 boards but break it for 15". Bug 962636 Reviewed-on: http://git-master/r/#change,93965 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Change-Id: Icb65592eb2df21e349e5a759a780e4438a0f5b26 Reviewed-on: http://git-master/r/95728 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11arm: tegra: pm269: 12.75mhz emc rateWen Yi
Add 12.75mhz emc frequency for Samsung K4P8G304EB-FGC2 LPDDR2 1GB memory chip. Bug 1011100 Change-Id: Ibbbb3f002c36c31cd2806051803ddd3ba9daa63b Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit a37cb14dc441005ddd977b6a83f41df817179d79) Reviewed-on: http://git-master/r/113383 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-11video: tegra: treat compilation warning as errorSanjay Singh Rawat
- Adding flag to treat warning as error. - Handled warning of unused function. bug 949219 Change-Id: Ic6edfc28bae95b8395cbd51e80f14aa4aa663f61 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/114624 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-11net: wireless: WFD specific changesJun (Gab-Joo) Lim
WFD specific changes integrated from broadcom patch Bug 1001418 Bug 997838 Change-Id: I0632307bf5fb959def4ee12687430a14ab9e068e Signed-off-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-on: http://git-master/r/111032 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-11media: video: tegra: sh532u: Focuser range tuning supportNaren Bhat
Support for get/set capabilities added. Focuser code has a way to calibrate itself that results in determination of optimal working range. This along with actual range from device ROM are returned to the caller. Focuser has the macro at lower end and infinity at farther end of the range, which are reversed to the user level to keep the inf/macro positions to be consistent. Focuser range translation is taken out. Bug 1004816 Change-Id: I1a086ff10e99940f9ad861397bf7e71e9996c68a Signed-off-by: Naren Bhat <nbhat@nvidia.com> Reviewed-on: http://git-master/r/110443 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Charlie Huang <chahuang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Patrick Shehane <pshehane@nvidia.com> Tested-by: Charlie Huang <chahuang@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-11arm: tegra: cardhu: move VI to PLL_PJihoon Bang
As a part of effort to bring in 437MHz clock frequency in EMC, We need to move VI from PLL_M to PLL_P. Bug 1005576 Signed-off-by: Jihoon Bang <jbang@nvidia.com> Reviewed-on: http://git-master/r/112704 (cherry picked from commit c175857e80355857b55e8eb2012c12e94e532835) Change-Id: Icd314c01625f5c4765b0215735ceafb7d3f25d1e Reviewed-on: http://git-master/r/114241 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11video: tegra: nvmap: Introduce IOMMU backend instead of IOVMMHiroshi DOYU
Introduce IOMMU backend functions which use DMA API familiy internally. Replace tegra_iovmm_*() API with arm_iommu_*iova*() and dma_(un)map_page_(at)(). Change-Id: I0b014926ffedc12bf8f868b163982c6082d050b6 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11ARM: tegra: iovmm: Allow alloc_client to take struct deviceHiroshi DOYU
Allow tegra_iovmm_alloc_client() to take struct device * instead of const char *name w/ __tegra_iovmm_alloc_client(). This is necessary to support IOVMM and IOMMU simultaneously. Change-Id: I18df5001bfe0ece8f9f15b636eb11def9f228dfb Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114215 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11iommu/tegra: smmu: move tegra_smmu_init in core_initHiroshi DOYU
Move tegra_smmu_init in core_init. IOMMU should be available at early stage of system booting. Change-Id: I8675e62acef44fb585a731c0f24be716b76ca41a Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114214 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11iommu/tegra: smmu: Enable all SWGRP by defaultHiroshi DOYU
Revisited later with new conf passed from DT. Change-Id: Ic94a698b0ee56603bbb7f2204ae8c5412ea133b1 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11ARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GARTVandana Salve
Replace TEGRA_{SMMU,GART}_{BASE,SIZE} with TEGRA_IOMMU_{BASE,SIZE} to deal with SMMU/GART in unified manner. This is necessary for DMA mapping API to pass the appropriate IOMMU address for SMMU and GART in the same code in nvmap. [Hiroshi Doyu: Squash nvmap parts into "nvmap: API conversion" patch.] Change-Id: I75429dd56554f880f144c375d2c20e8e8948ceee Signed-off-by: Vandana Salve <vsalve@nvidia.com> Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11arm: tegra: p1852: Add IOMMU_SMMU supportHiroshi DOYU
Migrating from IOVMM_SMMU to IOMMU_SMMU. Change-Id: If5bca4a3bce15d59641f11dfea3ad6da2a8efbf5 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114211 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11ARM: tegra: Remove duplicate clock initsSai Charan Gurrappadi
Change-Id: I80c384d1aa4b1e45a4542acbde6b904f4a014aff Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com> Reviewed-on: http://git-master/r/113679 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-11cpuquiet: Account for the corner case frequency when setting stateSai Charan Gurrappadi
Now consider frequency greater than or equal to idle_top_freq as UP Change-Id: I1332d46d1e42a00b3b31897b158eaf4ccfbaf8f5 Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com> Reviewed-on: http://git-master/r/113678 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-11sched: unthrottle rt runqueues in __disable_runtime()Peter Boonstoppel
migrate_tasks() uses _pick_next_task_rt() to get tasks from the real-time runqueues to be migrated. When rt_rq is throttled _pick_next_task_rt() won't return anything, in which case migrate_tasks() can't move all threads over and gets stuck in an infinite loop. Instead unthrottle rt runqueues before migrating tasks. Bug 976709 Change-Id: Ie3696702abc560fe8ffa7d2fb5dc5d54d532cc0d Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> (cherry picked from commit 4d18ba5765c206bf9f37634f532d97dabd507a58) Reviewed-on: http://git-master/r/103417 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-11drivers: misc: fixed therm estimator bugJoshua Primero
Fixed hi and lo limit bug in thermal estimator driver. bug 1007726 Change-Id: I2be90ca7d875dbed34004b83f070fb5cbd8bc467 Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/113564 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-11ARM: tegra: thermal: fixed some skin thermal bugsJoshua Primero
Fixed bug where skin cooling device is being bound to nct device instead of skin thermal device. bug 1007726 Change-Id: Ia6316735da8895fd4f4c20c0a76cd6796dafdf9b Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/113563 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11PM: move initcall_debug message in syscore_resumeDaehyoung Ko
debug uart driver needs to be resumed before calling printk so move debug message after finishing resume bug 992588 Change-Id: Ia8991a4b7be7a4e2a765c8e6b494fd906b38b98c Signed-off-by: Daehyoung Ko <dko@nvidia.com> Reviewed-on: http://git-master/r/108435 (cherry picked from commit 75e7ef273d52b40d5d662541043e7eebc74ee24e) Reviewed-on: http://git-master/r/110433 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-11ARM: tegra: cardhu: disable VBUS wakeBitan Biswas
Disabled USB1 VBUS wake up on board revisions prior to E1291-A03 and E1198-A02. We see repeated LP0 wakeups if the wake source is enabled. bug 980993 Change-Id: I080696924aaea06f973392fe7682fecc7574bf02 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/103627 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11usb: otg: tegra: wake enabledBitan Biswas
Wake sources usb VBUS or ID detect enabled bug 980993 bug 936982 Change-Id: Iea36d308c1a118abdb7815212d749bd058d0054f Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/103141 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-11ARM: tegra: support multiple wake sources with same irqBitan Biswas
Earlier implementation only allowed single wake source for a particular irq in wake table. Changed implementation to support multiple wake sources ==> single irq mapping. bug 980993 Change-Id: Iacb00487531129ef19c53128824aba802e80350e Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/103140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-09crypto: tegra-se: Enable interrupts after clock enableVictor(Weiguo) Pan
Because SE interrupts could be enabled in bootloader, if it's not cleared before jumping into kernel, it continues to assert the interrupt line to interrupt controller. When SE interrupts is enabled in kernel, to access SE registers in IST without clock enabled hung the CPU. To fix this issue, interrupt enabling is moved after clock is enabled. bug 1010334 Change-Id: I1b909efce2c9d92c3112039fc217f7c1360f9bbb Reviewed-on: http://git-master/r/113073 (cherry picked from commit b06e6662f738ad01a3b2b6803db654abaa03385e) Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com> Change-Id: Ide4b0295c781e0bba7aa071616e3e6160e44ee76 Reviewed-on: http://git-master/r/114064 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-09video: tegra: host: t30: Add syncpt/epp in ISP chSonghee Baek
This change is for programming VI and EPP through ISP channel to support RGB input and dual video capturing. 1. Added syncpt in the ISP channel to submit the channel. 2. Added epp clock to use VI2EPP for RGB capture. Note: To use this channel, EPP should be free from 2D. Bug 988546 Change-Id: I17fe278c9325aac2ea1e29cbaf50c8a4499d8551 Signed-off-by: Songhee Baek <sbaek@nvidia.com> Reviewed-on: http://git-master/r/113965 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-09video: tegra: host: resolve compilation time warningsSanjay Singh Rawat
- Handled warning of, possible use of uninitialized variable and unused function. bug 949219 Change-Id: I0d7d345e66774f08e52a12e653a5e7aa6a7a8591 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/113905 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-07-09video: tegra: resolve compilation time warningsSanjay Singh Rawat
- Handled warning of unused label. bug 949219 Change-Id: I72e22063b199562c4a4c065419c1656e3e8ff7ff Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/113880 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-09video: tegra: dc: vblank workerMark Zhang
Freeze vblank worker while suspending by adding the work into system freezewq. This eliminates a kernel panic caused by nvsd reading brightness valuesfrom display while clock gated. Bug 1006180 Bug 1003969 Bug 1003730 Change-Id: Ice9bfb18e5c826ae063c2b901421b1047ff9d2f0 Signed-off-by: Mark Zhang <markz@nvidia.com> Reviewed-on: http://git-master/r/112880 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09video: tegra: dtv: Fixed clk disabling issueAdam Jiang
APB clock for dtv logic block should be recorded by dtv_ctx->clk hanlder. Otherwise, kernel will trigger a NULL point error in suspend. Fixed Bug 1011149 Change-Id: I5d342ab6fc8ffb71211e370d304b17d5d44eef20 Signed-off-by: Adam Jiang <chaoj@nvidia.com> Reviewed-on: http://git-master/r/108743 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-09input: misc: fix compile time warningChandler Zhang
Add init value for rc in lightsensor_ioctl() to fix compile time warning. Change-Id: Ifcb953873b5bc861303d9d32b1906a69b2c8311f Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/113121 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09usb: otg: remove otg callbackChandler Zhang
Previously the callback was added to control USB VBUS. The standard way is to use regulator. Bug 997805 Change-Id: I88b15befaf4e162478da19ead50695978b2c5f4b Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/112901 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-09arm: tegra: kai: use regulator to control vbusChandler Zhang
Use regulator instead of USB OTG callback to control USB VBUS. Bug 997805 Change-Id: Icd2869f51e312c52b272a6e32fa8c7ab8763a5ac Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/112900 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09power: smb349: remove otg callbackChandler Zhang
The callback in otg driver is not a standard way of controlling USB VBUS. Remove the callback and use regulator to control. Bug 997805 Change-Id: I6d7fd01f9346e037515901ac6fe6d349a140d13e Signed-off-by: Chander Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/112896 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-09ARM: tegra: fiq_dbg: Enable FIQ serial debugKamal Kannan Balagopalan
Add platform callback to initialize and enable FIQ serial debugger Bug 970018 Change-Id: Icdf571f7698e10de661a0ce94694de9fb9c70271 Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/110955 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09ARM: common: fiq_dbg: Spew regs and stack at entryKamal Kannan Balagopalan
Dump all registers and callstack immediately after entering the FIQ handler. Bug 970018 Change-Id: Iab48f5a942b45015a9def0839cf3ef721dda8a5c Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/110954 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Steve Kuo <stevek@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-09watchdog: tegra: Add support for FIQ debuggerKamal Kannan Balagopalan
Enable FIQ on 2nd watchdog expiry to make use of FIQ debugger. FIQ debugger can be used to dump call-stack and registers when WDT logic triggers FIQ on 2nd timeout. Bug 970018 Change-Id: Ia2e7f8b136499974ff51f2f0c2ef55704dfe37e1 Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/110953 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Steve Kuo <stevek@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-09arm: tegra3: usb_phy: Fix warning message for lp1 resumePreetham Chandru
When the system resumes from lp1 for usb wake event we are seeing the below warning message: usb_phy_bringup_host_controller: timeout waiting for PORT_SUSPEND The above warning message are seen only for lp1 resume and not for lp0 resume. This is happening only for lp1 resume because in usb_phy_bringup_host_controller(), the port is suspended only if we are not resuming from remote wakeup, in case of lp0 remote_wake flag is set to true but not in case of lp1. This is because in lp1, pmc is not responsible for waking the system but it's the flow controller and hence UTMIP_WALK_PTR_VAL(inst) will return 0 due to this remote wakeup flag was getting reset to false. Bug 985396 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I67fcf21d77cbc627315164b6e1c4f27b0b9ae2c3 Reviewed-on: http://git-master/r/110064 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09ARM: tegra: wdt: Remove legacy WDT device supportKamal Kannan Balagopalan
Tegra3 adds new CPU watchdog timers. Remove the obsolete legacy WDT support for Tegra3 Bug 857748 Change-Id: I82478e1b43f22f39c1b8e6e66ae5299ffd079d1b Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/109908 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09ARM: tegra: wdt: Replace legacy WDT with CPU WDTsKamal Kannan Balagopalan
Tegra3 adds new CPU watchdog timers. Replace legacy WDT with CPU WDTs in all Tegra3 platforms. Bug 857748 Change-Id: I5bd30687003e6b2ebf09916fbd626d82f0bc0b76 Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/109907 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09arm: tegra: fix power down sequence fps/ameChandler Zhang
Fix power down sequence to align with POR. FPS, GPIO and AME part. LDO4 tracking is not disabled. Affcted regs: FPS_SD3 FPS_SD2 FPS_SD1 FPS_L4 FPS_L3 AME_GPIO GPIO3 GPIO4 CNFG1_L4 CNFG1SD0 CNFG1SD1 Bug 1001267 Change-Id: I8db160bf00cbe8f215c6e1b762d994d26d82809f Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/109134 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-09ARM: tegra: wdt: Add support for Tegra3 CPU WDTsKamal Kannan Balagopalan
Tegra3 adds new CPU watchdog timers. Add device support for the CPU WDTs. Bug 857748 Change-Id: I0f99c37fed89879d39667b734654c659fe631aaf Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/108379 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09watchdog: tegra: Revamp Tegra watchdog supportKamal Kannan Balagopalan
- Make all CPU watchdogs accessible except WDT0 - CPU WDT0 is reserved for suspend/resume WDT recovery - Fix WDT enable sequence on watchdog driver probe Bug 857748 Change-Id: Ia2d07856c32230ab8c9195fee151af09bce3ddde Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/99780 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Steve Kuo <stevek@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-09hwmon: tsensor: fix system hang in 0C.Linqiang Pu
Changed the low temp to 0C since 20C is very easy to trigger thermal alert under -15C to 15C environment temperature. And the thermal alert will run into endless alert from tsensor_work_func. Also revised suspend and resume routine to cancel the work when suspending and disable/enable irq. Bug 999175 Signed-off-by: Linqiang Pu <dpu@nvidia.com> (cherry picked from commit 6a909bfa690991438be298d4933946a92e4929c4) Change-Id: Icafc6d5f0164204cc0cb7bea64bef2fadadbfbfd Reviewed-on: http://git-master/r/111550 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-09ARM: tegra: thermal framework notifierBitan Biswas
Tegra thermal framework notifier is used to bypass driver callbacks after suspend is initiated. bug 999175 Signed-off-by: Linqiang Pu <dpu@nvidia.com> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> (cherry picked from commit de6b3b3e4b05edf05ceeda820a8aac548a83d410) Change-Id: I93bee5d6a4e2738db0d4db821035900b64a850be Reviewed-on: http://git-master/r/108924 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com>
2012-07-09hwmon: tegra: improve tsensor accuracyBitan Biswas
tsensor driver uses fixed point approximations. Improved accuracy of tsensor temperature reading - adding support to handle negative temperature to counter conversions and vice-versa bug 1001632 bug 999175 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> (cherry picked from commit 86ae0bdc3fbd34a5a1d0e08f7721ed527ddf5408) Change-Id: I5f6df85611d502a6dda1186234078fe973d7ca75 Reviewed-on: http://git-master/r/100576 Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-07-06arm: tegra: kai: cleanup the codeKerwin Wan
kai doesn't use spi4 at all so clear the relevant code. Change-Id: I6d04a880d3f4a793bd32181453897c0f6dd372cf Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/113470 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-by: Hao Tang <htang@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-06ARM: tegra: enterprise: OFF rails in sleep stateLaxman Dewangan
OFF the rails when the system is in sleep state. The rails are linked withe xternal req PREQ1 which is the core_pwr_req line. Followng rails are attached to PREQ1: SMPS2, SMPS4, LDOUSB will be attached to PREQ1 LDOLN, LDO7, LDO6, LDO4, LDO1 CLK32KG, SYSEN, REGEN2, REGEN1 will be attached to PREQ1 bug 979143 Change-Id: I20973faa78ef61fcd03cbe34445f94c36e280544 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I2ba5ca2aa1732222628d68f61d77acff88092d81 Reviewed-on: http://git-master/r/111185 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2012-07-06ARM: tegra: whistler: get rid of gpio enable/disable callsSanjay Singh Rawat
Gpio direction setting and freeing functions will do the needful now. Bug 984440 Change-Id: I32b1b0d67d2ebe1aa8b766b633fe675543714812 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/104938 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-06ARM: tegra: pm269: enable vibrator railLaxman Dewangan
Enable vibrator rail in order to support the vibrator. bug 1005183 Change-Id: I7133b259df590ad9dd376693b2f3224eb4431ec4 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/113635 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-06cpufreq: mid-range frequency biassatya popuri
Restrict go_maxspeed_load and max_boost at mid-range frequencies. Change-Id: I9e3c59bbe708b428e12ce4dbef2144be09751d5a Signed-off-by: satya popuri <spopuri@nvidia.com> Reviewed-on: http://git-master/r/111754 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Karthikeyan Samynathan <ksamynathan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-06crypto: tegra-aes: synchronize dma buffer accessSanjay Singh Rawat
- Using the dma sync apis to keep coherency. bug 984039 Change-Id: I9e389d2679f05c519ae4a51462247b7efeae01ca Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/111612 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-06ARM: tegra3: clock: Add EPP clock for ISP channelSonghee Baek
Adding EPP clock is for using EPP to support rgb capture in ISP channel. Bug 988546 Change-Id: I7d02cccfd228a235a7eadd67ae3304757ce90360 Signed-off-by: Songhee Baek <sbaek@nvidia.com> Reviewed-on: http://git-master/r/108413 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 21:19:28 +0000