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* set bsea sclk to ulong_max
* use unbounded work queues with 1 max_active
work item on each of them
* clear INTR_STATUS per operation
* free nvmap handle after using it
Bug 803932
Reviewed-on: http://git-master/r/#change,30196
(cherry picked from commit b0f6c074aab8a9f3bddec4a204b618180df630db)
Original-Change-Id: Ica9d702db9a247110d0639c64ab65672f02d7451
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/31936
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R5a51f9a8f7133a7e08f6544bbee581e30b46c6b5
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Added support for Security Engine.
Following HW features are supported:
CBC,ECB,CTR,OFB,SHA1,SHA224,SHA384,SHA512 and AES-CMAC
Original-Change-Id: Ic45c29add689f55be68966d333d1cb7cdb378353
Reviewed-on: http://git-master/r/29950
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R57f92020a7a713f624afe3b1d42da489bf89daba
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* add bsea engine support for encryption and decryption
* add arbitration semaphore id for bsea
Bug 803932
Original change: http://git-master/r/#change,29672
(cherry picked from commit 0008cdb0f38d0cd0c074671fc067c4321f340b06)
Original-Change-Id: I59fcaab29c47a8b42e7470b30486851cfe90848f
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/30190
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R6f1bf287860a24d0a535e49f516581b31092d182
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Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496
Reviewed-on: http://git-master/r/27559
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1
Rebase-Id: R46eb4226a3d37331db92f05d1a6e1c8e45f682a2
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Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a
Rebase-Id: Rb4bacf7db8c96e1865380466ef7eca71d72d08bc
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Bug 787628
Original-Change-Id: I73c3b8f0b3e69f1c4bc13bdaea84b19b14eb73d1
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/28003
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdf987e66c66135392489bd73ca16429d4d05d636
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clients call the algorithm's close api, which
results in the algo's cra_exit getting called, when
they are done using the hardware. we need to free the
key slot which was being used by the client when its
cra_exit is called.
Original-Change-Id: Ib42d445f5068c4ea1ef6b3edbbc547fe9eeef583
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/24673
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R8676bc01e6930c3164f8cc22d96023e0aeb44a3e
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Original-Change-Id: I7d8fe24ab5aa914fc2753f256eec261fcbf746bc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/22594
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Re4de8ecdfd6507cad5e0196882326d00f5ae79e0
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This reverts commit 8bc4f710e981d53a9bd161c6c054241231e09149.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Original-Change-Id: I0497afd3ec54e7b835de37e9941b2418e3dad4e3
Reviewed-on: http://git-master/r/22963
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rf393b9a6102e4550c44bc538ccc541879890f924
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This reverts commit a8dbfda58a6980976de60ba46f22a5f0b2ecab5f.
Original-Change-Id: I70407c45cc5605ad9924a5a1145e18371dc9d2ef
Reviewed-on: http://git-master/r/22554
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdfc2a43ce9137e1a7ff81b78868c2e48f91f1b02
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- set the key only at the start of encrypt/decrypt operations
- avoid using mutex in handle_req, since it is already serialised
- sanity checks while setting the iv
Original-Change-Id: I026e138f59d661cd705db6820bed63e5e15f02c5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/22162
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R11bd949802ebf158b87b8705aab5271c27da844b
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ssk slot is write-locked so the driver should not
track in its free slot pool.
Original-Change-Id: Ibf04a949a2894ef2c41851e7e92c13901c873bf2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/22161
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R7ae05f50294e8a7f0241296aee53cda57aa36a5f
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Original-Change-Id: I41ba8dfc193b346eda522eadfb0f9035f4d838f8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/22160
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R8351adfba377ede436f101194551e8091aa5528b
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Rebase-Id: R177e2f8e2b79f789558d19e4b17863c9b29fab9e
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This reverts commit 09e0e4fb75de1a008f00025a186d756435f9f034.
Rebase-Id: R7f871bc41beda798acea8b9c7c32d50531ad88e0
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Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Rebase-Id: R326381df3f4188cc1f700eb210c12b483afe9e77
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Change-Id: I9f10244b0603f7842b8504a16124d40dc4a71ed2
Signed-off-by: Colin Cross <ccross@android.com>
Rebase-Id: Rdc49da8123b4e700f2987a4a5ea19ad2b29ff1d6
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857ac889cce8a486d47874db4d2f9620e7e9e5de (ext4: add interface
to advertise ext4 features in sysfs) added an error check that
exposes a bug in the computation of sbi->s_itb_per_group. If
the number of inodes per group is not a multiple of the number
of inodes per block,
Original-Change-Id: I8c60817dbb6feb43535b567ec7ea5ee0af709c37
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit 8703a0ccb0135ae0de0d7011f29eeb6dc1caa486)
Rebase-Id: R7fc03850010d565447bb8702710040f112705738
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Original-Change-Id: I7be84ad877d1865c639ee5856f546276c8fdac73
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit e8945b26135c260f91c12a85cc911a165ab07504)
Rebase-Id: R3051e65e6a756bdad25ade5f865b383d9a2164e3
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Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM. This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.
Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.
Original-Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Rebase-Id: R7ae4d4825e9171bca2471fe776ecf363e75b9ca6
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This reverts commit 5dba29d1f761502e75320770fc4c6cf9c8e00998.
Rebase-Id: Rb6889e4755716f5baa5c7f272ae7d8c8b6d97ba5
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This reverts commit 5bf3a3e0d18712006090000256086c4a1672cca7.
Conflicts:
drivers/tty/serial/tegra_hsuart.c
Rebase-Id: R53d1706a5d5cdd2f06756158e6a4fb0e93f840e9
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Fixed index calculation when parsing E-EDID block SVD entry
in fb_edid_add_monspecs().
Change-Id: I0273e2f29e86687607923d07faf99a30696f5ead
Signed-off-by: Eric Laurent <elaurent@google.com>
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Looks for ieee registration number 0x000c03 as per HDMI spec.
CEA-861-E section D.6.8.
Change-Id: I6875b24c66e8754510edabcb4f9ba682a50d6ac1
Signed-off-by: Erik Gilling <konkers@android.com>
Signed-off-by: Lajos Molnar <molnar@ti.com>
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CEA defines multiple timings with dual timing ratios that cannot
be distinguished from timings parameters. Added 2 new fb flags
to specify 4:3 or 16:9 display ratios.
Also added a flag that denotes CEA formats that require repeating
pixels.
Change-Id: I75d413babdcb4048a0ccce6548ed386ad0e52318
Signed-off-by: Lajos Molnar <molnar@ti.com>
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These mode are directly from the CEA-861-E spec.
Change-Id: Ic29390fb8dfc4605da1f95aaee0e2e775dfc0a4a
Signed-off-by: Erik Gilling <konkers@android.com>
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This reverts commit c326f06779fb6bdd7f92c3ede8d1bebbe2fafbfa.
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To allow the spinlock lockup detection to actually trigger after
60 seconds, the tegra_wdt heartbeat needs to be longer than that.
Bumping it to 120sec, as at the 50% marker the watchdog takes an
interrupt.
Change-Id: I099fd7720d65c0e2050fa91161e30485fe84a1ed
Signed-off-by: JP Abgrall <jpa@google.com>
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When exiting lp2, each cpu boots through cpu_resume, which
modifies the last used page table to add a 1-1 mapping in
order to turn on the mmu. The first cpu to boot triggers
booting the second cpu, and if allowed to continue immediately
may start executing a userspace task that is using the same
page tables as the second cpu is modifying during its boot
process. Hold each cpu in a loop until all cpus have
finished booting to ensure page tables are back to their
original state. Each cpu triggers a global tlb flush
after it restores the page table, so all cpus will see the
original values before they exit idle.
Change-Id: Iad91ae57e2abbbec3d6d491460c3e19411b519c0
Signed-off-by: Colin Cross <ccross@android.com>
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tegra_sleep_wfi disables coherency to prepare for possibly
resetting the cpu. If an interrupt is received, it exits
wfi and re-enables coherency, but it was not flushing the
tlbs or the branch predictor array, which could have been
updated by broadcast tlb operations that were ignored.
Flush the tlbs and branch predictor array when exiting.
Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191
Signed-off-by: Colin Cross <ccross@android.com>
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Even if the card/emmc chip claims to support the Erase command,
the command won't work unless the controller is also configured
to support it.
Change-Id: Ic45fcd88dd3b3381677d907d31fa3a56bb697107
Signed-off-by: Ken Sumrall <ksumrall@android.com>
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Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Modified to use syscore_ops
Change-Id: Ic8a3a9559634eb3f1f0e4b40a2d8502d20d606d6
Signed-off-by: Benoit Goby <benoit@android.com>
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Enabling AHB prefetch on USB1, USB2, USB3 controllers,
to improve the USB transfer throughput.
originally work from Rakesh Bodla <rbodla@nvidia.com>
Change-Id: I3c45bb8e97ceffbf43229b9c3d9581a565b61187
Signed-off-by: James Wylder <james.wylder@motorola.com>
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The prefetcher fetches a total of 128 bytes, and then responding to
sequential reads with this prefetched data. To avoid coherency issues,
it discards the prefetched data if a non sequential read occurs.
Allocate dtd with 128 bytes boundary to make 2 consecutive dtd 128 bytes
apart.
Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Change-Id: I2adc02c2ac7901d0617b487cb498a34ec7a63e18
Signed-off-by: James Wylder <james.wylder@motorola.com>
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Submission from Jay Cheng <jacheng@nvidia.com>.
Change-Id: Ic92befe618adc7bdd12c35374fb3f855d7f6a515
Signed-off-by: Mike Corrigan <michael.corrigan@motorola.com>
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Need maximum memory bandwidth to support bi-directional
transfers on multiple endpoints.
Change-Id: Idfd74c62ea0438fca7b93e82a6032a28feeab830
Signed-off-by: James Wylder <james.wylder@motorola.com>
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Optimization that primarily addresses when cpu frequency
is low but a high memory bandwidth is needed.
Change-Id: I4f800c2368191c744aefd9f83eb96e4c108dbcc3
Signed-off-by: James Wylder <james.wylder@motorola.com>
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Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Change-Id: I8552e995ee5c124023dd7f5385e8ecca7a50eee8
Signed-off-by: James Wylder <james.wylder@motorola.com>
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Change-Id: Ib64190b01fc26bfb7fb8b9059afcc172d91e8da5
Signed-off-by: Sergey Kudakov <sergey.kudakov@motorola.com>
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Need cache maintenance on rw_handle to remove
display garbage issue which happens randomly.
Change-Id: I73606ae6551c0e75058e055f4a19e5f074a47004
Signed-off-by: Greg Roth <groth@nvidia.com>
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Commit 190f7b3ed5a597d2232e9047b50ac2d7613c3272 was an incorrect
merge, revert it.
Change-Id: I1c7e09fdbaad6637326facbc0ee06117bfb15e48
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Change-Id: I82497fc756552740836eaa2f608fecaea409cfeb
Signed-off-by: Michael I. Gold <gold@nvidia.com>
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Change-Id: Ied3851e0cb801f607499493f1e552f42daa97e6b
Signed-off-by: Ari Hirvonen <ahirvonen@nvidia.com>
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Multiple GetPortStatus requests can be made while the
USB bus is resuming. All requests must be handled
properly to prevent incorrect disconnect detection
during Resume and improper indentification of
Resume signaling as a remote wakeup event.
Change-Id: Ib07f83a2bab5699b2d95533d26d0a6bf541c697d
Signed-off-by: Nathan Connell <w14185@motorola.com>
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With the previous change in memory frequency (200 MHz
to 150 MHz) requests of 200 MHz will round up to full
speed. This negatively impacts current drain.
Change-Id: Ib67d8eaff57836a2f1756d84cce6533539911178
Signed-off-by: James Wylder <james.wylder@motorola.com>
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With the previous change in memory frequency (200 MHz
to 150 MHz) requests of 200 MHz will round up to full
speed. This negatively impacts current drain.
Change-Id: Iefdb3a50aff338b44daa8311218400e4b4586152
Signed-off-by: James Wylder <james.wylder@motorola.com>
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Removes changes to DC reset flow.
Change-Id: I491b6771c205bec7e19d4c661bb6d376ea8e25e4
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
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Change-Id: Ic69e022649bae71dd6d9a034c4da97e4197e5dc2
Signed-off-by: Colin Cross <ccross@android.com>
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