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2011-05-18arm: tegra: cardhu: set CPU EDP limitstegra-T30.ER5Varun Wadekar
Change-Id: I6282bbb63c34b8cc0d503cdd6eafe575fb78ef5f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31342 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: Tegra: Support to update edp zonesVarun Wadekar
Tegra cpu-freq driver will now recognize edp zones and cap the max cpu freq for that zone. The temperature monitoring driver will be giving inputs to cpu-freq on the current temperature which would be interpreted by the cpu-freq driver appropriately. Change-Id: I918eb31771aa7e1e1a5f25438edded727de6eb8c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31339 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18misc: nct1008: update edp zones for current temperatureVarun Wadekar
nct1008 will now use the ALERT# functionality to decide which edp zone to switch to. Change-Id: I1616a1d88e9f2f308a8b31935dbecec05ef54bca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31340 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18media: video: ov5650: synchronize sensors for stereoPrayas Mohanty
For stereo camera, it is important that both sensors should start sending data at the same time for them to be in sync. Add IOCTL (OV5650_IOCTL_SYNC_SENSORS), which user code can access to synchronize both sensors. bug 787214 bug 786928 Change-Id: I6bf34a8af3b7dd51150d5c0247b6787b824c1dae Reviewed-on: http://git-master/r/30005 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-18arm: tegra: sensors: synchronize cam A and cam BPrayas Mohanty
For stereo camera support, both cam A and cam B should start at the same point of time to be in sync. bug 787214 bug 786928 Change-Id: I417db0f8ff8c76130b76d8edb4e66189d6b92447 Reviewed-on: http://git-master/r/30004 Tested-by: Prayas Mohanty <pmohanty@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-18tegra: iovm: Limit forced Carveout-to-IOVM conversion to tegra 3Hiro Sugawara
Bug 828027 Change-Id: I890e0481be5aade59bc68510c9fe5929bb3b64a2 Reviewed-on: http://git-master/r/31902 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18arm: tegra: Fix suspend/resume hangVinod G
Spdif driver resume was causing issue on resume stage. Change-Id: I25c0d52889c4ff1b029053f744bee32023cf1a8f Reviewed-on: http://git-master/r/32070 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18ARM: tegra: power: Enable Tegra3 core DVFSAlex Frid
Enable Tegra3 core DVFS with default EDP limit set to 1.2V. Bug 812738 Bug 826200 Change-Id: If1e9f431729d0dbe6e8c89d9d8b9d5f9d2e8a2bf Reviewed-on: http://git-master/r/31254 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: tegra: baseband: Add PH450 modem init and reset functionsSteve Lin
Add PH450 modem init and reset functions for Tegra Enterprise. Bug 800301 Change-Id: I7068fa87118c2388badb664da3d1a83a3eb49dae Reviewed-on: http://git-master/r/30920 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18arm: tegra: Set 48Khz default samplerateVinod G
bug 804696 Setting 48Khz as default samplerate as DAM SRC has issue with 44.1Khz Change-Id: I57119564c170a5d379df8917b82f6ea8992cc138 Reviewed-on: http://git-master/r/31269 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: tegra: clock: Set Tegra3 CPU maximum rate to 1.3GHzAlex Frid
Set Tegra3 CPU maximum rate to 1.3MHz. Effective only on boards with EDP table. Otherwise, the default EDP limit keeps rate below 1GHz. Change-Id: I8221cf037cc957b45cafc7f59c76d3cf25816228 Reviewed-on: http://git-master/r/31617 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-18ARM: tegra: power: Enable Tegra3 CPU EDP by defaultAlex Frid
Change-Id: I62ad3b3b7e0b4feba223c0dfe5792194aea6e4cd Reviewed-on: http://git-master/r/31616 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-18arm: tegra: power: Fix build break when CONFIG_PM disabledScott Williams
The code to select LP0/LP1 low-power mode via a sysfs node does not compile if CONFIG_PM is disabled. This fixes that error. Change-Id: If166759bd89f03335bca529cbe50a32420f802f6 Reviewed-on: http://git-master/r/31903 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-18ARM: tegra: Check if the cpu already booted or notvjagadish
Check the CPU is ever booted before entering into powerup status confirmation loop. BUG 824307 Change-Id: I474d0536b00e84967a240037d2ed984a889dd2e0 Reviewed-on: http://git-master/r/30679 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com> Tested-by: Venkata Jagadish <vjagadish@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18arm: tegra: cardhu: Adding board entry for tps6236xLaxman Dewangan
Adding platform data entry for the tps6236x device and registering this device if board info has sku with bit0 as 1. bug 821295 Change-Id: I18618ef75eca66a1f699c003c787dcb1f06e7659 Reviewed-on: http://git-master/r/31388 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-05-18arm: tegra: devices: Adding device details for tegra kbcAlok Chauhan
Adding device details for the tegra based kbc driver. Bug 827020 Change-Id: I47b150fc97f97ce91c1de569aec067ad2e5f0660 Reviewed-on: http://git-master/r/31725 Reviewed-by: Alok Chauhan <alokc@nvidia.com> Tested-by: Alok Chauhan <alokc@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-05-18ARM: Tegra: Enterprise: Fix Touchscreen gpios.Alex Odorovic
Fixes the issue with touchscreen feeling sluggish and not detecting all events. Bug 824702 Change-Id: I26f9a9d2192e445c79fe1830adac3dfc4e04ba4e Reviewed-on: http://git-master/r/31614 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com>
2011-05-18media: tegra: avp: check for NULL on some APIsJon Mayo
clk and nvmap APIs can return ERR_PTR or NULL. also fixed some printf warnings. Bug 827548 Change-Id: Iae3eea2d3d7130bcaa4dadb126661908dcca1e96 Reviewed-on: http://git-master/r/31750 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18ARM: tegra: touch: Add SKU for enterpriseTom Cherry
Change-Id: I60c16f4293e828d2960db734759184445d557555 Reviewed-on: http://git-master/r/31445 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Robert R Collins <rcollins@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-18rtc: tps6591x: enabling backup battery chargingvenu byravarasu
With this change: 1. Enabled backup battery charging 2. Setting RTC default time, if it is not set previously. bug 796507 Change-Id: Idffb99f24718cd8b15f38b6ca8109969ef47be81 Reviewed-on: http://git-master/r/31522 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18power: battery: bq27x00: add "health" propertysyed rafiuddin
Addition of Health property which informs the health of the battery like good, dead and over charge. Bug 786669 Change-Id: I4ed3684ec4e777d110f3c5bd2a062ac5be22c6e2 Reviewed-on: http://git-master/r/30505 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18Merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Change-Id: Ib689952b7ac2e486761787b3eee08afa5df92683
2011-05-17usb: tegra: fix tegra ehci setup sequenceSteve Lin
Fix tegra ehci setup sequence according to EHCI spec. - move ehci_reset after ehci_halt - avoid redundant ehci_reset after ehci_run. ehci_reset has a side effect to cause phy reset for certain phy interface. Bug 800301 Change-Id: I9a798de1b6361742ce759e44d141673c0bd328b3 Reviewed-on: http://git-master/r/31432 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17ARM: config: cardhu: Enabling REGULATOR_TPS6236XLaxman Dewangan
Enabling the config variable CONFIG_REGULATOR_TPS6236X to support DC-DC converter device TPS6236x. bug 821295 Change-Id: Ibbab5f44d3d29517b4e5928a7a585887925afa22 Reviewed-on: http://git-master/r/31387 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17ARM: tegra: cardhu: remove avdd_dsi_csi regulator codePritesh Raithatha
remove avdd_dsi_csi regulator code as it is already handled by tegra_camera.c Bug 826043 Change-Id: I0e97268c4381a27d9d2b499d7f332cc21314a045 Reviewed-on: http://git-master/r/31191 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17arm: tegra: Add audio manager common interfaces.Vinod G
Audio manager common interfaces are defined to be called from SOC code. Audio manager will make the decision which all modules to be controlled based on use case connection. Correction added to the speaker amp and i2c gpio is provided for controlling the speaker amplification. Removed the speakersetting call. Change-Id: Id2c7f953fc78f66bee2e1d4773e03548de0ba5b4 Reviewed-on: http://git-master/r/30891 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17arm: config: Removing DUMMY REGULATOR from cardhu/ventana/enterpriseLaxman Dewangan
Removing the config variable REGULATOR_DUMMY from cardhu, ventana and enterprise as these boards have actual regulator. Change-Id: Ia39478b6adf887ca247cbf34bd8618b8ad463239 Reviewed-on: http://git-master/r/31136 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17ARM: tegra: dc: lower hdmi clock before set rateJon Mayo
choose a higher clock divider on hdmi before switching clock parents. This prevents hdmi from exceeding its DVFS clock limits. Change-Id: I09c23498bf6450cf19e91accb788715582c3befb Reviewed-on: http://git-master/r/31605 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com>
2011-05-17ARM: tegra: power: Add suspend index to cpufreq tableAlex Frid
Change-Id: I7bbe018f3786b9683cc9d4189fdcaadb9098f3f1 Reviewed-on: http://git-master/r/31456 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17ARM: tegra: power: Update Tegra3 CPU DVFS tableAlex Frid
Change-Id: I3164bb2d86619b891a647b5e6550470c509eb403 Reviewed-on: http://git-master/r/31308 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-17crypto: se: tegra: Support for Security EngineKasoju Mallikarjun
Added support for Security Engine. Following HW features are supported: CBC,ECB,CTR,OFB,SHA1,SHA224,SHA384,SHA512 and AES-CMAC Change-Id: Ic45c29add689f55be68966d333d1cb7cdb378353 Reviewed-on: http://git-master/r/29950 Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-17ARM: tegra: power LP0/LP1 selection via sysfsKaran Jhavar
Select LP0/LP1 on runtime using sysfs node /sys/power/suspend/type. Valid selctions/commands are: 1. lp0 2. lp1 3. lp2 Change-Id: I335a8845dbfed7539ae4bf8aee3ba3b97ecb3db3 Reviewed-on: http://git-master/r/30081 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-17ARM: tegra: clock: Enable clock while setting rate/parentAlex Frid
When clock configuration (source mux, divider value) changes, the new control register setting does not take effect if clock is disabled. Later, when the clock is enabled it would run for several cycles on the old configuration before switching to the new one. This h/w behavior creates two problems: - since dvfs takes into account only new (enabled) rate, the module can be over-clocked during initial phase of the clock switch - since parent clock refcount is updated when the mux register was written, the parent clock maybe disabled by the time of actual switch and h/w would not be able to complete switch at all To avoid described problems clock is now always enabled while setting the new rate/parent (and disabled afterwards to keep refcount intact). Change-Id: I9bda56a2a98c9f3678715da1e1b8fe78874fb71e Reviewed-on: http://git-master/r/31640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17ARM: 6355/1: hw-breakpoint: add mechanism for hooking into prefetch abortsWill Deacon
On ARM processors with hardware breakpoint and watchpoint support, triggering these events results in a debug exception. These manifest as prefetch and data aborts respectively. arch/arm/mm/fault.c already provides hook_fault_code for hooking into data aborts dependent on the DFSR. This patch adds a new function, hook_ifault_code for hooking into prefetch aborts in the same manner. This is picked from following git repository: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-2.6.38.y.git Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: S. Karthikeyan <informkarthik@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 3a4b5dca53aecb16db9e007d782b2d1e757e941a) Change-Id: Ic278bad0e3bb95f504e46b216a8d14fd61fbc4a5 Reviewed-on: http://git-master/r/31574 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17mach-types: Official tegra_enterprise machine numDan Willemsen
http://www.arm.linux.org.uk/developer/machines/list.php?id=3512 Change-Id: I432bd8512025c6f3ff312b8e120df37c68aa1153 Reviewed-on: http://git-master/r/31409 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-17regulator: tps6236x: Adding driverLaxman Dewangan
Adding regulator driver for the device TPS6236x. bug 821295 Change-Id: Ifed4044db33fa6867248fae000bddf6239cb9685 Reviewed-on: http://git-master/r/31386 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-05-15media: tegra: avp: Allocate IOVMM first for AVPKaz Fukuoka
bug 827505 Change-Id: If6d4fd137b72c3a08bf8fb1094d8dd31ab361f1c Reviewed-on: http://git-master/r/31633 Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Frank Thomas Bourgeois <fbourgeois@nvidia.com>
2011-05-13(WORKAROUND) Keep AVP kernel aliveKaz Fukuoka
- Avoid shutdown AVP kernel - This is a workadound for bug 827353 bug 827353 Change-Id: I7a8889bf190f91792c90a84fc69d5b190b8de73f Reviewed-on: http://git-master/r/31576 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra: power: PM269: Add GPIO_REGPradeep Goudagunta
Adding GPIO_REG for power rails of PM269 board. Bug 823160 Change-Id: Idbb889420e033780900b1b1b700637017640414e Reviewed-on: http://git-master/r/30366 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra : power: Set power rails SATA & PCIE off by defaultKaran Jhavar
Setting SATA & PCIE power rails (ldo1 & ldo2) off by default since they are not enabled on Cardhu. Bug 793780, 790141 Change-Id: If905f156b99314271874536d61fe384715f2412a Reviewed-on: http://git-master/r/31292 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra: enterprise: use UART4 as debug uartPradeep Goudagunta
Enable UART4 as debug uart. Bug 814271 Bug 822432 Change-Id: I73f01191d5f1e0fe979eb804028e0a7956eb93df Reviewed-on: http://git-master/r/30513 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13arm: tegra: nvmap: Forcing to convert CarveOut requests to IOVMHiro Sugawara
Adding a build time CONFIG option to enable forcing of conversion of non-IRAM CarveOut memory allocation requests to IOVM requests. Default is "y" to force the conversion. Each forced conversion is reported to console. Allocation alignments larger than page size for IOVM are enabled. Single page CarveOut allocations are converted to system memory. CarveOut memory reservation has been removed for aruba, cardhu, and enterprise. Change-Id: I3a598431d15b92ce853b3bec97be4b583d021264 Reviewed-on: http://git-master/r/29849 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13video: tegra: dsi: Adjusted the values of packet sequence registers.Kevin Huang
Changed the values of packet sequence registers for DSI burst video mode. Change-Id: I70188ed3c8fff094862a89377457751fd0d4382c Reviewed-on: http://git-master/r/31080 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: defconfig: Cardhu: Enabling ARM erratasvenu byravarasu
Enabling arm erratas 743622, 751472 and 752520 for cardhu Change-Id: I0fb985a6bc78160683924875f14b2afbecba0604 Reviewed-on: http://git-master/r/31473 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13media: tegra: avp: Use SMMU to load AVP kernelKaz Fukuoka
- Use nvrm_avp_e0000000.bin is for Tegra3 A01 - Use nvrm_avp_00001000.bin is for Tegra3 A02 and later bug 765965 Change-Id: I9bc28b122bd1b0cd2c1ece3bc681550de5912229 Reviewed-on: http://git-master/r/31202 Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2011-05-13media: tegra_camera: add support for regulator avdd_dsi_csiPritesh Raithatha
Bug 826043 Change-Id: I3d78f7941d54038f12f587400c899aa145c63122 Reviewed-on: http://git-master/r/31369 Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-05-13ARM: tegra: power: Limit Tegra3 CPU nominal voltageAlex Frid
Limit Tegra3 CPU nominal voltage in case when maximum rate specified in the clock tree is below maximum rate in CPU dvfs table. Change-Id: Ie7b47a1f482f3c33da19e530b05663683bd807a1 Reviewed-on: http://git-master/r/31307 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-13ARM: tegra: clock: Support Tegra3 CPU clock fractional dividerAlex Frid
Added support for Tegra3 CPU super-clock fractional 7.1 divider: use it to adjust CPU rate, when super-clock parent is fixed rate PLL (for other parent PLLs with adjustable frequency set divider 1:1). Bug 821438 Change-Id: Ib8342330d103beb535af4d74ea51c46b9e25dc30 Reviewed-on: http://git-master/r/31219 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-13arch: arm: tegra: Bringup Enterprise touchscreen.Alex Odorovic
Bug 824702 Change-Id: I9eb48dee19b3d9e37843a83ee28e9ffb008ddd7e Reviewed-on: http://git-master/r/31077 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Aleksandar Odorovic <aodorovic@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-12 21:24:03 +0000