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This patch adds SAI script support to imx-sdma.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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The new Solo X has more requirements for SDMA events. So it creates a event mux
to remap most of event numbers in GPR (General Purpose Register). If we want to
use SDMA support for those module who do not get the even number as default, we
need to configure GPR first.
Thus this patch adds this support of GPR event remapping configuration to the
SDMA driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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This patch update fec devicetree binding doc that add Optional
properties "fsl,num-tx-queues" and "fsl,num-rx-queues".
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This adds support for specifying the phy to be used with the fec in the
devicetree using the standard phy-handle property and also supports
fixed-link.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Some Ethernet MACs have a "fixed link", and are not connected to a
normal MDIO-managed PHY device. For those situations, a Device Tree
binding allows to describe a "fixed link" using a special PHY node.
This patch adds:
* A documentation for the fixed PHY Device Tree binding.
* An of_phy_is_fixed_link() function that an Ethernet driver can call
on its PHY phandle to find out whether it's a fixed link PHY or
not. It should typically be used to know if
of_phy_register_fixed_link() should be called.
* An of_phy_register_fixed_link() function that instantiates the
fixed PHY into the PHY subsystem, so that when the driver calls
of_phy_connect(), the PHY device associated to the OF node will be
found.
These two additional functions also support the old fixed-link Device
Tree binding used on PowerPC platforms, so that ultimately, the
network device drivers for those platforms could be converted to use
of_phy_is_fixed_link() and of_phy_register_fixed_link() instead of
of_phy_connect_fixed_link(), while keeping compatibility with their
respective Device Tree bindings.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller.
For TX, only one dedicated tx buffer is used for sending data.
For RX, RXFIFO 0 is used for receiving data to avoid overflow.
Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO.
Due to the message ram can be shared by multi m_can instances
and the fifo element is configurable which is SoC dependant,
the design is to parse the message ram related configuration data from device
tree rather than hardcode define it in driver which can make the message
ram using fully transparently to M_CAN controller driver,
then we can gain better driver maintainability and future features upgrade.
M_CAN also supports CANFD protocol features like data payload up to 64 bytes
and bitrate switch at runtime, however, this patch still does not add the
support for these features.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit a0dd1cb47d5792902eb380b70af292b4ba64d4b0)
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Starting from IMX6, the flexcan stop mode control bits is SoC specific,
move it out of IP driver and parse it from devicetree.
It's good from maintain perspective and can avoid adding too many SoC
specifi bits in driver but with no IP changes when the IMX SoC series
keep growing.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 97b99b59c9f09d58ea35f3c0cf58665c20f2e292)
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If wakeup is enabled, enter stop mode, else enter disabled mode.
Self wake can only work on stop mode.
For imx6q, the stop request has to be mannually assert on
IOMUX GPR13[28:29] register, we use syscon to control that bit.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 7f8ef8eeb2bd93d75eb4c970bcaabcfd499d348d)
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Add gpios for tranceiver control.
Before we have a common tranceiver binding, we use this way first.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit f50c22920fc26c6895afd3795dc1200235ca8cfd)
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The hip04 SoC of hisilicon has an AHCI compliant SATA controller,
and it is compliant with the ahci 1.3 and sata 3.0 specification.
There is a wrong bit in HOST_CAP of hip04 sata controller, which
enable unsupported feature of FBS, use AHCI_HFLAG_NO_FBS hflag to
disable it.
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit a1a205df6ee224f62c6d21cedebcb723db17fe0d)
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The Marvell Armada 380 SoC includes two AHCI compatible
interfaces. However, like all DMA-capable Marvell interface, they
require special handling to configure MBus windows. Therefore, this
commit adds a new ahci_mvebu driver, which relies on the
libahci_platform.c code recently introduced.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit a3464ed2f14d19ba923930f7c0c284499d64eb5b)
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The ahci-platform.txt Device Tree binding documentation is gaining a
growing number of compatible strings, and it will gain one more with
the addition of the Marvell Armada 380 AHCI support. It is therefore
time to reformat this list into a proper bullet list, and more
importantly order it alphabetically;
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 5799d6d4cf86c11503aee909a1ec555453c7f22a)
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The ahci_platform driver supports "snps,dwc-ahci".
Add this to the DT binding information.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 42a7f53ba0f2baa2ea23cd830511cea7f8612dd2)
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This avoids the ugliness of creating a nested platform device from probe.
While moving it around anyways, move the mk6q phy init code from probe
to imx_sata_enable, as the phy needs to be re-initialized on resume too,
otherwise the drive won't be recognized after resume.
Tested on a wandboard i.mx6 quad.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 90870d79d4f28711610dd2e72d8fa616c922d110)
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This patch adds support for the ahci sata controler found on Allwinner A10
and A20 SoCs to the ahci_platform driver.
Orignally written by Olliver Schinagl using the approach of having a platform
device which probe method creates a new child platform device which gets
driven by ahci_platform.c, as done by ahci_imx.c .
Refactored by Hans de Goede to add most of the non sunxi specific functionality
to ahci_platform.c and use a platform_data pointer from of_device_id for the
sunxi specific bits.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit c5754b5220f01e8722799d35c04a76e82c62d7d8)
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 4b3e603a298db26c6c37e8b08adcce24d014df13)
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The allwinner-sun4i AHCI controller needs 2 clocks to be enabled and the
imx AHCI controller needs 3 clocks to be enabled.
tj: Minor comment formatting updates.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 156c5887948cd191417f18026aab9ce26e5a95da)
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support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit f2518480c7b744296a5587990a54e3a284d932b8)
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Add EETI egalax touch screen for i.MX6sx-sdb board in the
new branch 3.14.y.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
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Some gpio-leds need retain the state even in suspend, such as charger led.
But this property missed in devicetree, add it.
(cooloney@gmail.com: fold DT binding updates into this patch)
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Bryan Wu <cooloney@gmail.com>
(cherry picked from commit 4270a78d23eece0b25a13bff1e71d114ec547de4)
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Port si476x machine dirver for i.MX series SoC and binding doc from imx_3.10.y
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Port the cs42888 machine driver from imx_3.10.y and do update according to
new esai driver and asrc driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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There's a missing script for hdmi audio support in current sdma driver,
thus add it.
This HDMI script doesn't use bd to copy memory like a normal one does
but only to update the memory address for HDMI internal AHB DMA and
then trigger its procedure automatically.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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User can specify clocks in devicetree which is used for accessing the registers
in this regmap.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit da7e2a7123dfab6e7ad23e4db072ef4611a2b6cd)
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This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[shawn.guo: cherry-pick commit 86be408bfbd8 from upstream]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links such as ESAI<->CS42888 and SSI<->WM8962 and SAI. It converts the
original sample rate to a common rate supported by Back Ends for playback while
converts the common rate of Back Ends to a desired rate for capture. It has 3
pairs to support three different substreams within totally 10 channels.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Reviewed-by: Varka Bhadram <varkabhadram@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 3117bb3109dc223e186302f5dc8ce9ed04adca90)
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Shared Peripheral ASRC, running on SPBA, needs to use shp sciprts for
DMA transfer. So this patch just adds a new DMATYPE for it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from commit f892afb07eeecf575179c4747952644a82a92a36)
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The patch updates the document by adding more information to describe the
DT proporties used by the Freescale Quadspi driver and the childs nodes.
For the child node for SPI NOR flash, we add the required property
("spi-max-frequency"), and refer to spi-nor-flash.txt for the optional
properties.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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We need a DT property to store the dummy cycles for DDR Quad read.
This is a common feature for the SPI NOR flash, such as Spansion and Micron
chips.
Add this file to describe this specific SPI NOR flash features which will
be referred by the SPI NOR flash drivers.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So this patch adds these clocks and their clock controls to the driver.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit ca3e35c7a37cb59b12a1839d03c621cf8fa9a3d9)
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The next coming i.MX6 Solo X SoC also contains SAI module while we use
imp_pcm_init() for i.MX platform.
So this patch adds one compatible route for imx6sx and updates the DT
doc accordingly.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit c754064453e0d48043bd6a111f5c1f8ef1b75f7e)
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For most platforms, the CPU and ESAI device is in the same endianess
mode. While for the LS1 platform, the CPU is in LE mode and the ESAI
is in BE mode.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit eaba603fc7c6281908c316d9e58de688943d58be)
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For most platforms, the CPU and SPDIF device is in the same endianess
mode. While for the LS1 platform, the CPU is in LE mode and the SPDIF
is in BE mode.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 86f28d76435b619bd0bc5f6fde2803a5bc27ca24)
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This patch adds support for the Cirrus Logic CS42448/CS42888 Audio CODEC that
has six/four 24-bit AD and eight 24-bit DA converters.
[ CS42448/CS42888 supports both I2C and SPI control ports. As initial patch,
this patch only adds the support for I2C. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Acked-by: Paul Handrigan <Paul.Handrigan@cirrus.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 0c516b4ff85c0be4cee5b30ae59c9565c7f91a00)
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Add clock driver for i.MX6 SoloX SoC.
Signed-off-by: Anson Huang <b20788@freescale.com>
[shawn.guo: cherry-pick commit d55135689019 from upstream]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[shawn.guo: cherry-pick commit 2cc140fe3607 from upstream]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch adds the binding file for Freescale QuadSPI driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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This patch adds the document for the SPI NOR framework.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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It's pretty common that on some reference design or validation boards,
one pin could be used by two devices on board, and the pin route is
controlled by a GPIO. So to assert the pin for given device, not only
the pinmux controller in SoC needs to be set up properly but also the
GPIO needs to be pulled up/down.
The patch adds support of a device tree property "pinctrl-assert-gpios"
under client device node. It plays pretty much like a board level pin
multiplexer, and steers the pin route by controlling the GPIOs. When
client device has the property represent in its node, pinctrl device
tree mapping function will firstly pull up/down the GPIOs to assert the
pins for the device at board level.
[shawn.guo: cherry-pick commit e5a718edab82 from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
[shawn.guo: cherry-pick commit 27e3604c82cb from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
drivers/reset/Makefile
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The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: http://thread.gmane.org/gmane.linux.drivers.devicetree/64973]
[shawn.guo: update property name to be 'power-domains']
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This patch introduces generic code to perform power domain look-up using
device tree and automatically bind devices to their power domains.
Generic device tree binding is introduced to specify power domains of
devices in their device tree nodes.
Backwards compatibility with legacy Samsung-specific power domain
bindings is provided, but for now the new code is not compiled when
CONFIG_ARCH_EXYNOS is selected to avoid collision with legacy code. This
will change as soon as Exynos power domain code gets converted to use
the generic framework in further patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Mark Brown <broonie@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
[on i.MX6 GK802]
Tested-by: Philipp Zabel <philipp.zabel@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[shawn.guo: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/31029]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Instead of using enum for clock ID, let's switch imx6qdl clock driver to
use macro. In this case, device tree can reuse these macros to improve
readability.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick from community IMX tree]
Conflicts:
arch/arm/mach-imx/clk-imx6q.c
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The esai_ahb clock is derived from ahb and used to provide ESAI the
capability of register accessing and FSYS clock source for I2S clocks
dividing. The gate bits of this esai_ahb clock are shared with the
esai clock -- the baud clock, so we need to call imx_clk_gate2_shared()
for these two clocks.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
[shawn.guo: cherry-pick commit 886cda418b28 from upstream]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Forward imx_3.10_y mxc video drivers to 3.14 kernel.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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re-use the upstreaming mxsfb.c code.
- add the lcdif axi clock for register and dram access
- set the lcdif pix's parent as pll5_video to get most accurate pix clock
- add binding doc for lcdif dts
Signed-off-by: Robby Cai <R63905@freescale.com>
[shawn.guo: cherry-pick commit 423273b4437f from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
drivers/video/mxsfb.c
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Add support to drop DDR and AHB frequency to 24MHz in
system IDLE state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
[shawn.guo: cherry-pick commit 7091e3d1c771 from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit d9c130328d2e from upstream]
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Add "fsl,imx6q-usbphy" for imx6dq and imx6dl, add
"fsl,imx6sl-usbphy" for imx6sl, and "fsl,imx23-usbphy"
is still a fallback for other strings.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 14de8c3a62b9 from upstream]
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