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2020-02-12ARM: dts: imx6q: follow addition of sata_ext clkMax Krummenacher
Commit f014b5b3b3ab added an additional clock to ahci_imx.c used on i.MX8. Add a dummy clock to imx6q.dtsi so that i.MX6 which doesn't need the clock the driver keeps working. Fixes: [ 2.053942] ahci-imx 2200000.sata: can't get sata_ext clock. [ 2.053962] ahci-imx: probe of 2200000.sata failed with error -2 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-04-10MLK-21416: ARM: dts: imx6q: correct SDMA script for ecspi5Robin Gong
Revert below upstreaming patch which broke SPI5 dma since ram script used for ecspi to workaroud ERR009165 and spi driver changed to XCH mode instead of SMC. Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core" This reverts commit df07101e1c4a29e820df02f9989a066988b160e6. Signed-off-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit 443e65efad14aa3fe1c99ead8fac10ec856b7e44)
2019-02-12MLK-18036-1 Add "fsl,optee-lpm-sram" node for optee os power management.Clement Faure
This node will be used by the OCRAM driver in optee to: * Get the OCRAM start address for power management in optee. * Add an entry that will overwrite ocrams nodes and dynamically reduce the OCRAM available for mmio-sram in Linux. That way we do not touch the legacy Linux boot and remove the dedicated optee device tree. Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-02-12MLK-18121: ARM: dts: imx6qdl: Fix gpu power-domains refLeonard Crestez
Upstream refactored GPC power domains to have a nested pgc node, this means that the pu power domain needs to be referenced differently. This fixes warnings like these: OF: /soc/gpu@00130000: could not get #power-domain-cells for /soc/aips-bus@02000000/gpc@020dc000 This warning probably also means that GPU power management is not done correctly. Old bindings are still used on imx6s* Fixes: 0a9a9a732f88 ("MGS-3705-1 gpu: dts: enable gpu devices for imx6") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Xianzhong <xianzhong.li@nxp.com>
2019-02-12MGS-3705-1 gpu: dts: enable gpu devices for imx6Xianzhong
set GPU baseAddress with 256M on IMX6Q and iMX6QP, add reserved cma in DTB to support different size, the default cma size is 320M on all imx6 boards. integrated patches from imx_4.9.y: 1.MGS-955 GPU:Integrate GPU module commit: 73183c14a20d4f1d02317f80db3d90b3be1546fc 2.MGS-1211 gpu: add GPU for 6sl,6sx,6dl commit: 80a8994c47cbb97fb31ef0efab92ddb29002448e 3.MGS-1087 gpu: Move the GPU reserved memory to DTS file commit: ea0111da6892b52c790da607a3d91140d1ebf936 4.MGS-2540 [#ccc] Need set baseAddress with RAM start address on IMX6Q commit: de838d99d9264884cbaaa601ab323a70b62634d9 Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2019-02-12MLK-13119-1 ARM: dts: imx6q: add vpu clock for cpu frequencyAnson Huang
When VPU is running at 396MHz, need to increase VDDSOC_CAP voltage for all cpu set-points, so add vpu clock node for cpufreq driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12023-1: ARM: dts: imx: imx6q add busfreq device node labelAdrian Alonso
Add busfreq device node label to allow override busfreq properties on machine device tree descriptor Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit fd8faeb7a40fc2f9fb331d6ca6a60b64c95d7ee6)
2019-02-12MLK-11508-5: dts: Add imx v4l2 capture driverSandor Yu
Add imx v4l2 capture driver. Signed-off-by: Sandor Yu <R01008@freescale.com>
2019-02-12MLK-11431-3: ARM: DTS: imx6 Add IPU and display supportSandor Yu
Add IPU, HDMI and LDB support. Signed-off-by: Sandor Yu <R01008@freescale.com>
2019-02-12MLK-11497-1 ARM: dts: add busfreq support for imx6q/dlAnson Huang
Add busfreq support for i.MX6Q/DL. Signed-off-by: Anson Huang <b20788@freescale.com>
2019-02-12MLK-11343-03 ARM: dts: imx: add clocks in cpu modeBai Ping
Add pll1, pll1_bypass and pll1_bypass_src clock reference define in dts file. Signed-off-by: Bai Ping <b51503@freescale.com>
2019-02-12MLK-11322-01 ARM: dts: imx: add ocram node used for lpm codeBai Ping
Reserve iram space for low power code. The first 16KB space is used for suspend/resume and cpuidle. Another 4KB space is for busfreq code. for i.MX6SX, it has a dedicated ocram space start at 0x8f8000 for low power code. Signed-off-by: Bai Ping <b51503@freescale.com>
2018-07-08ARM: dts: imx6q: Use correct SDMA script for SPI5 coreSean Nyekjaer
commit df07101e1c4a29e820df02f9989a066988b160e6 upstream. According to the reference manual the shp_2_mcu / mcu_2_shp scripts must be used for devices connected through the SPBA. This fixes an issue we saw with DMA transfers. Sometimes the SPI controller RX FIFO was not empty after a DMA transfer and the driver got stuck in the next PIO transfer when it read one word more than expected. commit dd4b487b32a35 ("ARM: dts: imx6: Use correct SDMA script for SPI cores") is fixing the same issue but only for SPI1 - 4. Fixes: 677940258dd8e ("ARM: dts: imx6q: enable dma for ecspi5") Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-14ARM: dts: imx6qdl: add capture-subsystem deviceSteve Longerbeam
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl: Add video multiplexers, mipi_csi, and their connectionsPhilipp Zabel
This patch adds the device tree graph connecting the input multiplexers to the IPU CSIs and the MIPI-CSI2 gasket on i.MX6. The MIPI_IPU multiplexers are added as children of the iomuxc-gpr syscon device node. On i.MX6Q/D two two-input multiplexers in front of IPU1 CSI0 and IPU2 CSI1 allow to select between CSI0/1 parallel input pads and the MIPI CSI-2 virtual channels 0/3. On i.MX6DL/S two five-input multiplexers in front of IPU1 CSI0 and IPU1 CSI1 allow to select between CSI0/1 parallel input pads and any of the four MIPI CSI-2 virtual channels. Changes from Steve Longerbeam: - Removed some dangling/unused endpoints (ipu2_csi0_from_csi2ipu) - Renamed the mipi virtual channel endpoint labels, from "mipi_csiX_..." to "mipi_vcX...". - Added input endpoint anchors to the video muxes for the connections from parallel sensors. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl: add multiplexer controlsPhilipp Zabel
The IOMUXC General Purpose Register space contains various bitfields that control video bus multiplexers. Describe them using a mmio-mux node. The placement of the IPU CSI video mux controls differs between i.MX6D/Q and i.MX6S/DL. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15ARM: dts: imx6: adopt DT to new GPC bindingLucas Stach
Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-09-09ARM: dts: add gpio-ranges property to iMX GPIO controllersVladimir Zapolskiy
To establish a connection between GPIO controllers and pin multiplexor controller add gpio-ranges properties to all GPIO controllers found on iMX50, iMX6Q/D, iMX6DL/S, iMX6SL, iMX6SX, iMX6UL and iMX7D/S SoCs. The change was done after human parsing of output from % gawk -n '{ sub(/.*__/, ""); if ($1 ~ "^GPIO") print $1, $2/4}' imxXX-pinfunc.h | sort -n Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-26ARM: dts: imx6: fix dtc warnings for ipu endpointsJoshua Clayton
When compiled with "W=1", dtc complains: e.g. "Warning (unit_address_vs_reg): Node /soc/ipu@02800000/port@2/endpoint@0 has a unit name, but no reg property" Endpoint nodes don't have a reg property, and the addresses in their node names are ordinals without any special meaning so remove them and swap them for semantic node names. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-29ARM: dts: imx6q: add missing links between ipu2 and mipi dsiPhilipp Zabel
The backlinks are already there since commit 4520e69238b3 ("ARM: dts: imx6qdl: Add IPU DI ports and endpoints, move imx-drm node to dtsi") and were moved by commit 70c2652c6c5b ("ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node"), but the links from IPU2 DI0/1 to the MIPI DSI mux are missing. Fix this. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-29ARM: dts: imx: Add basic dts support for imx6qp SOCBai Ping
The i.MX6Quad Plus processor is an high performance SOC of i.MX6 family. It has enhanced graphics performance and increased overall memory bandwidth compared to i.MX6Q. Most of the design are same as i.MX6Quad/Dual, so code for i.MX6Quad can be resued by this chip. The revision number is identied as i.MX6Q Rev2.0, but actually it is a new chip, as we did many change to the overall architecture. This patch adds basic dtsi file support for the new i.MX6Quad Plus processor. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-01-07ARM: dts: imx6q: clean up unused ipu2grpShawn Guo
The pinctrl group ipu2grp is a leftover from the previous iomuxc DT cleanup. It's not used by anyone now. More importantly, it's getting in the way of saving the unnecessary pinfunc container node from the board dts files that include imx6q.dtsi. Let's clean it up. Signed-off-by: Shawn Guo <shawnguo@kernel.org> Tested-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-12-22ARM: dts: imx6: add Vivante GPU nodesLucas Stach
This adds the device nodes for 2D, 3D and VG GPU cores. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-12-22ARM: dts: imx6qdl: add IPU aliasesPhilipp Zabel
This allows for consistent numbering of the IPU output and input ports. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-03-30ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' nodeLiu Ying
The MIPI DSI node contains some ports which represent possible DRM CRTCs it can connect with. Each port has a 'reg' property embedded. This property will be wrongly interpretted by the MIPI DSI bus driver, because the driver will take each subnode which contains a 'reg' property as a DSI peripheral device. This patch moves the existing MIPI DSI ports into a new 'ports' node so that the MIPI DSI bus driver may distinguish its DSI peripheral device(s) from the existing ports. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-20ARM: dts: imx6q: enable dma for ecspi5Anton Bondarenko
Enable dma support for ecspi5 controller Signed-off-by: Anton Bondarenko <anton_bondarenko@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-05ARM: dts: imx6q: update cpufreq volt/freq tableAnson Huang
According to latest i.MX6Q datasheet Rev. 3, 02/2014, the latest cpufreq volt/freq table is as below: LDO enabled/bypassed(min value): 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 0.925V, VDDSOC: 1.150V; the 792MHz setpoint's VDDARM min voltage is updated from 1.125V to 1.150V, adding 25mV to cover board IR drop, 1.175V is the right voltage we should use. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: dts: imx6qdl: Enable CODA960 VPUPhilipp Zabel
This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt. Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-07-18ARM: dts: imx6qdl: use DT macro for clock IDShawn Guo
Switch to use DT macro for clock ID, so that device tree source is more readable. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18ARM: dts: imx6qdl: Add CSI device tree port nodes for IPU1 and IPU2Philipp Zabel
This patch adds CSI subnodes for IPU1 and IPU2 that will contain ports and endpoints connecting to external elements in the video pipeline. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds
Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ...
2014-03-07ARM: dts: imx6qdl: Add IPU DI ports and endpoints, move imx-drm node to dtsiPhilipp Zabel
This patch connects IPU and display encoder (HDMI, LVDS, MIPI) device tree nodes, as well as parallel displays on the DISP0 and DISP1 outputs, using the OF graph bindings described in Documentation/devicetree/bindings/media/video-interfaces.txt The IPU ports correspond to the two display interfaces. The order of endpoints in the ports is arbitrary. Each encoder with an associated input multiplexer has multiple input ports in the device tree. The order and reg property of the ports must correspond to the multiplexer input order. Since the imx-drm node now only needs to contain links to the display interfaces, it can be moved to the SoC dtsi level. At the board level, only connections between the display interface ports and encoders or panels have to be added. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-02-24imx-drm: update and fix imx6 DT descriptions for v3 HDMI driverRussell King
Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-02-24imx-drm: add imx6 DT configuration for HDMIRussell King
Extracted from another patch by Fabio Estevam, this adds the DT configuration for HDMI output on the IMX6 SoCs Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-02-13ARM: dts: imx6q: add 852MHz setpoint for CPU freqAnson Huang
According to datasheet, i.MX6Q has setpoint of 852MHz which is exclusive with 996MHz, the fuse map of speed_grading defines the max speed of ARM, here we add this 852MHz setpoint opp info, kernel will check the speed_grading fuse and remove all illegal setpoints. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-10ARM: dts: imx6q: Add spi4 aliasSascha Hauer
The quad version has a SPI controller more than the other versions. Add an alias for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6q: add vddsoc/pu setpoint infoAnson Huang
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq is changed, each setpoint has different voltage, so we need to pass vddarm, vddsoc/pu's freq-voltage info from dts together. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx6q: update setting of VDDARM_CAP voltageAnson Huang
According to datasheet, VDD_CACHE_CAP must not exceed VDDARM_CAP by more than 200mV, as all of i.MX6Q boards' VDD_CACHE_CAP currently are connected to VDDSOC_CAP, so we need to follow this rule by increasing VDDARM_CAP's voltage. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-02-09ARM: dts: imx: imx6q.dtsi: use IRQ_TYPE_LEVEL_HIGHTroy Kisky
Make the interrupts node slightly more readable. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx: ocram size is different between imx6q and imx6dlShawn Guo
The ocram on imx6q is 256 KiB while on imx6dl it's 128 KiB. Let's have separate node for imx6q and imx6dl. It also changes imx6q size 0x3f000 to 0x40000 to match the hardware. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Liu Ying <Ying.Liu@freescale.com>
2013-08-22ARM: dtsi: enable ahci sata on imx6q platformsRichard Zhu
Only imx6q has the ahci sata controller, enable it on imx6q platforms. Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: add more imx6q/dl pin groupsShawn Guo
Add more imx6q/dl pin groups for those supported boards, e.g. sabresd, sabreauto, arm2. IPU2 pin groups are added into imx6q.dtsi, since the block is only available on imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx: share pad macro names between imx6q and imx6dlShawn Guo
The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board design can work with either chip plugged into the socket, e.g. sabresd and sabreauto boards. We currently define pin groups in imx6q.dtsi and imx6dl.dtsi respectively because the pad macro names are different between two chips. This brings a maintenance burden on having the same label point to the same pin group defined in two places. The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs pad macro names. Then the pin groups becomes completely common between imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the long term maintenance of imx6q/dt pin settings becomes easier. Unfortunately, the change brings some dramatic diff stat, but it's all about DTS file, and the ultimate net diff stat is good. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx6q{dl}: add a DTE uart pinctrl for uart2Huang Shijie
In the arm2 board, the UART2 works in the dte mode. So add a pinctrl for both the imx6q{dl} boards. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX6: sync imx6q and imx6dl pinmux entriesSascha Hauer
The i.MX6Q and i.MX6DL are pin compatible, so the pinmux entries should be in sync. This patch systematically adds the pinmux entries missing from the imx6q to the imx6dl file. Some name inconsistencies and whitespace damage is fixed along the way. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx6q: add a new pinctrl for ecspi1Huang Shijie
This new pinctrl is used by the imx6q-sabresd board. Signed-off-by: Huang Shijie <b32955@freescale.com>
2013-06-20Merge tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Arnd Bergmann
into next/dt From Shawn Guo: imx device tree changes for 3.11: * A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53, imx53-m53evk and imx27-phytec-phycore * Various pinctrl setting updates and additions * Enable various on board peripherals, usb, audio, nor, display etc. * Configure L2 cache data and tag latency from device tree * Add imx-weim bus driver * tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: (82 commits) ARM: dts: imx27: Add VPU devicetree node ARM: mxc: fix gpio-ranges for VF610 ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio support ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUX ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC support ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962 ARM: dtsi: imx6dl: Add a pinctrl for AUDMUX ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1 ARM: dts: imx6qdl-sabresd: add clko1 iomux configuration ARM: dts: Phytec imx6q pfla02 and pbab01 support ARM: dts: imx6q: Add pinctrl for usdhc2 and enet ARM: dts: imx27-phytec-phycore-rdk: Add MTD name for NOR flash ARM: dts: imx27-phytec-phycore-rdk: Add SDHC support ARM: dts: i.MX27: Add SDHC devicetree nodes ARM: dts: i.MX27: Add DMA devicetree node ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR ARM: dts: imx6dl: add pinctrls for WEIM NOR ARM: dts: imx6q: add pinctrls for WEIM NOR ARM: dts: imx6qdl: add more information for WEIM ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-17ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1Nicolin Chen
Add a pinctrl for I2C1 used on imx6q/dl-sabresd. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6q: Add pinctrl for usdhc2 and enetChristian Hemp
Add a group to the usdhc2 and enet pinctrl. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6q: add pinctrls for WEIM NORHuang Shijie
Add two pinctrls for WEIM: one for the weim nor, another for the chipselect. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>