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Pull watchdog updates from Wim Van Sebroeck:
"This contains following changes:
- Octeon: convert to watchdog-API and apply some fixes
- Cadence wdt: remove dependency on ARCH
- add DT bindings for qcom + msm
- bcm281xx: Remove use of seq_printf return value
- stmp3xxx_rtc_wdt + pnx4008_wdt: fix broken email addresses"
* git://www.linux-watchdog.org/linux-watchdog:
watchdog: stmp3xxx_rtc_wdt: fix broken email address
watchdog: pnx4008_wdt: fix broken email address
watchdog: octeon: use fixed length string for register names
watchdog: octeon: fix some trivial coding style issues
watchdog: octeon: convert to WATCHDOG_CORE API
watchdog: cadence: Remove Kconfig dependency on ARCH
ARM: msm: add watchdog entries to DT timer binding doc
ARM: qcom: add description of KPSS WDT for IPQ8064
watchdog: qcom: use timer devicetree binding
watchdog: bcm281xx: Remove use of seq_printf return value
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Add the watchdog related entries to the Krait Processor Sub-system
(KPSS) timer IPQ8064 devicetree section. Also, add a fixed-clock
description of SLEEP_CLK, which will do for now.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add the node for the LPASS clock controller found on a few qcom
SoCs so that the clock driver can probe.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
[sboyd@codeaurora.org: Added apq8064 and msm8960 nodes]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The interrupt is 16, not 32 (which it would be if we include PPIs
in the count of interrupts).
Cc: Andy Gross <agross@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <agross@codeaurora.org>
Tested-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Add SATA PHY and SATA AHCI controller nodes to device tree to enable
generic ahci support on the IPQ8064/AP148 board.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Add basic IPQ8064 SoC include device tree and support for basic booting on
the AP148 Reference board with support for UART, I2C, and SPI.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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