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2011-07-15ARM: remove unnecessary dcache_clean_areaHeechul Yun
Cortex-A9 has PIPT D-cache which do not require clean the cache on creating page table. Change-Id: I42d528be83ea8def96045c7e575c7b3ed95f5980 Reviewed-on: http://git-master/r/40505 Reviewed-by: Heechul Yun <hyun@nvidia.com> Tested-by: Heechul Yun <hyun@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-07-15ARM: remove unnecesarry L2 cache flushHeechul Yun
The memory barrier, mb(), flush L2 cache which is unnecessary for bit operations because D cache is coherent for all CPUs This patch improves scalability of the system. Change-Id: I3bec7ec767849091b6da720869241f3a16a7b5cb Reviewed-on: http://git-master/r/40504 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Heechul Yun <hyun@nvidia.com> Reviewed-by: Heechul Yun <hyun@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-25ARM: mm: domain switch removalXin Xie
This patch has 2 purposes: * Disable CPU prefetching ioremap'ed memory * Keep Copy-On-Write policy for some CPU instructions emulation in kernel space(i.e. SWP) This is the backport of the upstream Linux kernel: * ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUs (main kernel commit ID: 247055aa21ffef1c49dd64710d5e94c2aee19b58) Change-Id: Ic467be916282278e104192401b5289d283317f1a Reviewed-on: http://git-master/r/29734 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-05-25Revert "HACK stay compatible with the emulated TLS register HACK"Xin Xie
This reverts commit f00c8f71dae5a16b7fab0e77fc8b32feac9d38a7. We need enable the SWP() emulation which depend on removing domain switching on ARM kernel. Emulated TLS register requires the user space page mapped as R/W in kernel which requires domain swtiching. Remove this patch becasue the ARM V7 has HW TLS register. Change-Id: I8772832333cf53aaf2d5061d3b459576a737fcaa Reviewed-on: http://git-master/r/29733 Reviewed-by: Xin Xie <xxie@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-17ARM: 6355/1: hw-breakpoint: add mechanism for hooking into prefetch abortsWill Deacon
On ARM processors with hardware breakpoint and watchpoint support, triggering these events results in a debug exception. These manifest as prefetch and data aborts respectively. arch/arm/mm/fault.c already provides hook_fault_code for hooking into data aborts dependent on the DFSR. This patch adds a new function, hook_ifault_code for hooking into prefetch aborts in the same manner. This is picked from following git repository: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-2.6.38.y.git Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: S. Karthikeyan <informkarthik@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 3a4b5dca53aecb16db9e007d782b2d1e757e941a) Change-Id: Ic278bad0e3bb95f504e46b216a8d14fd61fbc4a5 Reviewed-on: http://git-master/r/31574 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-11ARM: errata: 727915: Background Clean & Invalidate by Way operation can ↵vdumpa
cause data corruption. PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. This fix is to replace the background Clean & Invalby Way operation by a software loop on all sets/ways. This works for r2p0 and r3p0 as well. Change-Id: I45e841d8049a18f2dd36ce13e8ef15322f14c5d5 Reviewed-on: http://git-master/r/29690 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-04-26arm: tegra3: Add SMP CPU idle supportScott Williams
Original-Change-Id: I96edd2706d959f04e9bc5cd4a841d9a582fbd469 Reviewed-on: http://git-master/r/14575 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I3d49abf93947d09af9bc6faf2b15675303723515
2011-03-22ARM: SMP: remove per_cpu based spinlock in do_IPI()Xin Xie
The spinlock used in the do_IPI function is declared in per_cpu section, and it does not have the cache snooping which can cause the spinlock failure. This fix is based on the main kernel tree: - ARM: SMP: avoid using bitmasks and locks for IPIs, use hardware instead commit 24480d980e9063b3ebd0dfdf2f396c305956c356 - ARM: SMP: remove IRQ-disabling for smp_cross_call() commit 0df7095205cbf6ea1cdfe6254e0d6a3b823caa3b BUG 798775 Change-Id: I6e03027cb3f586803a260e216c71fc2fd74d09f2 Reviewed-on: http://git-master/r/23779 Reviewed-by: Xin Xie <xxie@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-03-01merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Conflicts: arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/fuse.c arch/arm/mach-tegra/fuse.h arch/arm/mach-tegra/kfuse.c arch/arm/mach-tegra/tegra2_clocks.c drivers/video/tegra/dc/Makefile drivers/video/tegra/dc/hdmi.c drivers/video/tegra/dc/hdmi.h drivers/video/tegra/dc/nvhdcp.c Change-Id: I60a025d9e23e0699afcfaf9e3e42a98263cd7de8
2011-02-24Merge branch linux-tegra-2.6.36 into android-tegra-2.6.36Erik Gilling
Conflicts: drivers/video/tegra/dc/hdmi.c Change-Id: I10fd2dbcc07d7961dd75e10a2c4de926457c2912
2011-02-16ARM: PL310: Add power control register definitionTodd Poynor
Change-Id: Ia1f759aab15a241e8e29447622cd1e2998fa745c Signed-off-by: Todd Poynor <toddpoynor@google.com>
2011-01-10merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Conflicts: arch/arm/mach-tegra/fuse.c drivers/misc/Makefile Change-Id: I300b925d78b31efe00c342190d8dbd50e2e81230
2011-01-07Merge branch 'android-2.6.36' into android-tegra-2.6.36Colin Cross
2011-01-07ARM: 6490/1: MM: bugfix: initialize spinlock for init_mm.contextMyungJoo Ham
init_mm used at kernel/sched.c:idle_task_exit() has spin_lock (init_mm.context.id_lock) that is not initialized when spin_lock/unlock is called at an ARM machine. Note that mm_struct.context.id_lock is usually initialized except for the instance of init_mm at linux/arch/arm/mm/context.c Not initializing this spinlock incurs "BUG: pinlock bad magic" warning when spinlock debug is enabled. We have observed such instances when testing PM in S5PC210 machines. Change-Id: I52c6c6d035c220822a5675faaf8d163a3535985d Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Colin Cross <ccross@android.com>
2011-01-05merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Change-Id: I5fba2375f84610fda29872d1ea41d82404ee08f6
2011-01-04Merge branch linux-tegra-2.6.36 into android-tegra-2.6.36Erik Gilling
Change-Id: Iec42f1fa234c03c6267f91ba0553d1c651b9ba94
2011-01-04ARM: smp_twd: Use cpufreq notifiers to update prescalersColin Cross
Change-Id: I957d5ca8580d4e7a98fb9fc754ca8f00133940d9 Signed-off-by: Colin Cross <ccross@android.com>
2010-12-23merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Conflicts: arch/arm/mach-tegra/board-ventana-power.c drivers/mfd/tps6586x.c Change-Id: Ic8c46d4251d6e71fa2900b7e876f87e256299bc4
2010-12-21Merge branch 'linux-tegra-2.6.36' into android-tegra-2.6.36Colin Cross
Conflicts: drivers/usb/gadget/composite.c Change-Id: I1a332ec21da62aea98912df9a01cf0282ed50ee1
2010-12-21Merge commit 'v2.6.36.2' into linux-tegra-2.6.36Colin Cross
2010-12-09ARM: 6489/1: thumb2: fix incorrect optimisation in usraccWill Deacon
commit 1142b71d85894dcff1466dd6c871ea3c89e0352c upstream. Commit 8b592783 added a Thumb-2 variant of usracc which, when it is called with \rept=2, calls usraccoff once with an offset of 0 and secondly with a hard-coded offset of 4 in order to avoid incrementing the pointer again. If \inc != 4 then we will store the data to the wrong offset from \ptr. Luckily, the only caller that passes \rept=2 to this function is __clear_user so we haven't been actively corrupting user data. This patch fixes usracc to pass \inc instead of #4 to usraccoff when it is called a second time. Reported-by: Tony Thompson <tony.thompson@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-11-22kgdb,arm: fix register dumpRabin Vincent
commit 834b2964b7ab047610da038e42d61dc8dac6339a upstream. DBG_MAX_REG_NUM incorrectly had the number of indices in the GDB regs array rather than the number of registers, leading to an oops when the "rd" command is used in KDB. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-10-19Merge remote branch 'android-tegra-2.6.36'Dan Willemsen
Conflicts: arch/arm/configs/tegra_defconfig arch/arm/mach-tegra/tegra_i2s_audio.c Change-Id: Ib0d7fc5c84b21a58f78a4a987c245e0e110ff437
2010-10-19Merge branch 'linux-tegra-2.6.36' into android-tegra-2.6.36Rebecca Schultz Zavin
2010-10-19Revert "[ARM] mm: add page allocator for modifying cache attributes"Gary King
This reverts commit 54d414570432ce07fa1a14b657f53bed752e3d7e. Change-Id: I8e5cf6ef3555129da9741ef52a1e6a3a772ad588 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-13ARM: Use lazy cache flushing on ARMv7 SMP systemsCatalin Marinas
ARMv7 processors like Cortex-A9 broadcast the cache maintenance operations in hardware. This patch allows the flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode similar to the UP case. Note that cache flushing on SMP systems now takes place via the set_pte_at() call (__sync_icache_dcache) and there is no race with other CPUs executing code from the new PTE before the cache flushing took place. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
2010-10-13ARM: Synchronise the I and D caches via set_pte_at() on SMP systemsCatalin Marinas
On SMP systems, there is a small chance of a PTE becoming visible to a different CPU before the cache maintenance operations in update_mmu_cache(). This patch follows the IA-64 and PowerPC approach of synchronising the I and D caches via the set_pte_at() function. In this case, there is no need for update_mmu_cache() to be implemented since lazy cache flushing is already handled by the time this function is called. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
2010-10-13ARM: Assume new page cache pages have dirty D-cacheCatalin Marinas
There are places in Linux where writes to newly allocated page cache pages happen without a subsequent call to flush_dcache_page() (several PIO drivers including USB HCD). This patch changes the meaning of PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly mapped page in update_mmu_cache(). The patch also sets the PG_arch_1 bit in the DMA cache maintenance function to avoid additional cache flushing in update_mmu_cache(). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
2010-10-13Revert "ARMv7: Use lazy cache flushing if hardware broadcasts cache operations"Gary King
This reverts commit ff6c5cd434c779b6b3e8140a5bd5c30793a6123f.
2010-10-08Merge commit 'tegra/linux-tegra-2.6.36' into android-tegra-2.6.36Rebecca Schultz Zavin
2010-10-08[ARM] mm: add memory type for inner-writebackGary King
For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] mm: add page allocator for modifying cache attributesGary King
ARM CPUs with speculative prefetching have undefined behaviors when the same physical page is mapped to two different virtual addresses with conflicting cache attributes. since many recent systems include IOMMU functionality (i.e., remapping of discontiguous physical pages into a virtually-contiguous address range for I/O devices), it is desirable to support allocating any available OS memory for use by the I/O devices. however, since many systems do not support cache coherency between the CPU and DMA devices, these devices are left with using DMA-coherent allocations from the OS (which severely limits the benefit of an IOMMU) or performing cache maintenance (which can be a severe performance loss, particularly on systems with outer caches, compared to using DMA-coherent memory). this change adds an API for allocating pages from the OS with specific cache maintenance properties and ensures that the kernel's mapping of the page reflects the desired cache attributes, in line with the ARMv7 architectural requirements Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06ARMv7: Use lazy cache flushing if hardware broadcasts cache operationsCatalin Marinas
ARMv7 processors like Cortex-A9 broadcast the cache maintenance operations in hardware. The patch adds the CPU ID checks for such feature and allows the flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode similar to the UP case. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2010-10-06Merge branch 'android-2.6.36' into android-tegra-2.6.36Colin Cross
Conflicts: drivers/input/touchscreen/Kconfig Change-Id: Ifc75266e258f9513d78c47c12e2f1de1d2344f02
2010-10-06[ARM] twd: Allow twd rescaling to match cpu frequencyColin Cross
The clock to the ARM TWD local timer scales with the cpu frequency. To allow the cpu frequency to change while maintaining a constant TWD frequency, pick a lower target frequency for the TWD and use the prescaler to divide down to the closest lower frequency. This patch provides a new initialization function that takes a target TWD frequency and the relation between the cpu clock and the TWD clock, required to be an integer divider >= 2 by the ARM spec. It also provides a function to be called from cpufreq drivers to set the prescaler whenever the cpu frequency changes. Also fixes a typo in the printk of the calibrated frequency. Change-Id: I3fa8ef718ff5518170f1b2bab29efe960741853e Signed-off-by: Colin Cross <ccross@google.com>
2010-10-06[ARM] Add ARCH_PROVIDES_UDELAY config optionColin Cross
Change-Id: Ife690c9d055fc0f17a52d2b29048af5062a664a6 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06Add "nol2x0" early param to avoid initialisation of the L2 controllerCatalin Marinas
Some development platforms may have issues with this controller, so allow easy disabling from the kernel command line. The patch also adds a check for l2x0_disabled in the realview_pbx.c code to avoid setting additional L2x0 registers. Change-Id: Icbbd3e054688811200a4c96bf7e0a81c9c0ab790 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2010-10-06[ARM] gic: Export irq chip functionsColin Cross
Some systems combine the GIC with an external interrupt controller. On these systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. Export the irq chip functions so that these systems can define a custom irq chip that calls into the GIC handlers. Change-Id: I17fc4440fa2c91cc63004abf69c8e872b55c83c6 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06[ARM] gic: Add functions to save and restore gic stateColin Cross
on systems with idle states which power-gate the logic including the gic, such as tegra, the gic distributor needs to be shut down and restored on entry and exit from the architecture idle code Change-Id: I17603f5ac70d65c05587d0647cce3ba87675e117 Original-author: Gary King <gking@nvidia.com> Signed-off-by: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06[ARM] cache_l2x0: add shutdown and restart functionsGary King
Add shutdown and restart functions to the L2X0 outer cache controller, so that machines which need to flush and disable the outer cache controller prior to executing the architecture reset or platform suspend code can do so. Change-Id: I042aae121e7ba75223ed502afb4d118b0441597e Signed-off-by: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
2010-10-05ARM: Add generic fiq serial debuggerIliyan Malchev
Change-Id: Ibb536c88f0dbaf4766d0599296907e35e42cbfd6 Signed-off-by: Iliyan Malchev <malchev@google.com> Signed-off-by: Arve Hjønnevåg <arve@android.com>
2010-10-05ARM: Add fiq_glueArve Hjønnevåg
Change-Id: I27d2554e07d9de204e0a06696d38db51608d9f6b Signed-off-by: Arve Hjønnevåg <arve@android.com> Signed-off-by: Colin Cross <ccross@android.com>
2010-10-04[ARM] l2x0: add declaration for PREFETCH_OFFSET registerGary King
Change-Id: I0fc2aba8b332697533e1396aab2e613bc7179c33 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-03ARM: enable CONFIG_CPU_IDLE supportGary King
add ARCH_HAS_CPU_IDLE_WAIT and ARCH_HAS_DEFAULT_IDLE configuration, and expose default_idle and cpu_idle_wait cpu_idle_wait implementation based on the implementation in the x86 tree Signed-off-by: Gary King <gking@nvidia.com>
2010-09-29[ARM] Do not call flush_cache_user_range with mmap_sem heldDima Zavin
We can't be holding the mmap_sem while calling flush_cache_user_range because the flush can fault. If we fault on a user address, the page fault handler will try to take mmap_sem again. Since both places acquire the read lock, most of the time it succeeds. However, if another thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in between the call to flush_cache_user_range and the fault, the down_read in do_page_fault will deadlock. Also, since we really can't be holding the mmap_sem while calling flush_cache_user_range AND vma is actually unused by the flush itself, get rid of vma as an argument. Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106 Signed-off-by: Dima Zavin <dima@android.com>
2010-09-29HACK stay compatible with the emulated TLS register HACKBrian Swetland
Change-Id: I06453a7ce78a3d201f3cd5145d3000b0d9ba11fe
2010-09-19ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasingCatalin Marinas
ARMv7 onwards requires that there are no aliases to the same physical location using different memory types (i.e. Normal vs Strongly Ordered). Access to SO mappings when the unaligned accesses are handled in hardware is also Unpredictable (pgprot_noncached() mappings in user space). The /dev/mem driver requires uncached mappings with O_SYNC. The patch implements the phys_mem_access_prot() function which generates Strongly Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and Normal Noncacheable (writecombine) if O_SYNC. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-08Revert "[ARM] pxa: remove now unnecessary dma_needs_bounce()"Russell King
This reverts commit 4fa5518, which causes a compilation regression for IXP4xx platforms. Reported-by: Richard Cochran <richardcochran@gmail.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-01ARM: 6343/1: wire up fanotify and prlimit64 syscalls on ARMMikael Pettersson
The 2.6.36-rc kernel added three new system calls: fanotify_init, fanotify_mark, and prlimit64. This patch wires them up on ARM. The only non-trivial issue here is the u64 argument to sys_fanotify_mark(), but it is the 3rd argument and thus passed in r2/r3 in both kernel and user space, so it causes no problems. Tested with a 2.6.36-rc2 EABI kernel on an ixp4xx machine. Tested-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-01ARM: 6330/1: perf: reword comments relating to perf_event_do_pendingWill Deacon
This is purely a cosmetic change to the ARM perf backend because the current comments about the relationship between NMIs, interrupt context and perf_event_do_pending are misleading. This patch updates the comments so that they reflect what the code actually does (which is in line with other architectures). Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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