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M4 root clk shouldn't be turn off when M4 core is running
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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when kernel command line has "uart_from_osc" defined, set uart1
parent clock to OSC for low power case.
The patch also abstract the kernel parameter for IMX common to
reduce the redundant code. But for i.MX6SL patform, the origin
kernel parameter is uart_at_4M, now is changed to uart_from_osc.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add support to leave PLL1 enabled since its required whenever ARM-PODF is
changed. With this patch PLL1 is set to bypassed mode (and enabled) whenever
ARM is sourced from step_clk.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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When the M4 core is enabled on i.MX6, the QSPI2 clk can't be gated,
otherwise, the M4 will hang. This patch add a check to make sure when
M4 is enabled, just skip the QSPI2 clk gating operations.
Signed-off-by: Bai Ping <b51503@freescale.com>
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As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Since CAN device is allocated to run on M4 and handled by M4 if M4 is enabled,
so we do not set CAN parent clock when M4 is enabled.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit b41622a58d6e10e1be2618bf98fab6cc977d9985)
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QSPI2/GPMI_IO share the same clock source but with the
different gate, need explicitely gate the QSPI2 & GPMI_IO
during the clock init phase according to the SOC design.
The topo of the clock for the GPMI_IO and NAND as below:
mux --> pre divider --> post divider --gate-- >GPMI_IO
|-gate-- >QSPI2
(Note: i.MX6SX:GPMI_NAND and GSPI2 is PINMUX conflicts.)
The SOC design spec required that if change the parent clock
of the GPMI_IO or QSPI2, need gate the GPMI_IO and QSPI2 first
otherwise, there will have some glitch which cause the divider
malfunciton. Thus, we need explicitely gate QSPI2 & GPMI_IO at
the clock initialization phase and then later on common clock
framework will gurantee that each time, the parent clock rate
changes after the child clock is disabled(gated).
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 110d63a5886e065e77a69f816216af044c096a44)
Conflicts:
arch/arm/mach-imx/clk-imx6sx.c
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SAI and SAI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 1223c730e5ca58794721c26b3803b96f95fd3937)
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SSI and SSI_IPG are clocks controlled by the same clock gating field, so
register them with imx_clk_gate2_shared.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
(cherry picked from commit 42222ee66ae046187b0ca8ec4b0c00c8832810a7)
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As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
Signed-off-by: Anson Huang <b20788@freescale.com>
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By default, uboot set uart clk parent to OSC to make UART work when M4
is enabled. In the situation, uart maximum baud rate only reach at 1.5Mbps
that cannot match real case requirement.
The patch set the uart module clock source to pll3_80m in default. If
test low power case, it needs to add "uart_from_osc" in kernel command line.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit f9cfc11cf8628bd01efda611074131bfa323a120)
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change procedure.
Recent checks added to the clock code prints warning during ddr frequency change procedure.
Hence the clock rates printed by clk_summary after ddr freq change are incorrect.
This patch fixes the issue by:
1. Removing CLK_SET_RATE_GATE for ocram_clk since it has a busy bit to be checked when
the ocram_podf is changed.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
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Those system bus related mux only can be switched by busfreq driver,
and in busfreq asm code, it already follow the flow that hardware design
require, so no need to do flow check for these clk mux:
i.MX6Q/DL: periph_clk2_sel and pre_periph_clk_sel;
i.MX6SL: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel
i.MX6SX: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel.
Signed-off-by: Anson Huang <b20788@freescale.com>
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We already know that pll2_bus is the best parent of QSPI clock. Let's
set it up in clock initialization as the default, so that we can save
those implicit parent switching and rate changing calls from clock
framework.
shawn.guo: cherry-pick commit ecef6a715f1a from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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initialized
This is a forward porting of commit ebf625e1a496 (ENGR00318063-12: ARM:
imx6: enable clocks only after all parent and rate are initialized) from
imx_3.10.y to imx_3.14.y.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This is a forward porting of commit 580f8c84ae81 (ENGR00318063-11: ARM:
imx6: add return check for clock calls) from imx_3.10.y to imx_3.14.y.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The i.MX6 Reference Manual requires PLLs to be powered down before
changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and
audio/video dividers to enforce the check at clock core level. So any
clk_set_rate() call from clients on these clocks will fail if the clocks
are not disabled and unprepared.
shawn.guo: cherry-pick commit 763c47cb3684 from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The mux clocks found on imx6 SoCs are all glitchy ones except
pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When
switching parent clock of a glitchy mux without gating, a glitch could
be generated and propagated into the downstream divider, and hence locks
up the divider and results in no clock output.
To avoid the situation, the parent switching should happen only when
the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks,
so that clock core will make that check during clk_set_parent() call.
Since glitchless clocks do not need this flag, we create
imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel
and periph2_clk_sel are registered by imx_clk_busy_mux() which does not
set this flag anyway, so they need no change.
shawn.guo: cherry-pick commit 10bae51219b3 from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The current imx6sx clock driver combines two mux clocks ocram_alt_sel
and ocram_sel into one, while ocram_alt_sel is a glitchy mux and
ocram_sel is a glitchless one. Fix it to match the clock tree in
Reference Manual.
One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy ocram_alt_sel only when ocram_sel selects the
other path, i.e. periph. Otherwise, a glitch could be generated on
ocram_alt_sel and get propagated into the divider ocram_podf. In that
case, ocram_podf gets locked up and ocram clock has no output.
shawn.guo: cherry-pick commit a3b6793d21d9 from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang for spotting the error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
(cherry-picked from commit a1a0c0ac5b0e2bdf9870436b0b4f3075380c3372)
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Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m, register
this clk for system timer in MSL.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As some modules need to access ocotp in MSL, so we need to
make sure it is enabled during MSL, after kernel boot up,
clk dirver will disable it in late init.
Signed-off-by: Anson Huang <b20788@freescale.com>
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change perclk parent to OSC instead of IPG, as IPG clock may
be changed by busfreq.
when kernel command line has "uart_from_osc" defined, uart clk will
select OSC as its parent, this is to make PLL3 be able to be off
for low power purpose, as we need all PLLs off in low power idle
mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add clock driver for i.MX6 SoloX SoC.
Signed-off-by: Anson Huang <b20788@freescale.com>
[shawn.guo: cherry-pick commit d55135689019 from upstream]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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