| Age | Commit message (Collapse) | Author |
|---|
|
Only register power_off function when device tree property
_/soc/fsl,use-lpm-poweroff_ is set.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
|
|
By registering a power_off command the kernel does not go to halt
state but instead tries to power off. Our power off function sets
the SoC in a low power stop mode, which essentially turns itself
off almost completely.
Code snippet is taken from 3.0 kernel:
http://git.toradex.com/cgit/linux-toradex.git/commit/?h=colibri&id=28fc68ba39c7a2210f2bb11f866f20731f0918bd
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
|
|
Initialize suspend to memory in a own function. With that we can
continue initialization in case SRAM or external pull resistors
are not available and provide the standby mode only.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
The calls to iounmap require a pointer to __iomem. The element
vbase is already a pointer to __iomem, there is no need to
dereference the pointer again.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
|
|
The current probe code ignores a missing L2 cache, but still returns
ENODEV. Avoid returning ENODEV if a L2 cache is missing by setting
ret to 0.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
|
|
Flush caches before entering stop mode. This fixes a stack trace
which have been observed every ~3rd time entering Vybrid's STOP
mode (standby):
[ 103.630698] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 103.630698] pgd = 8e3cc000
[ 103.630698] [00000000] *pgd=8dae6831, *pte=00000000, *ppte=00000000
[ 103.630698] Internal error: Oops: 817 [#1] ARM
[ 103.630698] Modules linked in:
[ 103.630698] CPU: 0 PID: 164 Comm: sh Not tainted 4.1.5-00149-g9658f3e-dirty #391
[ 103.630698] Hardware name: Freescale Vybrid VF5xx/VF6xx (Device Tree)
[ 103.630698] task: 8d8d2140 ti: 8d866000 task.ti: 8d866000
[ 103.630698] PC is at cpu_ca8_dcache_clean_area+0x1c/0x34
[ 103.630698] LR is at vf610_pm_enter+0x74/0x84
[ 103.630698] pc : [<8001d648>] lr : [<80020a0c>] psr: a00f0093
[ 103.630698] sp : 8d867dd8 ip : 8d867da8 fp : 8d867de4
[ 103.630698] r10: 00000000 r9 : 807a6ad2 r8 : 807a60d4
[ 103.630698] r7 : 807d8f8c r6 : 00000002 r5 : 807d8f8c r4 : 00000000
[ 103.630698] r3 : 8001d620 r2 : 00000000 r1 : 00000000 r0 : 00000000
[ 103.630698] Flags: NzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
[ 103.630698] Control: 10c5387d Table: 8e3cc059 DAC: 00000015
[ 103.630698] Process sh (pid: 164, stack limit = 0x8d866208)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
|
|
To use self-refresh mode for DDR3 SDRAM memory in LPSTOPx mode, the
hardware need to have pull-ups/downs populated on RESET/CKE line of
the DDR memory. Read the device tree property which indicates whether
a given board has such resistors populated.
|
|
Add system suspend and resume support for Vybrid SoC. The standby
sleep state puts the SoC in STOP mode. The SoC can be woken through
an interrupt from GPC (Global Power Controller). The GPC can use any
interrupt as wake-up source. To save power the main PLL1 is bypassed
and uses the 24MHz on-chip oscillator. However, memory clock need to
be at full speed, hence the PLL2 needs to be on to keep the memory
clocked. The mode is completely implemented in C since we can access
the full memory at all times. The mode provides most power saving
while being able to be woken by any IRQ as wake-up source.
The mem sleep state (Suspend-to-RAM) uses Vybrid's LPSTOP2 mode. This
mode powergates most parts of the SoC expect some peripherials such as
Wake-Up controller (WKPU) or LP RTC. Parts of the internal SRAM is
retained too. The suspend code written in assembly runs from this SRAM.
The code puts the main memory (DDR3) into self-refresh mode and takes
it out of self-refresh mode on resume. Verified with Colibri VF50/VF61
V1.2A.
|
