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2019-05-24arm: imx: fix handling power stuff without psciMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-05-24arm: imx: gpc: do not poweroff M/F mix in suspendMax Krummenacher
The Colibri iMX6ULL 256MB crashes in resume if the M/F mix domain is powered down when suspending. With this workaround this does not happen. Crash looks as follows: root@colibri-imx6ull:~# echo +3 > /sys/class/rtc/rtc1/wakealarm; echo mem > /sys/power/state [ 52.800741] PM: Syncing filesystems ... done. [ 52.856715] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 52.865669] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 52.875024] Suspending console(s) (use no_console_suspend to debug) [ 52.950638] PM: suspend of devices complete after 68.211 msecs [ 52.952506] PM: late suspend of devices complete after 1.835 msecs [ 52.954292] PM: noirq suspend of devices complete after 1.757 msecs [ 52.954300] Disabling non-boot CPUs ... [ 52.954307] Turn off M/F mix! [ 52.955663] PM: noirq resume of devices complete after 1.222 msecs [ 52.956767] imx-sdma 20ec000.sdma: loaded firmware 3.3 [ 52.957669] PM: early resume of devices complete after 1.411 msecs [ 52.959140] gpmi-nand 1806000.gpmi-nand: use legacy bch geometry [ 53.005653] Suspended for 2.907 seconds [ 53.012207] PM: resume of devices complete after 54.507 msecs [ 53.073751] Restarting tasks ... done. root@colibri-imx6ull:~# [ 55.049753] gpmi-nand 1806000.gpmi-nand: DMA timeout, last DMA :2 [ 55.056377] gpmi-nand 1806000.gpmi-nand: Show GPMI registers : [ 55.062835] gpmi-nand 1806000.gpmi-nand: offset 0x000 : 0x00000000 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-05-24ARM: imx: mach-imx7d: configure clock source per FEC instanceStefan Agner
Configure Ethernet clock source for each FEC instance individually. This allows to use different clock source setting for the two FEC controllers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-05-24ARM: imx: mach-imx7d: put external ethernet clock in error caseStefan Agner
Exit early in case General-Purpose Registers are missing. This makes sure that clock is always freed properly (clk_put). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-05-24ARM: imx: gpc: Fix undefined references when using GPCv2Stefan Agner
When compiling a kernel with only GPCv2 support (e.g. only for i.MX 7) linking fails with the following errors: arch/arm/mach-imx/built-in.o: In function `imx_anatop_pre_suspend': platform-imx-dma.c:(.text+0xf50): undefined reference to `imx_gpc_usb_wakeup_enabled' platform-imx-dma.c:(.text+0xf5c): undefined reference to `imx_gpc_enet_wakeup_enabled' arch/arm/mach-imx/built-in.o: In function `imx_anatop_post_resume': platform-imx-dma.c:(.text+0x10cc): undefined reference to `imx_gpc_usb_wakeup_enabled' platform-imx-dma.c:(.text+0x10d8): undefined reference to `imx_gpc_enet_wakeup_enabled' Make sure the function exist even if GPC(v1) is not compiled in. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-05-24imx: Fix 'Expose SoC unique ID' for newer i.MX6Max Krummenacher
i.MX6 SL/UL/ULL use a different node in the device tree for with ocotp. So change to the relevant compatible string for these SoCs. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit 7b02a99744e495f630bdb5081c516d40e8112685)
2019-05-24busfreq-imx: only use existing global variablesMax Krummenacher
The struct arm_reg and soc_reg are declared in by a extern statement in include/linux/busfreq-imx.h. However they are only declared when imx6-cpufreq.c is compiled and linked. Qualify the use of arm_reg and soc_reg with the relevant config option and change KConfig to switch that option on for the SoCs which use it. This fixes the following build issue when building for i.MX 7 with option ARM_IMX6Q_CPUFREQ not set: arch/arm/mach-imx/built-in.o: In function `imx6ull_lower_cpu_rate': platform-imx-dma.c:(.text+0x5514): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x551c): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x553c): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x5544): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x5598): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x55a0): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x55ac): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55b4): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55c8): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55d0): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55f0): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x55f8): undefined reference to `arm_reg' Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> (cherry picked from commit 3f68dc7c600c0354f5df7f06b931661319addafb)
2019-05-24ARM: imx: spare the first 16KiB of OCRAM_S for Cortex-M4Stefan Agner
The Cortex-M4 boot vector table is located in the OCRAM_S. When building a firmware with a complete vector table at 0x00000000 Linux overwrites the vector table with suspend information. Use the higher 16KiB for suspend related information so that we can use the lower 16KiB for the Cortex-M4 core. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit a8e0d437843393309b6db46c0e19f9da0b5d213b)
2019-05-24apalis-imx6: use stopmode for poweroffMax Krummenacher
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 051ee1a1c24058db62f10a177b1271daebbd2ebe)
2019-05-24pm-imx6.c: fix power off by stop modeMax Krummenacher
With the 3.14.28 release of the kernel imx6_stop_mode_poweroff() does not enter stop mode. Thus the function does not switch of power but returns. This seems to be caused by the second processor which has been stopped. Set the WFI event mask for the stopped processor works around the issue. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry-picked from commit 2acff0eaece38533e85e08431e7ae9f3027c677a) (cherry picked from commit 894914718e9e563eb601e0090e1ae2ddadf426a9)
2019-05-24colibri-imx6: use stopmode for poweroffMax Krummenacher
After the system has been shutdown with PMIC_ON_REQ and VCC_BATT is supplied from a battery it will never restart either by RESET or power cycle. So use the PMIC_STBY_REQ after shutdown to switch off power rails. Conflicts: arch/arm/mach-imx/pm-imx6.c drivers/regulator/pfuze100-regulator.c (cherry-picked from commit c8b186404065c4502b485820ad4a51515924795c) (cherry-picked from commit ee4c5c4da3b32f65528a2d523ca4bce574dee3c5) Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 29ff2389ecf7cb4e30924c80b8d42165cf306936)
2019-05-24ARM: imx: mu: let Cortex-M4 know about A7 stateStefan Agner
Introduce two new messages to let the Cortex-M4 know in what state the Linux system is in. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit a86db1f7117a62019106e343ff894c6bd4da053d)
2019-05-24imx: Expose SoC unique IDBhuvanchandra DV
Expose SoC unique ID read from OCOTP registers. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 9090b5b90ccc350611a769230eab3fbc20c9d302)
2019-05-24mach-imx6q.c: handle RESET_MOCI when PCIe is disabledMax Krummenacher
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 02110528b45ae331d89f7e7bb6a29b5494ec0be1) (cherry picked from commit 8d07763eb1d6a2a11e9b237ac94b8de43183b02e) Conflicts: arch/arm/mach-imx/mach-imx6q.c (cherry picked from commit bea05755680df306e93e5a13f730fd1db203f947)
2019-05-13mach-imx7d.c: use enet_out clk to decide on PHY clockMax Krummenacher
The i.MX 7 can provide a reference clock to the PHY or use a reference clock from an external circuit. If the device-tree node with compatible "fsl,imx7d-fec" has a clock named enet_out then provide the clock from the i.MX 7, if such a clock is missing use a clock provided from an external circuit. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit 73c06d69321c45b69ffc864cbaaa7143da87d186) (cherry picked from commit d46df0826a9f948f05b71da80aa9397cb9337537)
2019-05-13ARM: imx: enet1: output reference clockMax Krummenacher
Enable output driver of Ethernet reference clock. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit dab46121a94916a253d7283c8b85ea6dcfb6e628) (cherry picked from commit 0adde3fe0129ae91e71e079c495b5c28974663c8)
2019-03-04MLK-21031 arm: imx: fix standby resume hang on imx7ulpJacky Bai
When system resume from VLPS mode, DDR IO must be restored before mmdc out of the self-fresh mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Tested-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 7dec20bcb6633c7feee1eb32a5d81356075a61f7)
2019-02-20MLK-20951 arm: imx: Update the mmdc io save/restore on imx7ulpJacky Bai
When system enters VLPS/VLLS mode, the IOMUXC config register for MMDC related IO pads need to set to '0' to reduce the current leakage for these IO pads. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-20389 Changed OPTEE busfreq traceCedric Neveux
To be able to constat that busfreq is started/done vith OPTEE OS, changed the mach-imx/busfreq_optee.c pr_debug macro with printk(KERN_DEBUG ...) Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
2019-02-12MLK-20582 Fix busfreq compilation CONFIG_OPTEE=nCedric Neveux
Compilation error with busfreq optee when CONFIG_OPTEE=n Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
2019-02-12MLK-20450 Fix Linux NO SMP kernel with OPTEECedric Neveux
- Fix busfreq optee mode to not install the linux assembly function used to synchronize all CPU in case of SMP mode - Fix l2cache OPTEE/Linux share mutex operations Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
2019-02-12MLK-20259 ARM: imx: add soc revision check for i.MX7ULPAnson Huang
i.MX7ULP SoC revision is available from B0, the SIM_JTAG_ID register bit[31:28] indicates SoC revision as below: 4b'0001 B0 4b'0010 B1 This register is NOT available on A0, tested on B1 chip as below: root@imx7ulpevk:~# cat /sys/devices/soc0/revision 2.1 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Tested-by: Ye Li <ye.li@nxp.com>
2019-02-12MLK-20203-3 ARM: imx: fix coverity issueAnson Huang
This patch fixes coverity issue of "divide by 0". Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-20023 Move Busfreq support to OPTEE OSCedric Neveux
- When OPTEE OS is present and if it support the busfreq for the running the i.MX, the busfreq is executed in the OPTEE OS by calling a specific SMC function - Only a WFE function is copied into the OCRAM to synchronize all Cores in multi-core devices - OPTEE OS add a DT property 'busfreq=1' in the 'firmware/optee' node to indicate the busfreq support Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
2019-02-12MLK-19589-01 ARM: imx: add imx6ulz basic supportBai Ping
The i.MX6ULZ is new SOC of the i.MX6 series. it is SW compatile with i.MX6ULL, so most of the code can be reuse from i.MX6ULL. To maximum the SW reuse, i.MX6ULZ don't have an independent SOC id in anamix. so a dummy ID is used to identify it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-19149 ARM: imx: fix low bus mode hang on i.MX7DAnson Huang
Per design requirement, AHB clock parent switch and divider change needs to keep previous/current parent enabled but when we switch the clock parent, previous AHB clock parent may be disabled by common clock framework if the use count is 0, so here we have to make sure AHB's previous parent pfd2_270m is enabled during AHB set rate. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit 41cb188e5f4732c7fdb83894399c4dc1303fd774)
2019-02-12MLK-19047-2 ARM: imx: busfreq: Prevent double reduce_bus_freqLeonard Crestez
The low_bus_freq_handler can be scheduled again between when it starts executing and when it takes the bus_freq_mutex. This can result in calling reduce_bus_freq twice as shown in the following trace: [ 762.101949] set_low_bus_freq(743): begin [ 762.101971] set_low_bus_freq(768): schedule low_bus_freq [ 762.114111] set_low_bus_freq(771): scheduled low_bus_freq [ 765.125161] reduce_bus_freq_handler(722): lock... [ 765.125174] bus_freq_daemon_handler(1043): lock... [ 765.125191] bus_freq_daemon_handler(1048): call set_low_bus_freq [ 765.125200] set_low_bus_freq(743): begin [ 765.125210] set_low_bus_freq(768): schedule low_bus_freq [ 765.125228] set_low_bus_freq(771): scheduled low_bus_freq [ 765.125239] bus_freq_daemon_handler(1052): unlock... [ 765.160624] reduce_bus_freq_handler(726): call reduce [ 765.166952] reduce_bus_freq(685): begin [ 765.170865] busfreq_notify(159): notify low enter [ 765.176095] Bus freq set to 24000000 start... [ 765.182731] Bus freq set to 24000000 done! cpu=0 [ 765.192646] imx_busfreq soc:busfreq: Bus freq set to low mode. Count: high 0, med 0, audio 0 [ 765.203912] reduce_bus_freq(717): end [ 765.208903] reduce_bus_freq_handler(733): unlock... [ 768.166631] reduce_bus_freq_handler(722): lock... [ 768.172386] reduce_bus_freq_handler(726): call reduce [ 768.186330] reduce_bus_freq(685): begin [ 768.191310] busfreq_notify(159): notify low enter Prevent this scenario by explicitly calling cancel_low_bus_freq_handler from inside reduce_bus_freq_handler. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-19047-1 ARM: imx: busfreq: Add debug check for double notifyLeonard Crestez
The only user of busfreq notifiers is imx_thermal and if it receives a double LOW_BUSFREQ_ENTER it will incorrectly decrease the reference count on its clk. Since tempmon uses pll3 directly this can cause problems like uart hangs. Guard against this scenario with an explicit check and warn inside busfreq_notify. This is not a high-performance path so it's better to be safe. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-18025: ARM: imx: Fix suspend initialization for Optee on imx7ulpClement Faure
Before the kernel starts, optee uses M4 SRAM to allocate its suspend function. When imx7ulp_pm_map_io() executes, the psci driver and psci_ops.cpu_suspend are not initialized yet. This causes the memset to always wipe the optee suspend code in the M4 SRAM. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2019-02-12MLK-18181-2 ARM: imx: Move gpcv2 regulator notifiers to drivers/socLeonard Crestez
The vendor tree does imx7 PGC management through regulator notifiers while upstream implemented the same features using power domains. These two drivers have entirely different interfaces with higher-level IP blocks. Resolve this conflict by moving the old code to drivers/soc and supporting both power-domain and regulator interfaces. This effectively merges the two drivers and is similar to how imx6sx implements both power domains and a regulator notifier for pcie specifically. Supporting both interfaces allows consumes to switch one-by-one, for example by having PCI work with a power-domains reference while usb hsic still uses the regulator enable/disable interface. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-18181-1 ARM: imx: Clear OF_POPULATED in imx_gpcv2_initLeonard Crestez
The power domain code shares the same node and will not probe if irqchip probes first and marks the node with OF_POPULATED. Clearing the OF_POPULATED flag is also done in imx_gpc_init for imx6 and imx_gpcv2_irqchip_init implemented by upstream. In imx_4.9.y this was solved in a different way by adding a second pgc node, see commit fab513930e78 ("MLK-14280: gpc: gpc driver not probed"). Solving the problem by clearing OF_POPULATED allows using the upstream PGC driver without hacks. Having two irqchip implementations with same name seems to work fine with the mach-imx variant taking precedence. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-18308-2: ARM: imx: imx7ulp: add poweroff featureRobin Gong
On i.mx7ULP, poweroff kernel by sending rpmsg message to M4, and M4 poweroff CA7. Then M4 can power on CA7 again by type 'V' command in its console or press POWERON key once M4 support POWERON. Note: CA7 should enter VLLS mode firstly before poweroff by M4. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-18051 arm: imx: fix the audio bus hang when tee enabledBai Ping
fix audio bus mode hang issue on imx6sl. The root cause of this issue is that busfreq mode passed to TEE side is wrong, it will lead to ccm setting is wrong in TEE. Signed-off-by: Bai Ping <ping.bai@nxp.com> Tested-by: Anson huang <anson.huang@nxp.com>
2019-02-12MLK-16750-5: arm: imx7d: support using psci to handle power stuffPeng Fan
Support using PSCI to handle Power stuff on imx7d. i.MX7 LPSR mode not implemented now. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK15034-4: ARM: cpuidle imx7d: Declare longer exit_latency/target_residencyLeonard Crestez
Low power idle exit latency is much longer than declared, in the milisecond range. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK15034-3: ARM: cpuidle imx7d: Use a single counter for lpi flowLeonard Crestez
The current code for deciding which CPU runs the complete lpi flow is too complicated. Since all enter/exit code now runs under the same lock we can just use a single non-atomic counter of cpus inside lpi. Another variable is used to make num_online_cpus() available to ASM code but idle code can treat it as a constant. Unlike on imx_4.9.y num_online_cpus is fetched every time idle is entered becuase hotplug notifiers are gone. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK15034-2: ARM: cpuidle imx7d: Check IPIs manually before LPILeonard Crestez
The GPC will wake us on peripheral interrupts but not IPIs. So check them manually by reading the GIC's GICD_SPENDSGIR* registers and aborting idle if something is pending. We do this only for the last cpu and after taking the required locks. We know that at this stage the other cpu is in WFI itself or waiting for the imx_pen_lock and can't trigger any additional IPIs. This means that the check is not racy. This fixes occasional lost IPIs causing tasks to get stuck in the TASK_WAKING 'W' state for long periods. This eventually manifested as rcu stalls. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK15034-1: ARM: cpuidle imx7d: Extend imx_pen lock to cover entire flowLeonard Crestez
This makes the code much easier to reason about. In particular it o makes sure the imx7d cpuidle driver respects the requirements for cpu_cluster_pm_enter/exit: * cpu_cluster_pm_enter must be called after cpu_pm_enter has been called on all cpus in the power domain, and before cpu_pm_exit has been called on any cpu in the power domain. * cpu_cluster_pm_exit must be called after cpu_pm_enter has been called on all cpus in the power domain, and before cpu_pm_exit has been called on any cpu in the power domain. This fixes interrupts sometimes getting "stuck" because of improper save/restore of GIC DIST registers. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-14874 ARM: imx7d: Ensure ARM clock only disabled if cpus in same stateLeonard Crestez
GPC will stop ARM clock if both CPUs are in idle and CPU_CLK_ON_LPM is set in GPC_LPCR_A7_BSC. Make sure that doesn't happen when cpu1 enters state2 and cpu0 enters state0 because the default arm WFI state is not marked with CPUIDLE_FLAG_TIMER_STOP and it can result in arch_sys_timer being stopped unexpectedly. It is possible to reproduce incorrect behavior by explicitly disabling other idle states for cpu0/cpu1 and timing how much sleep calls take on cpu0. Ocassionaly something like "sleep 1" will take 3-4 seconds to complete. Make sure that both CPUs are in the same idle state before entering WAIT. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-12349 ARM: imx: skip RBC workaround for standby mode on i.MX7DAnson Huang
For standby mode, RBC workaround is NOT necessary as ARM platform is NOT powered down; Correct GIC register offset(0x1000) for disabling distributor. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12262-6 ARM: imx: enable memory power down for i.MX7D TO1.1Anson Huang
Enable memory power down for i.MX7D TO1.1 to save power, TO1.0 has issue of entering DSM by mistake, so it is disabled as a solution, now that this issue is fixed on TO1.1, enable it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12262-5 ARM: imx: add RBC workaround for i.MX7D DSMAnson Huang
Same as low power idle, during GPC shutting down ARM core, interrupts must be hold until the process done, apply RBC workaround and disable GIC during GPC powering down ARM core. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12262-3 ARM: imx: reduce DDR3 normal frequency to 400MHz for i.MX7D TO1.1Anson Huang
i.MX7D TO1.1 only supports DDR3 running at max frequency of 400MHz, update busfreq driver accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12262-1 ARM: imx: enable ddr auto self-refresh for i.MX7DAnson Huang
Enable DDR auto self-refresh for i.MX7D, when doing DDR frequency scale or suspend/resume, DDR self-refresh will be disabled, this is incorrect for saving power, enable it for all these scenarios. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12262-4 ARM: imx: fix low power idle issue on i.MX7D TO1.1Anson Huang
For low power idle with ARM power gated, per hardware requirement, there must be no interrupt coming during the power down process of ARM core, so RBC counter is enabled to hold interrupts and GIC must be disabled at the moment; The hardware design team recommends ~240us is required during ARM core power down, so we update the RBC counter value to 8(~240us); Update GPC SCU and CPU power up/down timing according to design team's recommendation. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12136-1 ARM: imx: adjust slot control to meet design requirement on i.MX7DAnson Huang
Design team recommend to put SCU/C0/C1 in same power up slot to avoid reset timing issue of debug mode, adjust the power up slot and timing per their requirement. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12093-2 ARM: imx: correct coding errorAnson Huang
Correct coding error and use macro define instead of register value. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12088 ARM: imx: low power idle support for imx7d single core (HAX)Anson Huang
When only single core online for i.MX7D, the secondary core wfi flag should be set to make sure low power idle can be entered when last core enters wfi. Otherwise, DDR/CCM/ANATOP will NOT enter low power mode as the secondary core wfi flag is always clear; Make sure the last power up slot do the ack for single core case. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Since upstream removed cpu hotplug notifiers skip this part. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-12203-2 ARM: imx: adjust loop number to delay ~20us for i.MX7D low power ↵Anson Huang
idle ARM does NOT execute one instruction every cycle, the bus bandwidth, cache status etc. would impacts the instruction execution time, so we can NOT just calculate the delay time by ARM frequency, this patch adjusts loop number to get a ~20us delay, measured via GPIO pin. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12093-1 ARM: imx: adjust latency value of low power idle on imx7dAnson Huang
Per design team's suggestion, when enter/exit DDR PADs low power mode, ~10us delay is necessary to make sure signal stable enough for DDR operation, so add ~20us delay(10us margin) and adjust latency value of low power idle. Optimize enter/exit self-refresh flow of DDRC according to design team's suggestion. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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