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2017-06-19imx: fix errors when CONFIG_SOC_IMX6SLL is not definedAlejandro Mery
I'm not exactly sure how to properly fix the cpuidle part as the whole file seems to assume all IMX* are enabled so this is mostly a "bug-report" instead of a proper patch arch/arm/mach-imx/built-in.o: In function `init_mmdc_lpddr2_settings': platform-imx-dma.c:(.text+0x9938): undefined reference to `imx6sll_lpddr2_freq_change' platform-imx-dma.c:(.text+0x993c): undefined reference to `imx6sll_lpddr2_freq_change' arch/arm/mach-imx/built-in.o: In function `imx6sl_init_late': platform-imx-dma.c:(.init.text+0xdef0): undefined reference to `imx6sll_cpuidle_init' Signed-off-by: Alejandro Mery <amery@hanoverdisplays.com>
2017-04-19MLK-13801-01 ARM: imx: add gpt_3m clock on imx6sllBai Ping
Add gpt_3m clock source on i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit a0c56a60ea0c0acae0bc8eea75c465eeb11826cd)
2017-02-22MLK-13362-2 ARM: imx: fix audio bus mode hang for imx6dq lpddr2Juan Gutierrez
The double MU count operations should be only done when changing the MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz). Otherwise, the MU count may overflow and lead to system hang/panic issue. This is basically a porting of 4d09bf110b878a6f720ee9d19c8b64ceace95fbe to imx6dq lppdr2. Also a member "freq" has been added to the mmdc_settings_info structure to store the current ddr frequency on iram settings to be able to execute the double MU count, only on 400MHz mode and bypass the operation otherwise within the update freq routine. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-02-20MLK-13281-2 ARM: imx: missing brackets on phy checking for 6sxJuan Gutierrez
Adding the corresponding brackets were missing when introducing a new phy fixup function. This patch fix it. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-02-08MXSCM-240-4 arm: imx: add missing brackets to mmdc_clk checkJuan Gutierrez
Even though is not affecting the behaviour, the brackets are missing to limit this check for imx6q as was intended in first place Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-02-08MLK-13894 ARM: imx: Add low power run voltage change support on i.mx6ullBai Ping
Drop the VDD_SOC and VDD_ARM voltage to 0.9V when system runs at low power run mode. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 65517808712fcd4c5cb3b81a5d8714929957e49c)
2017-02-08MLK-13601-02 ARM: imx: Add fuse check support for imx6ullBai Ping
On i.MX6ULL, some part can run at 1GHz or 800MHz setpoint. we need to use the speed grading fuse to disable the unsupported setpoint. speed grading fuse define as below: 2'b00: Reserved; 2'b01: 528MHz; 2'b10: 792MHz; 2b'11: 996Mhz; Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-01-31MXSCM-243-2 arm: imx6q: mmdc handshake for lpddr2 2ch-mode on low-powerJuan Gutierrez
For i.mx6q systems the mmdc handshake on channel 0 is kept enabled (while channel 1 is bypassed). This is ok for lpddr2 systems operating on 1ch-mode, but not true for 2ch-mode. On this case the handshake needs to be set for both channels, otherwise a kernel panic or Oops error might be observed after resuming from suspend. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-31MXSCM-243-1 arm: imx: get the mmdc 2ch-mode api for lpddr2Juan Gutierrez
To configure the suspend settings for lpddr2 systems is necessary to know if mmdc is operating on 1ch-mode or 2ch-mode. Here, the imx_get_lpddr2_2ch_mode api is introduced to get this info when needed and decide accordingly. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-26MXSCM-240-3 arm: imx: set CLK_GET_RATE_NOCACHE flag for clock dividersJuan Gutierrez
Using the CLK_GET_RATE_NOCACHE flag on the clock dividers will allow the recalculation of the rate instead of just caching its value. For instance, this allows the mmdc clock to be properly updated, after being modified by the busfreq driver, within an iram routine by calling the clk_get_rate api. Using this flag allows to call only to the .recalc_rate functions instead of additionally call the .set_rate ones. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2017-01-26MXSCM-240-1 arm: imx: set mmdc clk rate on high audio freq on i.mx6q lpddr2Juan Gutierrez
As periph_pre_clk's parent is not changed when going to high audio frequency, the clk framework will not update its children's frequency. This cause the the mmdc_ch0_axi clk_rate does not reflect the right frequency when reading it from userspace like: cat /sys/kernel/debug/clk/mmdc_ch0_axi/clk_rate Since the mmdc_ch0_axi_podf is changed in the asm busfreq routine, then the mmdc rate needs to be updated to make sure clk tree is right, although it will not do any change to hardware. To do this the clk_get_rate api is used to update the mmdc_clk which needs to be dereferenced from the device tree. Since for other cases like ddr3, the update of the rate of the mmdc clk is not needed, the absense of this parameter (on the device tree) don't make throw an error, instead, NULL checks are used to check if the mmdc clk needs to be updated or not. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-20MXSCM-241-2 arm: imx: coherency issues after updating lpddr2 busfreqJuan Gutierrez
After a frequency transition, like 400MHz to 24Mhz, on i.mx6DQ SCM systems (which use lpddr2), the curr_ddr_rate variable retains its previous cached value causing the next frequency update transition to fail by following a wrong flow which results in a complete hang of the system. Issuing an L1 cache flush during the freq update routine (as in in MXSCM-241-1) and moving up the curr_ddr_rate variable before calling tge freq update alleviates the problem. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-20MXSCM-242-1 arm: imx6q: flush and disable L1 before L2 on lpddr2 for i.mx6qJuan Gutierrez
Flush and disable L1 before disabling L2, to let data to be coherent. Flushing L1 pushes everyhting to L2. L2 is sync later, but it can still have dirty lines. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-19MLK-13774 ARM: imx: fix lpddr2 busfreq support on i.mx6ullBai Ping
Fix busfreq support on i.MX6ULL LPDDR2 board. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 4306d7689b330d67ccf6586e365465f217d3df09)
2016-12-21MLK-13484 ARM: imx: imx6ul: add PHY KSZ8081 new silicon revision fixup settingAndy Duan
The previous code only support i.MX6UL EVK RevA, RevB, RevC PHY KSZ8081 with fixed silicon revision. Different silicon revision may have different phy fixup init setting. i.MX6UL EVK RevC1 apdate new silicon revision PHY. After debug and tune, the revision still need the same phyfix setting. So, add Ethernet PHY KSZ8081 new silicon revision fixup setting. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit: 15c759347681b65fa33986f0fc5687a374d9f3a1)
2016-12-19MLK-13616 ARM: imx: Add low power run voltage change support on i.MX6SLLBai Ping
On i.MX6SLL, if all PLLs is bypassed in low power run mode, we can decrease the VDD_ARM_IN and VDD_SOC_IN voltage to 0.925V to save power. a 25mV margin is added to cover IR drop and board tolerance. Add low power run voltage change support for i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 3b9da6e8b867ee59c81314d3e08af60053a5855d)
2016-12-08MXSCM-217 imx: keep weak 2p5 power up when ENET WOL wakeup is enabledJuan Gutierrez
When ENET wake up is enabled by wake-on-lan (WOL), the weak 2P5 ldo needs to keep power up even for LPDDR2 due to the ENET_PLL is feed by the weak 2p5 ldo during DSM. If the weak 2P5 ldo is power down the ENET module is power off hence it is not able to sense the WOL interrupt and trigger the system resume. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2016-11-21MLK-13497 clock: make an accurate pixel cock rate for epdc on i.mx6sllRobby Cai
change parent clock to pll3_pfd2 and calculate out a desired pixel clock rate. This patch fixed the following warning. "imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412" Signed-off-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit 76a336b931a74605caa94ca82c7b8343d604fee6)
2016-11-16MLK-13384 ARM: imx: remove ldo bypass check on imx6sllBai Ping
As on i.MX6SLL, there is no ARM LDO, the code for ARM LDO bypass check is unnecessary, remove these piece of code in i.MX6SLL low power idle. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit be3df9ec9b68574b5a319009fa6f37c105d6b771)
2016-11-16MLK-13362 ARM: imx: fix audio bus mode hang on imx6sx/ul/sllBai Ping
When MMDC runs at a low frequency, it is not recommended to perform "force measurement", the MMDC measure unit may return a wrong measurement value when running below 100MHz. Additionally, the double MU count operations should be only done when changing the MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz). Otherwise, the MU count may overflow and lead to system hang issue. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 4d09bf110b878a6f720ee9d19c8b64ceace95fbe)
2016-11-16MLK-13344-05 ARM: imx: Add cpuidle support on imx6sllBai Ping
Add low power idle support on i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 26de2bb5e8ddef4f1562cc5e6001bfc0027106f0)
2016-11-16MLK-13344-04 ARM: imx: Add busfreq support on imx6sllBai Ping
Add bufreq driver support on i.MX6SLL. For i.MX6SLL, it only support LPDDR2 and LPDDR3. the DDR clock change flow is same on these two type of DDR. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 8479afb4e7c52c6de1bedefb00a7cea4320fc14d)
2016-11-16MLK-13344-01 ARM: imx: Change AXI and AHB clock rate on imx6sllBai Ping
Increase the AXI and AHB clock rate on i.MX6SLL according to the RM to improve the system bus performance. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 1bbfc89fa5ecf644115cac878bd8fd7ed10b988c)
2016-11-16MLK-13343-1: ARM: imx: clk: Add extern audio clock in imx6sllShengjiu Wang
add extern audio clock in imx6sll clock tree Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> (cherry picked from commit c23203e1247c94ee154e8f04925eb1d659465229)
2016-11-16MLK-13333-3 ARM: imx: enable bus clock auto gating for i.mx6sllAnson Huang
i.MX6SLL has new hardware function of bus auto clock gating, whenerve bus is idle, its clock will be auto gated to save power, enable this function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 857b0c9bb240805662bacbdcad963779848621bb)
2016-11-16MLK-13333-1 ARM: imx: correct i.mx6sll dram io low power modeAnson Huang
i.MX6SLL has different DRAM IO offset, and it has no CAS/RAS/ODT/RESET pin now, correct the DRAM IO offset. To better support all different i.MX6 SoCs and different DRAM types, introduce a new column to store the low power settings for DRAM IO, then suspend asm code no need to check SoC or DRAM type, just get the DRAM IO's low power settings from OCRAM pm_info and set to each DRAM IO. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 00f51e3c882b7674d26954fdf421e8e3824c3ed5)
2016-11-16MLK-13309-01 ARM: imx: clear the L2_PGE bit on imx6sllBai Ping
On i.MX6SLL, the 'L2_PGE' bit in GPC CNTR register is set by default,this bit must be clear, otherwise, system will failed to resume from DSM mode if L2 cache is enabled. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit c463f044d77ca4b3442013f4f5c3b464fb64f029)
2016-11-16MLK-13306-2 ARM: imx: update MMDC restore settings for i.mx6sllAnson Huang
i.MX6SLL LPDDR3 script v1.2 is released, update MMDC restore settings accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 45ffeee7a34c5ca54d46722850a8917d0cfc8cd3)
2016-11-16MLK-13306-1 ARM: imx: correct ddr type for i.mx6sllAnson Huang
For MMDC, LPDDR3 type's value is 2b'11, which is different from DDRC, so correct it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 80c543452d9d66f03b84fe31ca3d6e7bbdf28603)
2016-11-16MLK-13303-11 ARM: imx: add cpufreq support for i.mx6sllAnson Huang
Add cpufreq support for i.MX6SLL, uses i.MX6SL's opp table for now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 750c04596f178dff20408ef7c371fb18134f1a43)
2016-11-16MLK-13303-10 ARM: imx: add DSM mode support for i.mx6sllAnson Huang
Add DSM mode support for i.MX6SLL, Mega/Fast mix can be off now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 408d72246b5e28f2a69e0d4559e414921ae7a4e3)
2016-11-16MLK-13303-8 ARM: imx: add i.mx6sll msl supportAnson Huang
Add i.MX6SLL MSL support, machine code reuses i.MX6SL. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit f834656e5fcc3338c4fb35b2908d98cf3313b0a9)
2016-11-16MLK-13303-7 ARM: imx: add gpt timer support for i.mx6sllAnson Huang
Add i.MX6SLL GPT timer support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 44b5e3b1252a5c82f1332a5bf17877558c50cae4)
2016-11-16MLK-13303-5 ARM: imx: add clock driver for i.mx6sllAnson Huang
Add clock driver for i.MX6SLL. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> (cherry picked from commit 06100a0ca8733700c42d66ce6bb91ca941db9222)
2016-11-04MLK-13281 ARM: imx: add micrel phy init for 6sxscm evb boardAlejandro Sierra
Add Micrel phy initialization for imx6sxscm evb platform Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2016-11-04MLK-13280 ARM: imx: missing mmdc read fifo reset on resumeJuan Gutierrez
When a device like (USB, CAMM, tty, etc) prevents the megamix domain to power down during the suspend process (by enabling a wakeup source) the resume process goes through a path where the MMDC context should not be restored. However this resume path does not reset the read fifo MMDCx_MPDGCTRL0[RST_RD_FIFO] for the platforms with LPDDR2 causing a bad resuming and reset of the device due to an exception. This patch adds the reset_read_fifo on the No-restoring-MMDC path to fix the bad resuming. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2016-11-04MLK-13279 rpmsg: imx: make vring address configurable by dtsJuan Gutierrez
vring memory address was hardcoded at the top of the 1GB RAM. For systems with a memory map with less or different than 1GB, the hardcoded value might be not correct and cause issues. This patch add the support to pass the vring address from device tree configuration on the reg platform argument in the following format: reg = <vring_address vring_size> For example, for a 512MB system, with the rpmgs vring placed at top of the memory the configuration will look like below: &rpmsg{ reg = <0x9FFF0000 0x8000>; }; Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2016-10-26MLK-13387-4 ARM: imx: gpcv2: correct pcie phy reg notifierRichard Zhu
1.8v of imx7d pcie phy, should be turned on after the 1p0d(1.0v) of pcie phy is turned on. And turned off before the 1p0d(1.0v) of pcie phy is turned off Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> (cherry picked from commit ee97d82dad19d04e30d482a08923c2e11c629b1f)
2016-10-20MLK-13361-3 arm: imx6q: busfreq: restore mmdc timing settings for 100MHzJuan Gutierrez
The timing settings for 100MHz are almost the same as the ones for 400MHz except for the MMDCx_MISC[RALAT] parameter which needs to be set to 2 cycles. For the 100MHz case the restoration of the mmdc setting should be performed in 2 steps: restore the mmdc setting and then overwrite the RALAT setting for 2 cycles. A decision code within the "mmdc_clk_lower_equal_100MHz" macro is added to go to the "equal to 100MHz" or to the "lower to 100MHz" case Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Lozano <alejandro.lozano@nxp.com>
2016-10-20MLK-13361-2 arm: imx6q: busfreq: wrap ralat settings on a macroJuan Gutierrez
Setting the Read Additional Latency (RALAT) to 2 cycles, MMDCx_MDMISC[RALAT] = 2, is needed for 24MHz operation point. Currently this is set within the "set_timings_below_100MHz_operation" macro, which is use for the 24MHz case. In order to provide a generic way for setting RALAT=2 the code is wrapped in this new macro: "set_mmdc_misc_ralat_2_cycles", so other set points (besides the below 100MHz case) can reuse this code. As an example, for 100Mhz operation the RALAT should be set to 2 cycles, however, the rest of the MMDCFG parameter are not the same as in the "below_100MHz" case. So, this macro can be reused for its RALAT part. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2016-10-20MLK-13361-1 arm: imx6q: busfreq: rename 100MHz-related macrosJuan Gutierrez
Two macros are renamed: 1) set_timings_above_100MHz_operation as restore_mmdc_settings_info 2) mmdc_clk_lower_100MHz as mmdc_clk_lower_equal_100MHz For (1) the operation is generic to several cases and not just related (at least on a semantic way) with the operations "above" 100MHz Renamed as restore_mmdc_settings_info the macro can be reused for the other cases like equal to 100MHz and possibly other intermediate operation points. For (2), the macro is renamed as mmdc_clk_lower_equal_100MHz to reflect that this macro handles both the "lower than 100 MHz" case and the "equal to 100MHz" case. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2016-09-19MLK-13243: arm: imx6q: busfreq: lpddr2 fix system clocks audio modeAdrian Alonso
Fix system clock topology used by lpddr2 for audio mode Keep pll2_pfd2 as clock root for periph_pre_clk to match lpddr2_freq_imx6q.S switching mechanism. (Rework from commit id 427b1b6d628827ca83887b92c8331a261a254151) Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry pick from commit 583b09e4d30ec0ce3b3a0494ebd0419d05701ce2)
2016-09-15MLK-13240: arm: imx6q: lpddr2 freq fix switch to 100MhzAdrian Alonso
Fix switch_to_100Mhz miss to store updated podf dividers for system clocks running at 100Mhz (audio mode) Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry picked from commit f54f8c9e1fbb0c937c3ad2e0867ccc2d4d50e77a)
2016-09-15MLK-13147: arm: imx6q: lpddr2 freq simplify system clock sourcesAdrian Alonso
Simplify system root clock sources, only use pll2_pfd2 and osc for system clocks, when busfreq request high bus mode or audio bus mode only update dividers to achieve operating frequencies from same source (pll2_pfd2). Bus freq mode (400M) (100M) (24Mhz) mmdc_ch0_clk_root @396MHz @99MHz @24Mhz axi_clk_root @198MHz @49.5MHz @24Mhz ahb_clk_root @132MHz @49.5Mhz @24Mhz ipg_clk_root @66MHz @24.75Mhz @12Mhz Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry pick from commit c85924790d0e3d4dd2bc86c088f363853ea4af91)
2016-09-12MLK-13186-3 arm: clk: configure pcie ext osc clkRichard Zhu
When the external oscillator is used as pcie ref clk. the below configurations should done. - set the lvds_clk1 as input - set the source of the pll6_bypass to be lvds_clk1 - set the pll6 to be bypass mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> (cherry picked from commit c45c230b7f488dcf18b715129852d27c24c849e6)
2016-08-25MLK-13119-2 ARM: imx: support VPU 396MHz for i.MX6QP 1.2GHzAnson Huang
When i.MX6QP with speed grading fuse blown to 1.2GHz, VPU should run at 396MHz, add this support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-08-24MLK-13101 ARM: imx: correct the pll2's clock type on imx6slBai Ping
On i,MX6SL, no NUM and DENUM register, so this PLL should not be registered as IMX_PLLV3_GENERIC type PLL, it should be registered as IMX_PLLV3_SYSV2. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2016-08-10MLK-13062 arm: imx: correct PLL2 rate calculationAnson Huang
As i.MX6's PLL2 also support a fractional-N synthesizer, so we need to consider the NUM and DENOM's value to get a correct rate, as fraction may be used in some cases. Remove round_rate and set_rate for PLL2, as it is NOT allowed to be changed in kernel dynamically, otherwise, PFDs and DDR may NOT work normally, it normally should be changed in u-boot before DDR is enabled. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-08-02MLK-12978: arm: clk: i.MX6SX set lcdif2 pixel clk parent to ldb_di0Sandor Yu
i.MX6SX LDB will connect to LCDIF2. And LCDIF2 pixel clock can not re-parent when it's on. So default setting clock parent to ldb_di0. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2016-06-23MLK-12935 ARM: imx: switch system counter clock to 32K in suspendAnson Huang
During suspend, as 24MHz will be disabled, but system counter needs to be running in order to maintain accurate clock source, so we need to switch system counter's clock from base clock(24MHz) to alternate clock(32K) before system enter STOP mode, otherwise, the suspend time will NOT be counted into system time when issue a "date" command. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 470f930321d7633ea9844a1ebf6784cafd8b7372)
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