Age | Commit message (Expand) | Author |
---|---|---|
2011-08-01 | ENGR00139531: MX5x-All bus-masters must have DDR clock as a dependent clock. | Ranjani Vaidyanathan |
2011-01-17 | ENGR00132139 MX50: Set DDR to 24MHz in LPAPM mode | Ranjani Vaidyanathan |
2011-01-17 | ENGR00127147: MX50: Add support for Automatic Low Power Mode on DDR | Ranjani Vaidyanathan |