Age | Commit message (Expand) | Author |
---|---|---|
2011-12-13 | ENGR00170141: Fix debug messages generated by CPUFREQ | Ranjani Vaidyanathan |
2011-11-17 | ENGR00162319: MX6 - Add support for updated VDDARM voltages | Ranjani Vaidyanathan |
2011-11-16 | ENGR00162460:MX6-Revert "MX6-Disable PLL1 when CPU clk is below 400MHz." | Ranjani Vaidyanathan |
2011-10-27 | ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz. | Ranjani Vaidyanathan |
2011-10-13 | ENGR00159641: MX6-Add DVFS-CORE support | Ranjani Vaidyanathan |
2011-10-13 | ENGR00159959: MX6-Updated CPU voltages for different frequencies | Ranjani Vaidyanathan |
2011-08-30 | ENGR00139280: MX6: Add CPUFREQ support | Ranjani Vaidyanathan |