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Several file names and paths showed copy/paste or otherwise issues.
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Bug 862502
Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722
Reviewed-on: http://git-master/r/47398
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef
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Add support for forced Tegra3 LP2 low power mode on the boot processor
(CPU 0) via the cluster control interface when all others are offline.
Switching to the LP CPU mode is also enabled with this change.
LP2 in idle and LP2 mode on the secondary processors is not yet
supported.
Change-Id: Icb898729f093be5e006c413f701532dd45228687
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
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The movw/movt instruction pair (encapsulated by the mov32 macro)
is preferred over literals for loading addresses. The use of literals
for singleton data accesses can cause unnecessary cache misses and
evictions for cache lines that are unlikely to be accessed again in
the near future. Furthermore, certain code sequences must refrain
from using data accesses. Therefore, in general, addresses should
be loaded by mov32.
Change-Id: I9bcc3ee191f882996197ce2edc0eb510d4ff7b4a
Reviewed-on: http://git-master/r/40460
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R7ddd0d9b1e2fc8ab653b9220388acbecdbf4c57f
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