Age | Commit message (Collapse) | Author |
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select emc evfs table based on DDR present
using RAMCODE
Bug 200195279
Change-Id: I7fbc693383c9e231b2c2119020eebc7bba544c6e
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/1144528
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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CD575MI:
Max GPU freq is set to 852Mhz for 4/4/16
cpu_g powered by pllx is set to 1.5 and 1.8Ghz below 0 degC
Enable SOC dvfs for default personality
CD575M:
Lower CPU freq to 1912Mhz @ Max 1.12V
Lower GPU freq to 804Mhz @ Max 1.90V
Bug 1563635
Change-Id: Ib33f34fe2c0580d0f750de40f68560031f7266b0
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/711627
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Updated dvfs table for Jetson-tk1 2GB
Bug 200028708
Change-Id: Ia6000916ca7388b6c5f17af6f399a4b11a0ed650
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/495978
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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If memtype from boardid eeprom is 1, then only load
emc dvfs for 4GB
Bug 1541809
Change-Id: I82b7b40b738308504cf9c88be0fc02d067d22d21
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/455952
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Mike Thompson <mikthompson@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Add machine support for t132 pm375.
bug 1522642
Change-Id: I842150ecccb722a93b7b80b3c87dcf1ceb13e7b5
Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440518
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Mike Thompson <mikthompson@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Update DVFS table for PM359 from V1 to V2. The main difference between V2 and V1
is due to the emc_reg_calc update from V6.0.0 to V6.0.4.
- Disable SEL_DPD on MID package
- Increase tR2p by 2 for 102MHz CFG
Bug 1427416
Change-Id: I3199fa8a2118b92bc7f5e8c8cf14c0e0e48d2527
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/417882
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Update the emc dvfs table
Bug 200004533
Change-Id: Iae708a77150ac04c88708c5e3f495301bb029c22
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/409191
(cherry picked from commit 3c68fa97fa27af944b2cac20ab30aaa1a23ec35c)
Reviewed-on: http://git-master/r/411913
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Change-Id: I0221c4172d1bbcc1b864aa041e684f10cb416909
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: http://git-master/r/408970
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Change-Id: I4dc22e8a7878c1f90798d6e8d013af6f0b48cb5d
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: http://git-master/r/403722
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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- Load the emc tables from Device Tree by default.
- This is only if memory-controller node representing the
emc-table is available in the Device Tree.
Change-Id: I49d414bddd7b9af1bc45f671bb6d29f46c103783
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: http://git-master/r/391035
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
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Add EMC DVFS table for PM375
Bug 1454434
Change-Id: I83ef7cfcf65f5d1a4b7e7a711e6373e249439e34
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
(cherry picked from commit 68d11631a811113c2d8230b7a0ce3f85f718fb66)
Reviewed-on: http://git-master/r/391872
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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DVFS table modified for PM359 to update entry for
204 and removed entry for 102.
Bug 1427416
Change-Id: I033254cdb825cb6cb95679089f152630b4bfb707
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/386465
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
Tested-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
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Add derated tables for E1792 and load emc
and derated tables from DT for E1791
Bug 1350759
Reviewed-on: http://git-master/r/#/c/384528/
Change-Id: I10bf2d7a232d954cb67401f6567836db0b8511c2
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/387407
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Some Tegra12 EMC DVFS table entries were missing the "expected dvfs
latency (ns)" field. Add this missing field for those entries.
Bug 1327082
Change-Id: I30f4ac2865bb6c0a54a888107d1d84e703509d26
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/379103
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
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There are two tegra_emc.h files; this patch renames the platform
data header to "tegra_emc_pdata.h" to avoid confusion.
Change-Id: I8160682823ec4fcb7c9a883bfc10285d3cc91551
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/376788
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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Add EMC DVFS table for T132 Laguna-ERS-S (PM359)
bug 1427416
bug 1465179
Change-Id: I4ee60ed681dc5ebacc6ec0d8f01d9bf442956650
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/370033
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Bug 1340913
Change-Id: I2bd353042cb230051ad3dfbcaf03fafd50d0c363
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/355312
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: Ica0708ad3abe0c43e7883e4e03b7ec06290e1015
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/355317
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I806924ddc9a7c5f409d6f587becaa6f9bf8c8b9d
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/356808
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Add EMC DVFS table for Laguna-ERS-S (PM359)
bug 1354315
Change-Id: Ida20f7797589559498db04df144e91e7c65f0588
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/357059
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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2GB emc dvfs table was using 4GB table
add latency register to e1780 emc tables.
Bug 1340913
Reviewed-on: http://git-master/r/354768
(cherry picked from commit eab2732013e388453fb8af98b76164ec2bdba6f2)
Change-Id: I0bd5ff7a5795f75b7c961cb67ad856b250f3d929
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/354770
GVS: Gerrit_Virtual_Submit
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Fix various warnings to enable -Werror option.
Bug 1211919
Change-Id: I913728fd3f2cbac0243b4e116c53cb035ed17f35
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/354292
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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bug 1430981
Change-Id: I1ed7f62d7779375abbb5b9469c96c34ce96f58e6
Signed-off-by: Leo He <leoh@nvidia.com>
Reviewed-on: http://git-master/r/349772
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hunk Lin <hulin@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Bug 1340913
Change-Id: If591be04d3606155e03a8e9af9f9379a369091b3
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/351546
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Change-Id: I1c8c11f793c3577b4cbf93c52ea46cc1659a25f8
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/345626
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I5880df9df3687253e226065a60442863e1039234
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/345642
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I7afb4b877ce069d9ed579866bb757c9f1cec89d4
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/345640
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I710e6f04758a4dcd8c62dbb9c2dd79bf73e8e63a
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/345638
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: Iaee1f380644460e8ac71a8651a7af5373d402879
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/348110
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Bug 1417585
Change-Id: Ib82e3ef2d3b27685313688e8642c2cf4ce3a19a1
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/347754
Reviewed-by: Robert Shih <rshih@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Bug 1417887
Change-Id: I57bc4236c3d2cab1e0c5a916e29fde5431b42501
Signed-off-by: Eric Chuang <echuang@nvidia.com>
Reviewed-on: http://git-master/r/339376
Reviewed-by: Robert Shih <rshih@nvidia.com>
Tested-by: Robert Shih <rshih@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ryane Luo <ryanel@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I6616fc74aa1c94461c6718c92c6779da4082ac3e
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/334789
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I98d72c3c033410542389447018549132266026ef
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Change-Id: If2ab30db6b7d25f61f083ba4bf67606a9d7c6635
Reviewed-on: http://git-master/r/343803
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I118fd7a6b0f6a7cd11e7ae97337f515827b16ca3
Signed-off-by: Anshuman Nath Kar <anshumank@nvidia.com>
Reviewed-on: http://git-master/r/338897
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I02c1995c4eca89d09ffe12fc562013f8ecf536b1
Signed-off-by: Ryane Luo <ryanel@nvidia.com>
Reviewed-on: http://git-master/r/339771
Reviewed-by: Hayden Du <haydend@nvidia.com>
Tested-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Bug 1340913
Change-Id: I8d99a0a35d7f9ee3399bb8530e5ece6a65ef4ea7
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/337968
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bug 1350759
bug 1340913
Change-Id: I65bbb1e6592e00afa0d6aac00839a229cdb9e2c4
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/337573
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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This reverts commit 56bd22350af077f07e438254afad6a4c1fb65fbf.
- Change 56bd2235 is dependent on EMC table 0x18 support, which
is being reverted
Change-Id: I2237a6a70f140eb7d59e8662d22062ed2a3ba6d8
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/336439
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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bug 1409572
Change-Id: I317341d2b8ac43947322e16bdc01147946735c37
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/332589
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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bug 1350759
bug 1340913
Change-Id: I75c04442e0ff6f0913bb2821c4f07e139cbf92cd
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/332574
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Device will auto register by device tree.
Bug 1373423
Change-Id: I4edb790d262712d6a3daa2b9afc43b6d8b7a0325
Signed-off-by: Ryane Luo <ryanel@nvidia.com>
Reviewed-on: http://git-master/r/309554
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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Rearrange parsing of dt nodes of emc tables
Add emc dvfs tables for tn8 ers
Bug 1360455
Change-Id: I21a81a67d315bba9dd7af792ddaebe251dc505cd
Signed-off-by: Ryane Luo <ryanel@nvidia.com>
Reviewed-on: http://git-master/r/299848
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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Bug 1361265
Change-Id: I12b0ee2af4b4a86885cc67b5e6f805c097121659
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/289967
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Adds functionality to load the EMC table from the NCT
partition. If no memory table is in NCT or the NCT
partition doesn't exist, fall back to the built-in table.
Bug 1300925
Change-Id: I09c13443600c987884f67520ca72a7702e052837
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/289290
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Change-Id: Idf5cb03a52261e7f433de24add8bc0edf5ed918f
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/302549
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I212b481d59913f07902935ffe320d112227112a7
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/302475
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Removing unwanted fuse.h header inclusion
Bug 1380004
Change-Id: I6cd7ceac380a6e418705965823f7127ad39dd548
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/299810
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Change-Id: Ic1ff0cf3eb9aada54fdf0c803c430439ce598dfc
Signed-off-by: Xue Dong <xdong@nvidia.com>
(cherry picked from commit 714fffcab30ed95018c03df4743de00a9c8a2d61)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
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Change-Id: I986d261c9a2fc03fcfbce84aec07f281d5721c00
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/270380
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
(cherry picked from commit d2f698c9c653c5098eb5d121038dd362785c8b0e)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
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T124 platforms i.e. Ardbeg, Laguna, TN8 and Loki used only with
T124 SoC and hence config CONFIG_ARCH_TEGRA_12x_SOC is always
enabled for these platforms.
Hence removing of additional macro check from the code to make
code simple.
Change-Id: Ic28c65eef0db9f8d4af57a85ad776de1fbe1f2f1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/265421
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