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2016-05-16arm: tegra: new dvfs update for aging factorBibek Basu
Following support added DVFS for Gauranteed freq considering aging CPU freq limit at higher temperature EDP max current limits for each SKU Bug 200195229 Change-Id: If00f3fd6b891cf366047dda331bd7ab1c15b40f7 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1146577 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-03-14arm: tegra12: dvfs update for embedded SKUBibek Basu
CD575MI: Max GPU freq is set to 852Mhz for 4/4/16 cpu_g powered by pllx is set to 1.5 and 1.8Ghz below 0 degC Enable SOC dvfs for default personality CD575M: Lower CPU freq to 1912Mhz @ Max 1.12V Lower GPU freq to 804Mhz @ Max 1.90V Bug 1563635 Change-Id: Ib33f34fe2c0580d0f750de40f68560031f7266b0 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/711627 GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-12-10arm: tegra12: enable gpu edp capping for jetsonBibek Basu
Enable GPU edp capping for jetson-tk1.Also update the max_cpu_current and max_gpu_current for PM375 Bug 1563635 Change-Id: I165440959ba0f23d102f1d89a6c6e9191329305d Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/590332 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2014-07-04ARM: tegra: ardbeg: Lower E1733 voltage map bottomAlex Frid
Lower E1733 voltage map bottom from 700mV to 650mV on Tegra13 platforms. Change-Id: Id52712f364e67e50fd7a5778d55c36536736c764 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/433758 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Anand Bhatia <anandb@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-06-19arm: tegra: soctherm: fix pskip bypass programDiwakar Tundlam
Fix PSKIP configuration in soctherm for T132 chipset. Bypass ramp rate only in soctherm, but program the similar registers in ccroc the same as before as in soctherm for correct throttling behavior. Also added a clear comment noting the restriction of mapping throttling_depth string and actual throttle depth configuration in T13x due to indirect vector-based throttle selection. Change-Id: I86635101fc61229e54b22db67f134917e6a7e0aa Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/423359 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com>
2014-05-27arm: tegra: Correct throttling name for voltmon_ocHridya
Bug 200006274 Also, removed throttling names for t12x Change-Id: I74fd98d5b41b5c9dff6b1dbc5215ba6d5fc0f4c9 Signed-off-by: Hridya <hvalsaraju@nvidia.com> Reviewed-on: http://git-master/r/412876 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-05-21arm: tegra: Enable Power Features For E1765Hridya
Bug 1513802 Change-Id: I9db782c3f014f7fdef0ae3bc68fd0bca8bd46acf Signed-off-by: Hridya <hvalsaraju@nvidia.com> Reviewed-on: http://git-master/r/409709 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-05-16arm: tegra: enable OC1 and OC4 throttling for PMU1936Diwakar Tundlam
Bug 1436772 Change-Id: I40d2e4c12edebee9e9a17ad06073b698918b694f Reviewed-on: http://git-master/r/397463 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/408924
2014-05-13arm: tegra: thermal: new ATE rev and marginsDiwakar Tundlam
Added check for new ATE rev (0.9+). Added WAR for ATE revs 0.9-0.11 - continue to use PLL-TSOSC for thermals. Updated thermal thresholds and CPU and GPU EDP margins per thermal margins spreadsheet. Bug 1429685 Bug 1510809 Bug 1511626 Change-Id: I78528be0ed6b01625dd464054fbbf39c810c8873 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/407793 Reviewed-by: Automatic_Commit_Validation_User
2014-05-08sysedp: tn8: enable SW feedback for battery OC throttlingTimo Alho
* Enable battery OC hardware throttling on E1971 platform * Enable SW feedback loop on battery OC throttling on all TN8 platforms Bug 1511092 Change-Id: Iedf95e6b139661d5577519728a0fa781b525a341 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/406349 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-05-07arm: tegra: thermal: clean up fuse check apisDiwakar Tundlam
Allow fuse check api to be called only to check the fuse revision. Bug 1429685 Change-Id: I0370f237c4562814af0f41a162bccff2b3db5371 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/405474 Reviewed-on: http://git-master/r/405990 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-02ARM: tegra: add support for E1733-1000-00-F.2Laxman Dewangan
The ams PMIC module E1733-1000-00-F.2 has populated with ams AS3722 version 1V2. Add dts file and dfll register map for this PMIC module support on E1973 Bowmore-ERS-S. bug 1498084 Change-Id: I5b03ed7cf172c313820ff719907cac0c1afd03b6 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/401657 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-04-29ARM: tegra: ardbeg: disable modem OC3 throttlingNeil Patel
The modem assertion of MDM_POWER_REPORT will now trigger a change in EDP state rather than direct CPU/GPU throttling. Bug 1468546 Change-Id: I69da7daa37929b36de881d966ca78ba30de0b7d4 Signed-off-by: Neil Patel <neilp@nvidia.com> Reviewed-on: http://git-master/r/387828 (cherry picked from commit 3abf162a16cb1693fdfa5e8e4f2ac5ce3d023ff5) Reviewed-on: http://git-master/r/402513 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-04-23ARM: tegra: remove unused macros for TCA6416 and header inclusionLaxman Dewangan
TCA6416 device has been moved to DT for its registration and so it is not require to have macro for this device and header inclusion of this device. Remove the macro and header inclusio from different board source files. Change-Id: I39a06417bc12acdbc8ff430acc7a6a449a0060d8 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/397147
2014-04-23arm: tegra13: CPU and GPU EDP supportDiwakar Tundlam
Update CPU and GPU EDP limits for various T132 platforms. Bug 1434482 Change-Id: I318d0254d7338482d3a8eea9c236838511ab8ce0 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/396112
2014-04-23arm: tegra13: soctherm: use PLL-TSOSC to throttleDiwakar Tundlam
For certain older revs of ATE, we will use use PLL-TSOSC (instead of the CPU-TSOSCs) on T132 devices to drive throttling (HW and SW) and shutdown to avoid random shutdown issues seen on some platforms. Switch to PLL-TSOSC instead of CPU-TSOSC in all t132ref platforms. Bug 1468124 Change-Id: I432676d12c2ad35910f70e9dc8225db5480e6f53 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/396157
2014-04-23drivers: tegra: pmc: change name of struct tegra_tsensor_pmu_dataPaul Walmsley
At Aleks' request, change the name of struct tegra_tsensor_pmu_data, to clarify what it is and what it does. This structure has nothing to do with PMIC temperature sensors. Instead it's used to configure the boot ROM appropriately to tell the PMIC how to power off the SoC after SOC_THERM's critical thermal trip point has been reached ("thermtrip"). The name will now be 'struct tegra_thermtrip_pmic_data'. Change-Id: I40e5aeeb74267993272e33c92300d3506a15a4a8 Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Reviewed-on: http://git-master/r/396170 Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-08ARM: tegra: remove power tree population from board files of ArdbegLaxman Dewangan
Power tree of Ardbeg is moved to DT and hence removing the duplicate power tree from board files. Change-Id: I60c2cec913583352e83c16de7bebfede6a60f9c7 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/392928 GVS: Gerrit_Virtual_Submit
2014-04-04arm: tegra: soctherm: move PMC register accesses into PMC driverPaul Walmsley
The PMC IP block is not part of the SOC_THERM IP block, but the SOC_THERM code contains direct register reads and writes to the PMC IP block. Move these accesses into something PMC-specific: in this case, drivers/platform/tegra/pmc.c. While here, remove the usage of the REG_SET/GET* macros, since upstream Linux practice is to use the actual bit-manipulation operations, rather than these macros. This is part of the process of modifying the tegra11_soctherm.c code to convert it into a low-level device driver for the arsoc_therm IP block. We also relocate struct tegra_tsensor_pmu_data to a PMC-specific header file, since it is PMC-specific, and convert any header references to the old location to point to the new location. Thanks to Matt Longnecker for comments on the first version of this patch. Bug 1201644 Bug 1380438 Bug 1482001 Change-Id: Iea630ac9d9b3dfaab03edf44e2a2725174c7a3d8 Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-on: http://git-master/r/392198 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-03arm: tegra13: CPU HW thermal throttling enableDiwakar Tundlam
Enable soctherm HW throttling for T132 platforms. Bug 1479594 Change-Id: Iadbd45c01372a865eb716b0d8db0a009b0e3a5f9 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/391597 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2014-03-28ARM: tegra: soctherm: Add tegra-dram trip pointIshwarya Balaji Gururajan
Add a trip point for the DRAM temperature polling mechanism. This activates a mechanism in the EMC driver to keep the DRAM operating in spec when it goes above a certain temperature threshold. Bug 1436864 Reviewed-on: http://git-master/r/#/c/379190/ Change-Id: Ib328edafbf7bd3f4c5e9a02771bbd42d9b025508 Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/379183 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
2014-03-26arm: tegra13: thermal: program shutdown for 1761Diwakar Tundlam
Enable thermal shutdown setup on 1761 board having palmas PMIC Change-Id: I91ea59450d5c868ceed99fa8136eac238663e3aa Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/387334
2014-03-26ARM: tegra: move power_supply_extcon to DT for Ardbeg/TN8.Laxman Dewangan
Move power_supply_extcon driver which is used for AC/USB notification to Android to DT and remove related code from board files. Change-Id: I9e97ac155c87324e59b7a0af8299688386fd4ef1 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/387064
2014-03-25ARM: tegra: pmc: deleting pmc.h from mach-tegra/Sumit Singh
Moving the content of pmc.h to linux/tegra-pmc.h and deleting it. Bug 1440573 Change-Id: I54014c58765b99dd99e6aaae22bad8cb9010e79c Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/377592 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-03-21ARM: tegra: move power tree to DT for E1735/E1733 for Shiled-E1780-1000Laxman Dewangan
Move power tree to DT for PMIC module E1735 ad E1733 based Shiled ERS E1780-1000. If power tree do not have the regulator node then use the power tree from board files. Change-Id: I467b8e5e5ef1f584456aa8e2843dc638cbf087ae Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/384297
2014-03-21ARM: tegra: move PMIC interrupt polarity config to pmcLaxman Dewangan
Add API for changing interrupt polarity of PMU_INT on PMC and call it from the board files. This will avoid the duplication of same code. Change-Id: I2ca4515125487f3de6e3b90c0408f09785ca5181 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/384969
2014-03-19ARM: tegra: rewrite power tree registration for different ardbeg fabLaxman Dewangan
use switch-case instead of if-else for power tree registration based on board id. This will it is more readable and create nice platform to move power tree to DT. Change-Id: I800a312f3ad179bc9197cba0b6391e121d214539 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/383865
2014-03-19ARM: tegra13x: move cold/vmin trips to socthermDiwakar Tundlam
Move vmin trip points that boost voltage below cold-temp to soctherm thermal zones on t132 norrin and bowmore (ffd and ers) boards. To support both legacy DVFS and CL-DVFS with vmin/cold trips, we register two cdevs with the same type, bound to the same trip_point and the DVFS back-end knows which one is active to take action. Changed soctherm driver to allow binding multiple cdevs to the same trip_point so the above mechanism works. Bug 1479500 Change-Id: Ibe54a71c6518a0500fec3fc31c95d3d27797e079 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/383354
2014-03-19ARM: tegra: Don't register power_supply_extcon for ardbegChaitanya Bandi
As Shield ERS has Bq2477x and it's power supply is AC adapter, power supply updates happen from Bq2477x driver itself. Bug 1457299 Change-Id: Iec185f42709daf6a4f1235a36605927de4cce8ed Signed-off-by: Chaitanya Bandi <bandik@nvidia.com> Reviewed-on: http://git-master/r/383649 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-03-19ARM: tegra: dt: Move bq2477x registration to DT.Chaitanya Bandi
Moved bq2477x registration to device tree. Change-Id: I68ec28b3a09ce650ea3e850b6660665b641d39eb Signed-off-by: Chaitanya Bandi <bandik@nvidia.com> Reviewed-on: http://git-master/r/381887 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-03-19ARM: tegra: Add en_bat fixed regulator in ardbegChaitanya Bandi
en_bat rail viz. GPIO_PK5 is required to enable a level translator on Ardbeg platforms. Added an entry for the same as a fixed regulator. Change-Id: I4709bd08c445edf59d0da5010db98bb870a5fa76 Signed-off-by: Chaitanya Bandi <bandik@nvidia.com> Reviewed-on: http://git-master/r/381885 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-03-14ARM: tegra: remove fixed regulator init from board file for TN8Laxman Dewangan
the fixed regulators of TN8 is moved to the DT and there is dummy function for the fixed regulator initialisation in board files. Removing this unused code. Change-Id: Ia5bf176945ada7b4e38792d322db035be02aaf27 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/381480 GVS: Gerrit_Virtual_Submit
2014-03-07arm: tegra: ardbeg: enable OC3 throttlingGreg Heinrich
This patch enables OC3 throttling on Ardbeg platform, conditional on Bruce baseband being enabled. Configures soc_therm with 50% throttling for CPU and "medium_throttling" for GPU. Configures GPIO_PK0 I/O as INPUT/PULL_DOWN. bug 1451260 Change-Id: Ib443be161b34827cf8190b737ff15313683ce051 Signed-off-by: Greg Heinrich <gheinrich@nvidia.com> Reviewed-on: http://git-master/r/362941 (cherry picked from commit 5f9322d9d031ce397a458553cb9b14ea98221807) Reviewed-on: http://git-master/r/375585 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Steve Rogers <srogers@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-02-26arm: tegra13: soctherm: Ignore fuse check errorDiwakar Tundlam
Until soctherm fuse calibration and correction data is published, assume all fuse values are valid and initialize soctherm accordingly. Also added PMU board_id check to enable THERMTRIP using palmas PMIC info. Bug 1454792 Change-Id: I28c4693d12fb09360dfc42979ff7b8202f6fbf6b Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> (cherry picked from commit 101d59944e6a1811d6d88e1fe9b341a1dfadac9f)
2014-02-06Patch to set MEMIO to 1.2V for E1971 and E1973Hridya
Change-Id: Id8d12c1ace0d1af40a09e577544c937caa424897 Signed-off-by: Hridya <hvalsaraju@nvidia.com> Reviewed-on: http://git-master/r/361078 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-05ARM: tegra: Support Ardbeg DT variants w/wo DFLL dataAlex Frid
DT variants that are used for Ardbeg platforms with E1735 PMIC module may or may not include DFLL data. To keep functionality intact in the latter case DFLL platform data in Ardbeg board file was retained, but the respective platform devices are registered from board file only if DT DFLL node is not available. Also added a special hook to modify DT for E1767 prototype module that yet to be productized, and does not have separate DT variant. Consolidated E1735 setting for suspend mode in ardbeg_suspend_init() function. Set E1735 regulator idle mode thresholds during regulator initialization. Bug 1442709 Change-Id: I9b2f0db468a86c8b142b88bf0678ced7ccb2f2c2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/362601 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-05arm: tegra: ardbeg: force CAM_1V8_LDO1 to be trueCharles Kong
Force CAM_1V8_LDO1 to remove the ~19mW power leakage at camera i2c lines when camera is off. The power impact of CAM_1V8_LDO1 is ~0.55mW. The idle battery power is also dropped by this change. Bug: 1441261 Change-Id: I690b6e71d0935242dcb8211fd291c2d43441ec20 Signed-off-by: Charles Kong <charlesk@nvidia.com> Reviewed-on: http://git-master/r/363528 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-04ARM: tegra12: update thermal margins for POP pkgHyungwoo Yang
update thermal margins for T124 POP package. Bug 1447319 Change-Id: I278430c024352cbda836edf4acb6377a590097c7 Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Reviewed-on: http://git-master/r/362164 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-02-04arm: tegra: tn8: change voltmon (OC1) throttlingTimo Alho
Change OC1 (voltage monitor) throttling parameters on P1761 platforms. New values: - Throttling depth 75% - Ramp rate 3.76us While at it, also fix voltmon_oc1 and batmon_oc4 structures to be static. Bug 1444676 Change-Id: I2dee90db845b71704abc9e77c119081c2964332b Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/359870 (cherry picked from commit 3a13c642841f8c2b6819b012079769c7d2b752df) Reviewed-on: http://git-master/r/362847 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
2014-02-03Revert "ARM: tegra: power: Add VDD_GPU SiMon consumer"Alex Frid
This reverts commit 84169083f38a0b7b5e9282d0f095701059d51be9. No need for direct consumers, since SiMon registration for vdd_gpu notification has been moved to common DVFS rail interface. Bug 1343366 Change-Id: Ie2652ffc50a028a110984d88e356d1c10b403156 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/360766 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30arm: tegra: TN8: Reactive cap on volt comparatorSteve Rogers
This change adds two changes: 1. Set the IRQ to fire if we see 100 trips within 100 ms. 2. When the IRQ fires, we'll use reactive capping to reduce the total AP+DRAM budget. Bug 1444676 Change-Id: I9827e125ef23c1b984bb0faba8a7811bbde74501 Signed-off-by: Steve Rogers <srogers@nvidia.com> Reviewed-on: http://git-master/r/359936 (cherry picked from commit ecf1b186c4eb0aafd1d20926a8998824e86e2f2f) Reviewed-on: http://git-master/r/361477 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
2014-01-29ARM: tegra12: Remove PWM voltage map from DFLL dataAlex Frid
Removed PWM voltage map from DFLL platform data on Ardbeg and Loki boards. Replaced it with duty-cycle conversion coefficients that are used by the CL-DVFS driver to recreate maps during probe. Moved DFLL bypass regulator initial voltage from map calculation to regulator definition macro. Bug 1442709 Change-Id: I5abd27c610a02b9ab924df56559760bfe9711156 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/358933 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-29ARM: tegra12: Move DFLL bypass device registrationAlex Frid
Moved registration of DFLL bypass device from CL-DVFS driver probe to board regulator init. Thus the initialization/probe order of DFLL bypass device and driver, CL-DVFS driver and legacy DVFS is now the same as if all devices are defined in device tree (although DT is not used, yet). With changed order, set initial voltage for DFLL bypass regulator constraints to boot (rather than nominal) level. Bug 1442709 Change-Id: I96e8b38c1f3969e7e46913ef659fe49bb81892c4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/358586 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-29ARM: tegra: Remove DFLL data from TN8 board filesAlex Frid
Removed DFLL static platform data from TN8 board files, so that CL-DVFS driver will use DT binding instead. Appended auxdata lookup table to keep compatible device name. Bug 1442709 Change-Id: I88a1acd4db82adaa11da0ae928afe997d7e3b91a Signed-off-by: Alex Frid <afrid@nvidia.com>
2014-01-21Tegra13: DVFS: Update for adding separate dvfs and speedo fileKrishna Sitaraman
Update Makefile and other supporting files for adding separate dvfs and speedo files Change-Id: Ifb7f9baa596a413164da7b3491f621820c9d9d88 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/350003 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21arm: tegra: norrin: Enable interrupt on TCA6416Johnny Qiu
Bug 1405054 Change-Id: I290a6089a3663e451d873939ec092359913116f8 Signed-off-by: Johnny Qiu <joqiu@nvidia.com> Reviewed-on: http://git-master/r/345158 Tested-by: Hayden Du <haydend@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-18ARM: tegra: remove non-required header inclusionLaxman Dewangan
Remove non-required header include as linux/pca954x.h from different board files. Change-Id: Ied77ac30a3bed5c320fd2159724788b78aa7324c Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/357110
2014-01-17ARM: Tegra12: TN8: Add Vmin trips pointsDaniel Fu
As TN8-FFD won't use NCT72 for thermal. Add the Vmin trips points of CPU,GPU,PLL for TN8-FFD. Bug 1430981 Change-Id: Ia754da4cbd6731ee01f5b39b6faeb74775bca711 Signed-off-by: Daniel Fu <danifu@nvidia.com> Reviewed-on: http://git-master/r/356007 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-15ARM: tegra: move power mon i2c-mux device registration to DTLaxman Dewangan
Move power monitor i2x mux device registration to DT and remove the board-file registration. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: Ia6790690934be8ec87082e0853ce30398f68adce Reviewed-on: http://git-master/r/354257 GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-01-14arm: tegra: p1761: enable OC1 throttlingTimo Alho
This patch enables soc_therm OC1 throttling on p1761 platform - Configure soc_therm with 75% for CPU and "medium_throttling" for GPU - Configure KB_ROW15 as input with PULL-UP Change-Id: I8c8f597b8b62c77099ea43cf14362a6a5197f622 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/354260 GVS: Gerrit_Virtual_Submit Reviewed-by: Steve Rogers <srogers@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Vandana Bansal <vandanab@nvidia.com> Tested-by: Vandana Bansal <vandanab@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 09:08:28 +0000