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Using SPI1/SPI2 as initial pinmux for gpio X5/6 affecting spi
controller. GMI A26/27 can be pinmuxed for SPI1_CS0 and SPI1_SCK balls.
It will not affect GMI behavior because A26/27 presently not used on
p1852.
bug 927551
bug 875873
Reviewed-on: http://git-master/r/90551
(cherry-picked from 8b0123f835a671072b23abbe4fdb9d9aa16463cb)
Change-Id: If39c93daa7d1b73777b56c729b0c9b9149770440
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/92499
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gerrit_Virtual_Submit
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Currently the GPIO that we are trying to use for therm_alert is
GPIO_PW2 which is incorrect. The GPIO we ought to use is GPIO_PW3.
Bug 920368.
(cherry picked from commit ad4714c486c6a734681287ea4d85869f05704397)
Change-Id: If1a8cf4b8cdbdd69f2d01f4c292775d413384bc0
Reviewed-on: http://git-master/r/#change,74273
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/91730
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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+ Enable uart4 and remove spi4
+ use SPI2 instead of SPI1 as initial pinmux for gpio x5/6
bug 933971
Reviewed-on: http://git-master/r/78718
(cherry picked from commit 7135fbe5edf7357384dc92b613ea46dc927d6b06)
Change-Id: I46d3072dd160d7a2d1f11f949cc934fbdff1e0a6
Reviewed-on: http://git-master/r/91234
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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bug 871603
P1852 is a T30 based Automotive platform.
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/72253
(cherry picked from commit 98d50016e70a22ae7e8e109cfb6633a8fe75f905)
Change-Id: Iede9881fc1168bb6802694e233554d84adfb8f44
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/79981
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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