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2014-03-14ARM: tegra: remove CONFIG_USE_SECURE_KERNEL usageVarun Wadekar
Remove the config variable usage from the kernel and make the secure firmware check dynamic. This make LP1 resume tricky since we need to execute out of TZRAM till SDRAM is out of self-refresh. To fix this, store secure firmware presence bit in TZRAM during boot. Bug 1475528 Change-Id: Ic18766bbee14626e8cf092363d57f4d98b44b6df Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/377616
2014-03-14arm: tegra: use PSCI interfacesVarun Wadekar
ARM defines PSCI interfaces to be used for power states. We have been using the actual semantics for quite some time now and so can remove our implementation of the SMC issuing code and use the generic interfaces present in <arm/arm64>/kernel/psci.c. Bug 1475528 Change-Id: Ieba8a0a54f5ee731626e7d92a767ef044e88f12d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/378354
2014-02-12ARM: tegra: Return the actual idle stateSai Gurrappadi
MC clock stop and powergating use the same powerdown function so it is possible to request power_down(state=2) but end up powergating (state=1). This causes faulty updating of residency times. Fix this by returning the actual idle state entered instead of returning true/false. Bug 1452222 Change-Id: I5d07f1316770030edcb1bccf4409b452eb6814d9 Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-on: http://git-master/r/365695 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mitch Luban <mluban@nvidia.com>
2014-02-09Revert "ARM: tegra: trustzone: Single kernel to work in both secure and ↵Varun Wadekar
non-secure mode." This reverts commit 7f93a0dddf39f372c064f772f9af6903e91aaacf as the t132ref builds break with the following errors - <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:45: undefined reference to `is_secure_mode' <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:57: undefined reference to `is_secure_mode' <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:58: undefined reference to `tegra_generic_smc' Change-Id: I4e44c2ffba4e1c013213e543b67f2d49a928b764 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/365347
2014-02-09ARM: tegra: trustzone: Single kernel to work in both secure and non-secure mode.Nitin Sehgal
- Remove CONFIG_TEGRA_USE_SECURE_KERNEL config option - Use DBGDSCR.NS bit to dynamically get secure/non-secure mode - Replace ifdefs with dynamic code. - Keep CONFIG_TRUSTED_LITTLE_KERNEL to enable secure os bug 1411345 Change-Id: I75ddfed7a35fcb30e2772bb43057ae022bcf09b3 Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com> Reviewed-on: http://git-master/r/353155 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2014-01-27arm: tegra: enable multi cpu entry to fmin@VminPrashant Gaikwad
Last CPU sets CPU voltage to Vmin and CPU frequency to minimum when all other cores are power gated. Other cores do not enter this state. Exit from this state can be from any CPU whichever exits first. Bug 1025890 Change-Id: I9b5e23c8f77cde0709e1bde63716d46984843d09 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/355587 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-12-12arm: tegra: enable PTM/ETB tracing after the LP2Xin Xie
bug 9622188 Change-Id: Id55c9f540891363fcc188dc9fe9d0fff80394810 Signed-off-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/337999 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
2013-12-03arm: tegra: use ARM's DEN0028 v0.9 and PSCI specs to define SMCsVarun Wadekar
Use SIP Service calls (0x82000000x) and Standard Service calls (0x8400000x) from the DEN0028 spec. PSCI says that we need to use 0x8400000x in r0 for any power management features i.e. cpu idle/hotplug/on/off followed by the actual cpu state (LP2/LP1/LP0) in r1. This translates to Std service calls space mentioned in the DEN0028 spec. The SIP service calls can be used by silicon partners for their CPU specific settings. We use this SMC space for L2 settings and to set the CPU reset vector. SMCs that are interrupted return a special status code to the NS world. Look for that status and send a restart SMC (value = 60 << 24) when received. Also removed save/restore of r4-r12 as we rely on the secure OS to do this for us. Change-Id: I6fae83cc96d29c23305177df770fa07f7970c383 Signed-off-by: Scott Long <scottl@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/329998
2013-11-01arm: tegra: do not read cntfrq registerBo Yan
cntfrq register is not initialized, reading from it returns garbage value. instead, just call the measurement function tegra_clk_measure_input_freq, which returns the same frequency. Change-Id: If2229808686dae76bb92088b4e6540c979b7643f Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/323826 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-10-28ARM: tegra: Move mach-tegra/{gic.h, pm-irq.h}Ajay Nandakumar
Moving mach-tegra/gic.h and mach-tegra/pm-irq.h to include/linux/irqchip/tegra-irq.h so that it helps faclitate the movement of irq drivers from mach-tegra/ to drivers/. Bug 1379891 Change-Id: Id062ebc16441ac295df78731c1e44b32e75d3286 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/302884 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-21arm: tegra: remove unnecessary fuse header filesShardar Shariff Md
Removing unwanted fuse.h header inclusion Bug 1380004 Change-Id: I6cd7ceac380a6e418705965823f7127ad39dd548 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/299810 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-10-17ARM: tegra: Move mach-tegra/{cpuidle.h,timer.h}Ajay Nandakumar
Moving mach-tegra/clock.h and mach-tegra/timer.h to include/linux/tegra-cpuidle.h and include/linux/tegra-timer.h so that it helps faclitate the movement of drivers from mach-tegra/ to drivers/. Bug 1379817 Change-Id: Ia0a33c3f726d2f672409c270ac8ca1629f05eff8 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/299019 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14ARM: tegra: Move platform detect from <mach/hardware.h> to <linux/tegra-soc.h>Dan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I13f3ff891510d2c868f609d507149b32183d34c5
2013-09-14ARM: tegra: dvfs: Don't power-down cluster if dfll bypassAlex Frid
If dfll is bypassed in legacy dvfs mode, CPU voltage during cluster power-down entry/exit is at fixed level set by regulator h/w. This level may not be high enough for current CPU rate. Hence, disabled CPU G cluster power-down when dfll bypass is used. Bug 1310396 Change-Id: I6fc276f94008506f38adbb4b6a8fdc92d4c6ee2e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/260228 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: Tegra: Add residency stats for MC clock stopMatthew Du
Added MC clock stop print to residency stats Change-Id: Iec78cab1fbe7a66ea0ae674bbcf039e60af7d889 Signed-off-by: Matthew Du <matthewd@nvidia.com> Reviewed-on: http://git-master/r/257800 Reviewed-by: Mitch Luban <mluban@nvidia.com>
2013-09-14ARM: tegra: Remove unused includeDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: Add trace for MC clock stop statePrashant Gaikwad
Add trace for MC clock stop state entry and exit. Bug 1010971 Change-Id: I1c10a1918224598293c84e827faf6179c30ee634 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/223328 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: Tegra: Add CONFIG_TEGRA_USE_SECURE_KERNELJames Zhao
This new config would only be enabled when we enable a secure os implementation. This config would be generic and we can reuse it if/when we change the secure os vendor. Change-Id: I94a0a365d4dc834fafa1137a0c0d9adf1b394c51 Signed-off-by: James Zhao <jamesz@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/211756 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Johnson <cwj@nvidia.com>
2013-09-14ARM: Tegra: Add idle state for MC clockPrashant Gaikwad
This state puts DRAM in self-refresh. It is attached to MC clock domain, disabled initiallly and will get enabled automatically when MC clock domain is turned off. /sys/module/cpuidle_t11x/parameters/stop_mc_clk_in_idle can be used to control this state. Bug 1010971 Change-Id: Ia7d70ba1e5a4cdd8ac9cc722de20ed0cd4dabf1a Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/197386 Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14ARM: tegra11: power: Restrict entry to Fmin@VminAlex Frid
Don't use Fmin@Vmin idle state while VDD_CPU rail is updating. Change-Id: I34443fd48668db68343a74acff1c9c514e8269cc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/206482 (cherry picked from commit fadbfaaded67190c09bf2cb079e0b50c0f6dfa22) Reviewed-on: http://git-master/r/208932 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra11: Update entry condition for Fmin@VminBo Yan
Currently, we do Fmin@Vmin if sleep length is longer than its threshold, but shorter than threshold for C0NC. Change this behavior so that we do Fmin@Vmin not only when sleep length falls between the threshold of Fmin@Vmin and threshold of C0NC, but also when sleep length is longer than Fmin@Vmin threshold and cluster wide power down is not enabled in sysfs. This means if sleep length is above C0NC threshold and C0NC/rail-gating are not enabled in sysfs, cpuidle will do Fmin@Vmin instead of per-core power gating. Change-Id: I9b3f3d772d54fbb10b47edfe60342c23f372fb90 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/203962 (cherry picked from commit debdbe0cf0c109b7f41e2cb01ad285653af249c1) Reviewed-on: http://git-master/r/206721 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra: power: Rename CPU idle rate control APIsAlex Frid
Change-Id: Id9bc9deabf8573a0743c5aafd1dc42f654b6f842 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/204413 Reviewed-on: http://git-master/r/207898 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11x: Fix time accounting in power downBo Yan
Include the time of Fmin@Vmin state in the time spent in power down. After this change, the time spent in cpu powered down state as reported by kernel cpuidle infrastructure will also include time spent in Fmin@Vmin state. This makes sense because Fmin@Vmin currently is implemented as a sub-state of "cpu powered down". bug 1235206 Change-Id: I94b3829f70ebcefe6741e9f0d8c92936705f229c Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/201054 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
2013-09-14ARM: tegra11x: Support min residency per platformBo Yan
Though there is no compelling reason to have different residency requirement of Fmin@Vmin and non-CPU power gating for each platform, still makes it possible to define these thresholds per platform. If they are not defined, the default value are taken. Change-Id: I663afb869338bd2e4078b15253c8f8e29c3d6b3c Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198846 (cherry picked from commit 841fb812bfc793c3028b72cbfa05ce26a21226c4) Reviewed-on: http://git-master/r/200860 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra11x: Add stats for clock gating@VminBo Yan
bug 1049931 Change-Id: I94a751cf7cf58e6930c53975912b34cb65d7bd6c Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198019 (cherry picked from commit d903506a1e558234b8afcd867f55aed4b024ffe7) Reviewed-on: http://git-master/r/200859 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14ARM: tegra11x: clock gating at Vmin in CPU idleBo Yan
Force Vmin by dropping DFLL rate to minimum in cluster idle state if power gating non-CPU partition and rail gating are not as power efficient. bug 1049931 Change-Id: I83a9d1f55995c4ab14d5afb1095877b23b25de09 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198018 (cherry picked from commit 358df5ac0b2792ac0f1c87725358ad007036e666) Reviewed-on: http://git-master/r/200858 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14ARM: tegra11x: Define ncpu residency for 2 clustersBo Yan
There is no compelling reason to define minimum residency of non CPU power gating for each different platform. Non CPU power gating has far less dependency on platform in terms of latency when compared against rail gating. So move this parameter to CPU specific idle driver code. Define minimum residency of non CPU power gating for both slow and fast cluster. The entry criteria is different for two clusters, so different value are required. Change-Id: I3f734d056f6de6a804ca4c14e037a98bc07c646d Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/197537 Reviewed-on: http://git-master/r/200856 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra11x: Fix wake-up time adjustmentBo Yan
The wake up time adjustment for per-core CPU power down entry has a few issues: the logic of checking masking bit is wrong and unnecessary, the timer function for getting context is not used elsewhere and seems redundant, the calculating statement itself is confusing. This patch aims to fix issues above. Change-Id: Id717f50005e0c32db80af786d9b1fbbe628c196a Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/197065 (cherry picked from commit 544629015e3a2924ea094e9809131dd0be30954d) Reviewed-on: http://git-master/r/200855 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14ARM: tegra11x: Remove redundant cpu_number callsBo Yan
The "cpu_number" maps cpu number for slow cluster to "4", this can be reused later, no need to call "cpu_number" every time. Change-Id: Ib0636b80b587868e23a6b07a5cc9960e13d38353 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198580 (cherry picked from commit 79faef4783ff207f38d76c283704e3b70ea31f18) Reviewed-on: http://git-master/r/200853 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14fixup cpuidle-t11x.c move iomap.hDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra11x: more accurate sleep timeBo Yan
The sleep length in tick data structure does not reflect how long timer has been running, thus the expected wake up trigger may be set to a value which is too late. Directly accessing timer register to get the next timer event, which is then used to calculate the expected wake up time. This implies we are sleeping shorter than before in case of cluster power down, but will make sure we don't oversleep. Change-Id: I84598db30b6a739103026d090b130f3adb63147b Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/193483 (cherry picked from commit f51efbce4b67bfb79cdb68f2613e58b080634b37) Reviewed-on: http://git-master/r/196111 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra11x: Raise clock rate for C1NC power gatingBo Yan
The C1NC power gating has long latency when slow cpu runs at very low clock rate. Raising it to 204MHz can reduce this latency significantly. The CPU clock is reverted back to its original value once slow CPU wakes up. bug 1177454 Change-Id: Idc6122f0a2ba8ad35c963942c60e9cf4a4f0b0c2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/193501 (cherry picked from commit a71665bb3ddb437536cec00be91e9b201414fc93) Reviewed-on: http://git-master/r/191455 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
2013-09-14ARM: tegra11x: timer save/restore is removedBo Yan
The current timer save and restore is unnecessary because it's done by broadcast mode entry/exit. The clock event using arch timer does not support the feature "CLOCK_EVT_MODE_PERIODIC", so there is nothing comparable to tegra30 in which the periodic load has to be preserved. Change-Id: Ia1f91be4f7d1f6e827c95ce013502c77a3c389b0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/193239 (cherry picked from commit de701176ec031f68f3f2c6ecab294745d46c1099) Reviewed-on: http://git-master/r/193979 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14security: tf_driver: integrate latest TL releaseHyung Taek Ryoo
Tegra4 version: TF_TEGRA4_AC02.02.39373 Create a new SMC (0xFFFFFFE7) for no flush operations in cluster power down. Bug 969937 Change-Id: Ie91d1ab2560ab56ee9ca2c8f35757a9bb5222c26 Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/168212 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra11x: Add flag to force C0NC power gatingBo Yan
The bit 2 of fast_cluster_power_down_mode now dictates whether to force the power down mode specified in b[0-1]. If bit 2 is 0, then b[0-1] specifies the deepest cluster power state in idle, the cluster idle power state doesn't need to go to that level every time. If bit 2 is 1, then b[0-1] forces cluster idle power state to that level. bug 1181412 Change-Id: I36aacc2d5318c7054d32d662c150530c51a4e9a5 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/166718 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra11x: cpuidle: Implement cluster power down for secure osHyung Taek Ryoo
This change implements cluster power down feature for secure os. Bug 969937 Bug 1178454 Change-Id: I2e40fddfad409396657102e24f07d75c8de7d879 Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/166482 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-09-14ARM: tegra11x: cpuidle: Remove LP2 referencesBo Yan
This change completely removes references to lp2 in cpuidle-t11x.c, some related changes also affect cpuidle-t2.c, cpuidle-t3.c, and a few other files. bug 1034196 Change-Id: Ic2387bf614b39bd08ed4b2fc6e996f6fbf8306c0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/160017 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2013-09-14ARM: tegra11x: cpuidle: Stats for C1NC/C0NC/CRAILBo Yan
This patch adds stats for power gating C0NC and C1NC partitions, it also adds stats for fast cluster rail gating. The numbers under column CPU0 are the sum of CE0 power gating, C0NC power gating, and rail gating. The numbers under column cpulp are the sum of CELP power gating and C1NC power gating. Change-Id: Ia02f78ed124652b1deac3a6e29a47aaec8fcd910 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/147745 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com> Rebase-Id: Rc72aeff0aefb0081c4b340e734933bf7c92d74c5
2013-09-14ARM: tegra: replace tegra_cpu_wfi with cpu_do_idleBo Yan
Function "cpu_do_idle" is defined in ARM common code, there is no need for "tegra_cpu_wfi" which has the identical implementation. Change-Id: I8ca3ada171990148162276a76434aebd2bd188e2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/159157 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rd6a6fc2bab5af491f65b018cc4bd4cecfdd2b60b
2013-09-14ARM: tegra: restructure cpuidle utility functionsBo Yan
As more and more chips are supported, the conditional compilation flags in cpuidle.h also grows, this is becoming unwieldy and cumbersome. Let each chip register its own set of functions can alleviate this problem. Change-Id: I033d7aeb7a46869783a5c78058869920d81d070b Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/147420 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R1a350795453ebdbebad3f61a7f24e7f6a9eb4180
2013-09-14ARM: tegra: Change CPU idle power state namesBo Yan
LP3 means clock gating, so make it explicit. Also changed the idle state name "LP2" to "powered-down". bug 1034196 Change-Id: Icb2e8ba1aafa7b100cef96c7907940a251fd7e59 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/147280 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R330175b25e1cc3a9d138f8376c670340d80e9429
2013-09-14ARM: tegra11x: residency time for different LP2 modeBo Yan
Select CPU partition power gating only, non-CPU power gating, or rail gating based on the required minimum residency and requested sleep length. The minimum residency for non-cpu power gating and rail-gating are arbitrarily set in this change, they have to be characterized. The minimum residency for non-cpu power gating shall always be less than the minimu residency for rail gating. Also fix a bug that prevents rail-gating Change-Id: Icc646061f0fb47662fa74e77c6ae6b5d5da1444a Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/146640 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rd2f8f5583057310c04bf0ea1d1bd8cdbbd15a9a6
2013-09-14ARM: tegra11x: fast cluster power down controlBo Yan
Currently, we are using "power_gating" to control what power down mode to choose for fast cluster. With this change, a new sysfs node "fast_cluster_power_down_mode" is used for that purpose. This node is an unsigned integer with only 2 LSB used. '00' means power gating CPU only, '01' means power gating non-CPU partition as well, '10' means rail-gating the entire fast cluster, '11' means emulation mode, which shall not be selected in production environment. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/144769 (cherry picked from commit 08cf1b25cbcfbb46822f76d08313ed1a9be6fc28) Change-Id: I1a8a79cbd9f1f3ddce0b0f3d42fb3747284ac58e Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146486 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R619facf202528adc6cfab1c93d482671a5e415b0
2013-09-14ARM: tegra11x: Control power gating of each CPUBo Yan
Currently, LP2 can be enabled or disabled for either CPU0 or CPUn, this is good for T30, but for T114, CPU0 is no different from any other CPUs in terms of hardware power management support. Add finer control so that power gating can be enabled or disabled for any individual CPU in fast cluster. The control is done through sysfs interface. The node "cpu_power_gating_in_idle" is a CPU mask. the 5 LSB represent 5 CPUs. bit 0 is for CPU0, bit 1 is for CPU1, bit 2 is for CPU2, bit 3 is for CPU3. By default the mask is set for all CPUs. Writing a '1' to bit n enables power gating of CPUn. any other bits are not used. The special case is bit 4, which controls the single CPU in slow cluster. For example, to enable power gating for all CPUs in fast cluster, just write a "15" to that sysfs node. To disable power gating for all CPUs, write a "0". To enable LP2 for slow CPU, write 0x10 to that node. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/144136 (cherry picked from commit bbfd7d15eba22492d56831e4db1181128ffa56ae) Change-Id: I12299718d286f51d8340c0258cbd1265f3212655 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146485 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: Ra21713c217770922349b19cf5a27fcd41b5a8dcc
2013-09-14ARM: tegra11x: Create cpuidle driver for t11xBo Yan
The initial version is copied from cpuidle-t3.c, then conditional compilation macros are cleaned up, unused functions are removed. t11x code then is removed from cpuidle-t3.c "slow_cluster_power_gating_noncpu" is added to sysfs to let user control how to power gate slow cluster. It's disabled by default, which means we power gate CPU partition only when running in slow cluster. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/141422 (cherry picked from commit 2f7860a3cd004d803df2550499a26c6675617b01) Change-Id: I7a00f7a77fa8a6612bdc9dd4f9c2a2656b2d84c5 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146483 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R182076c70588d7fc5bc7b1feaac43ce8917c9d89
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