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path: root/arch/arm/mach-tegra/cpuidle-t3.c
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2012-04-19Revert "ARM: tegra: rethink the cpu suspend-resume code path"Sang-Hun Lee
This reverts commit f31ca2d9e0580b58dc51fde31fc8ace190dd253b. Bug 967887 Change-Id: I3fe975f7a6939cace5e208947bcb82e09008c0ac Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96787 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-05ARM: tegra: rethink the cpu suspend-resume code pathVarun Wadekar
The current kernel methodology expects that tegra_cpu_suspend is actually the last function in the entire suspend sequence. In order to achieve this, the code needs to be remodelled a bit so that we actually execute native cpu_suspend at the end of the suspend sequence. This allows us to leverage all the cpu_suspend code developed by ARM in the upstream kernels. Bug 934368 Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/84481 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-06ARM: tegra: power: Don't enter LP2 if not in NOHZ modeAlex Frid
Prevent Tegra3 secondary CPU entry to LP2 state when scheduler tick is not switched to NOHZ mode, yet. Bug 945658 Change-Id: I654f7aac0e545ecb557005cc4efad4317689e091 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/87937 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23ARM: tegra: power: Power off multiple CPUs on-lineAlex Frid
Currently on Tegra3 cpu complex is powered off in idle (enters CPU0 LP2 state) only if all secondary CPUs are off-line. This commit adds an option for CPU0 to enter LP2 while secondary CPUs are still on-line but have been power gated and entered LP2 state by themselves. The critical race: secondary CPU is waking up from LP2, while CPU0 is turning common CPU rail off, is addressed as follows. 1. When entering LP2 state on CPU0: a) disable GIC distributor b) check that CPU1-3 are all power-gated (i.e., either off-lined or have entered LP2) c) if (b) passes - set all interrupts affinity to CPU0, then re-enable distributor and continue with CPU complex powering off d) if (b) fails - re-enable distributor and enter clock-gated (LP3) state on CPU0 This procedure prevents waking secondary CPUs by GIC SPIs. 2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ or private timers would happen. This is achieved by disabling timers and legacy interrupts if CPU1-3 enters LP2 state with external timers selected as wake sources. Respectively, establish dependency between turning rail off and LP2 wake timers configuration options. 3. Finally, no IPIs is sent by CPU0 entering LP2. There are no special changes in wake up procedures - whenever CPU0 is awaken by external interrupt or wake timer, cpu complex is powered on by h/w, and secondary CPUs that were in LP2 state are ungated by the same interrupt (off-line CPUs are kept power gated). Hence, there is no need for CPU1-3 external wake timers to run while the rail is off, and these timers are stopped. To make sure that none of secondary CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep interval of all CPUs. By default configuration option for powering off multiple on-line CPUs is disabled on Tegra3. Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83547 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-17ARM: tegra: power: Add external LP2 wake timers on secondary CPUsAlex Frid
Add an option to use external timer as Tegra3 secondary CPU wake source from lp2 (power gated) state. This is a follow up to commit 51e6be9ce103fbeb2b73fa2a9d2b6528a6941e81 that disabled wake from external timer, since its interrupt is registered too late - after secondary CPU is brought on-line, and already had a chance to enter lp2. With this commit, secondary CPU is not allowed to enter lp2 in idle until wake timer is registered (clock-gated lp3 state is entered instead). External timer wake up mechanism is enabled on Tegra3 only if option HAVE_ARM_TWD is not selected. Otherwise, continue to use local CPU timers as lp2 wake sources. Change-Id: Ic8c33f55e77174717bfa6525041e1263d3232dd5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83546 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-13ARM: tegra: power: Don't over-sleep LP2 on secondary CPUsAlex Frid
Adjust Tegra3 secondary CPU LP2 time for exit latency to avoid scheduler event over-sleep. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/78635 (cherry picked from commit 433a3e356a0281efb1caf9b78bb1576008a58ed2) Change-Id: Ifd298f0a4364fe4775ae209d76b2eda24b1bfefc Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82709 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com>
2012-02-03ARM: tegra: power: Separate lp2 latency for secondary CPUsAlex Frid
Do not use common lp2 exit latency for Tegra3 secondary CPUs in G mode. Separately measure and adjust latency on each slave CPU; use per-cpu latency to determine target residency threshold for entering lp2 on each CPU. Reviewed-on: http://git-master/r/78375 Change-Id: I4470d1b4814d8f12129e21105dd952a903084f1e Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78903 Reviewed-by: Automatic_Commit_Validation_User
2012-02-03ARM: tegra: power: Separate lp2 latency for G/LP CPU modesAlex Frid
Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes. Separately measure and adjust latency in each mode; restart calculation after mode switch from the last measured latency in the target mode. Reviewed-on: http://git-master/r/78344 Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78902 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-03ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entryAlex Frid
When Tegra3 secondary CPU is entering LP2, read TWD timer state into context structure, rather than separate local variables. Reviewed-on: http://git-master/r/77957 Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78899 Reviewed-by: Automatic_Commit_Validation_User
2012-01-12ARM: tegra: power: Fix Tegra3 LP2 statsAlex Frid
Fixed Tegra3 LP2 stats to account for total completed and interrupted LP2 time (interrupted LP2 time was missed). (cherry picked from commit 4207244f6fc25544315fe5aaf067ea7684731d9d) Change-Id: I3b87819d56e3a700f7e0858fa124b0fdfabe8295 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/73902 Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-on: http://git-master/r/74557 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-01-10arm: tegra: REVERT "use unsigned cpuidle latency variables"Joseph Lehrer
Reverting until LP2 hang problem better understood. bug 896827 Reverts I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Change-Id: I9ae1f8e75b77049baf26480691b98e6f9cacca4e (cherry picked from commit c0b30ab66c5f1286a5c1f10777c436a80f8f2fa8) Reviewed-on: http://git-master/r/72905 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com> Tested-by: Joseph Lehrer <jlehrer@nvidia.com> (cherry picked from commit 3d7b52eaf614848e8417c84b819c76faed306503) Reviewed-on: http://git-master/r/73951 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-30arm: tegra: use unsigned cpuidle latency variablesJoseph Lehrer
Latency calculations were using mixed signed/unsigned variables and assignments resulting in very large values which interfered with entering LP2. bug 896827 Change-Id: I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Reviewed-on: http://git-master/r/72151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2011-12-15ARM: tegra: dvfs: Add DVFS rails statisticAlex Frid
On Tegra3: complete account of in- and out-of-bound rails control. On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted. Change-Id: Ib68cbbfe3e4f965e758aca17a0ba30277d530347 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/67340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-30ARM: tegra: power: Fix LP2/LP3 states accounting on Tegra3Alex Frid
- Made sure LP3 state is reported as last entered state to cpuidle governor in case when LP3 is entered as a fall back from LP2 path. - Accumulate idle time designated to LP2 state by cpuidle governor and time actually spent in LP2 by each CPU separately. Update LP2 statistic output. Change-Id: I55b461e94925ba7a41112756ed958f81fc0bc882 Reviewed-on: http://git-master/r/60381 Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R240873bd1de225696d392ac5ba2c3d517c59d86e
2011-11-30ARM: tegra: power: Add Tegra3 cpu idle parametersAlex Frid
Add Tegra3 cpu idle parameters: lp2_0_in_idle and lp_n_in_idle to independently control LP2 mode for boot and secondary cpus. Change-Id: I7e526b9bd78a9d5c3235307bbc89f5fb507bec2b Reviewed-on: http://git-master/r/55630 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rc6a468b2e9e065c344b2386366d5a47d77ddf037
2011-11-30ARM: tegra: power: Update Tegra3 LP2 time predictionAlex Frid
Use local timer count to predict time to be spent by secondary CPU in LP2 state instead of scheduler timing. This is more accurate, as local timer wakes CPU after counts down to zero. Change-Id: I28fe6c3153e1c527abf4cf66b556d64516582a35 Reviewed-on: http://git-master/r/55629 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Rebase-Id: R577246dfe6bce06bf7a1f87d0ab488322d98b631
2011-11-30ARM: tegra: power: Clean Tegra3 LP2 entry procedureAlex Frid
- Do not save/restore local timer configuration across secondary CPU LP2 state. It is always preserved, since local timer is neither power gated nor reset when secondary CPU is in LP2. - Do not configure external timer for secondary CPU wake up, since we can use local timer instead. Moreover, in current code external timer interrupt is registered too late on secondary CPU after it is brought on-line, so the timer may not always be able to wake CPU up from LP2. Change-Id: I864e9910fe7112bbce3ea4dbaef12be4b42fb5dc Reviewed-on: http://git-master/r/55070 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R3407f05d200d81e29994daf278170d3619714bef
2011-11-30ARM: tegra: power: Fix premature clock event broadcast modeScott Williams
Do not switch to clock event broadcast mode until the final CPU is going into LP2. Switching into broadcast mode on the secondary CPUs can cause double ticking and/or kernel panics on the primary. Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48743 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5
2011-11-30ARM: tegra: power: Rename variables for consistencyScott Williams
Rename Tegra3 CPU idle handler variables to be the same as their Tegra2 counterparts for consistency. Change-Id: I49a03182ff5a15d34847b3837f681ca842dcf643 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc71d7d71bebb197c983180429f24de7708d8dfea
2011-11-30ARM: tegra: power: CPU complex must be suspended on CPU0Scott Williams
All CPUs are not created equal. CPU0 must be the one to perform the CPU complex rail gating action and as such must always be the last CPU taken down. Change-Id: I92d1c1c29305d2bf35a15baa43a6d299806482b7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5ba8fbba2771a2458fcf27d9d49c964ffbe53c88
2011-11-30ARM: tegra: power: Add LP2 in idle support for secondary CPUsScott Williams
Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917
2011-11-30ARM: tegra: timer: Save TWD registers on secondary CPU LP2Scott Williams
Change-Id: I0ca5186fd833913b79abf2a7dbddc528d547acc6 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Simplify, remove unnecessary macros Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R686b57e37db12361f3c5054500c74337de6fd5a6
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
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