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2011-11-30video: tegra: host: Fix misspelling in GPU detectionTerje Bergstrom
Fix misspelled configuration variable in tegra_gpu_register_sets(). Bug 889239 Change-Id: Id7da08e0eca16f28b1b6a17608b4f367311b5620 Reviewed-on: http://git-master/r/59889 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rf1d450abb59df99dcfdef6ff743fb32c9b254741
2011-11-30ARM: tegra: fuse: Fix tegra_chip_uidDan Willemsen
This now matches what the bootloader thinks the chip ID is (and the lot code is no longer all zeros). Change-Id: I46dc677b983dd28f7f77e49919860fef66da8f51 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/56316 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rfb7b961acd57447df95600d4f1678d84242ed1b9
2011-11-30ARM: tegra: Clean up the chip revision decoderScott Williams
Replace the chip revision decoder with something that is more extensible and maintainable. Change-Id: I1c31cbded4ca14e7949be551995b4aaa75f5c1fb Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/50931 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Rebase-Id: Raf389b9daa8a8312c38f281dcf05ea19b2018136
2011-11-30ARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter setsScott Williams
Determine the number of GPU register sets based upon the setting of ARCH_TEGRA_DUAL_3D. Change-Id: I66e860fba2a979921ac4e4bd39bed99fb305996e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/50355 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R443612bad1ec0f745a51b8f301a322b5bb8cef96
2011-11-30ARM: Tegra: dvfs: Proc array indep of new T30 char SKUsDiwakar Tundlam
- Make process_ids array independent of SKU to avoid confusion when detecting SKU, speedo_id and parsing process_id. - Added SKU definitions for characterization SKUs of AP30, T30, T30S Bug 855816 Original-Change-Id: I925d54ab6d35e8af038cbfe84ef4b4c076cd596d Reviewed-on: http://git-master/r/43096 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R832f8fb1a34ab700af0c6389fbe5307f334cc54c
2011-11-30ARM: tegra: fuse: Add A03 revision for Tegra3.Krishna Reddy
Original-Change-Id: I9fd1e67b17db69bd835c7474070e453ee37b4b62 Reviewed-on: http://git-master/r/43186 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R8ad876ded62f88d6ff032183a1f9d2b8bb2775b2
2011-11-30arm: tegra: fuse: tsensor specific fuse public API addedBitan Biswas
Defined public fuse API to extract tegra3 tsensor configuration parameters. bug 851791 Original-Change-Id: Ia14e2d515ee1d695556492464e8ceaf4b0d13477 Reviewed-on: http://git-master/r/42367 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R1090e6ad78bcef23670ff647de86e695780f5b76
2011-11-30arm: tegra: Fix build warningsScott Williams
Fixes "warning: passing argument 1 of 'param_get_uint' discards qualifiers from pointer target type" and "note: expected 'char *' but argument is of type 'const char *'" messages. Original-Change-Id: I7610dc0bde0cf3b9a7597f3892b09f7c31a156d1 Reviewed-on: http://git-master/r/36560 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R87f617932a52d873aa237072e14339627300cf5d
2011-11-30ARM: tegra: fuse: Don't fail when priv not passed inDan Willemsen
Rebase-Id: R63d06986e871cea59b0eb39d4290fa44b0312024
2011-11-30nvhost: Add checks for # of GPU register sets.Terje Bergstrom
Checks from a fuse whether we have one or two register sets. - fuse.h/fuse.c: Implement tegra_register_sets() - nvhost_3dctx.c: Use tegra_register_sets() to determine number of sets to save. - dev.c: Create entry /sys/module/nvhost/parameters/register_sets to return to user space the number of sets. Change-Id: Ibd9a50cfe77a642335bd85b5814e8fdd8d2c35e6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/29786 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R0a53bbe37d8d83599b85514dad33bcd04a2f67f4
2011-11-30arm: tegra: Fix build warningScott Williams
Fixes "warning: function declaration isn't a prototype". Change-Id: Ifbf00f2294413193ff5a7d652252841072466779 Reviewed-on: http://git-master/r/35441 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Ra1a83859770f6f73cb122152dc76fdcc7aff66d0
2011-11-30ARM: tegra: dvfs: Update DVFS tables with data for T30SDiwakar Tundlam
Change-Id: I38b9752adc9e927935fe7ffe5590c41577a45809 Reviewed-on: http://git-master/r/34381 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R318f6916f8213c25092110a8800eb506d1718b38
2011-11-30arm: tegra: Add sysfs tegra chip id/revisionHoang Pham
Original-Change-Id: Ia4437fd1374fd38b0cfaf9869012e9553ea1a156 Reviewed-on: http://git-master/r/35602 Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd744a3c83776e1b70f34a3312f323ed534e321ad
2011-11-30arm: tegra: fuse: add function to get chipidLuke Huang
1. Add the function to return chipid. 2. Remove the if-def for A01 for tegra2 and add kernel panic if tegra2-A01 is detected. 3. Clean up errors/warnings reported by checkpatch.pl. Original-Change-Id: I0aa4ed2c4fd77e8e5ae83feceee94372b1506446 Reviewed-on: http://git-master/r/32450 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R7e4adad9e8127d725ebae51bc308ace382bebc3e
2011-11-30arm: tegra: Clean up SOC conditionalsScott Williams
Change SOC conditionals to make them more forward-looking. Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9 Reviewed-on: http://git-master/r/32706 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R77c675a1995116098b58f1f775bc7c3cc8722998
2011-11-30ARM: tegra: clock: Fix speedo_id eval for max speedo valueDiwakar Tundlam
Original-Change-Id: Ia36ea70b054262772df39650b5fdc7419be2bfcf Reviewed-on: http://git-master/r/32802 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R90d4deb23bca5ba6bad270c6c6eb54a851ae6a6f
2011-11-30ARM: tegra: clock: Set speedo_id according to actual fused SKUDiwakar Tundlam
- Read SKU_INFO fuse to get A02 SKU info - Update CPU DVFS to use actual SKU info obtained - Enable main table for EDP capping and thermal throttling Original-Change-Id: I7ff3b06476998d77cc3f7a4fc03fb72e26b570db Reviewed-on: http://git-master/r/32084 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re91f616032d8045ea2c28822e40f815f3e449931
2011-11-30ARM: tegra: power: speedo, cpu, core process ids for tegra3Diwakar Tundlam
Original-Change-Id: If206f26e0f10f666fd7839c1ebb839eeb4899e21 Reviewed-on: http://git-master/r/29879 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd2eefa2c3c6775846eb76777565b144ea9e0e58a
2011-11-30ARM: tegra: Decode optional chip-private feature string in cmd lineHiro Sugawara
ap20 needs to distinguish between A03 and A03p revisions. Original-Change-Id: I726d45f5ea3c5283ae11057f01c86038eb6c2872 Reviewed-on: http://git-master/r/27777 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: If14b6330ccd8bb6420e0c9118291414cc383b94d Rebase-Id: R60cae4b7b2061deeedd0cabaa6bf95f2f379514a
2011-11-30ARM: tegra: chipid: Parse and save Tegra chip ID passed by fastbootHiro Sugawara
Original-Change-Id: Ibb00d64820cc81b6af08c4ac7266d2df94bd6a1e Reviewed-on: http://git-master/r/26631 Tested-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Idc50a6f9891bc61f19e1f282480519ffccf11ad4 Rebase-Id: R787474379574ab1e081e49528af749709856b682
2011-11-30Update copyrightsScott Williams
Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
2011-11-30arm: tegra: Add support for T30.A02Scott Williams
Bug 784484 Original-Change-Id: I8aec236c62f01c3f319b1d96c8c13464cb564904 Reviewed-on: http://git-master/r/22886 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8f857fe8422c60b2ec3ccc0961bbd426e3c69c29 Rebase-Id: Rcfffd5053a81c091fd424f00a3ef06be7cd87117
2011-11-30arm: tegra: fix ventana build breakJin Qian
Fix build break on ventana due to improper use of kernel config paramters. Original-Change-Id: I7ec13091cf67fa5cb25b39c92eb33756263506c4 Reviewed-on: http://git-master/r/22705 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Id942dc5dc79e0edf5dc27d418083f340ae40edb8 Rebase-Id: R789dea06de4b014643eff9b43343907e9dadcdda
2011-11-30ARM: tegra: Add Tegra3 speedo stubsAlex Frid
Original-Change-Id: I05b9b8014062a28a69407c08fc630a280214315e Reviewed-on: http://git-master/r/16661 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I190f04798473bf4452d00561cae96e45085c3dc0 Rebase-Id: Rad0832a8d7afd74adeaaaf0faaad40e0ac0a8f1d
2011-11-30Merge remote branch 'git-master/android-tegra-2.6.36' into 0112-1120Dan Willemsen
Conflicts: Makefile arch/arm/configs/tegra_defconfig arch/arm/configs/tegra_whistler_android_defconfig arch/arm/mach-tegra/Kconfig arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/board-ventana-sensors.c arch/arm/mach-tegra/board-ventana.c arch/arm/mach-tegra/board-whistler-panel.c arch/arm/mach-tegra/board-whistler-pinmux.c arch/arm/mach-tegra/board-whistler-power.c arch/arm/mach-tegra/board-whistler-sensors.c arch/arm/mach-tegra/board-whistler.c arch/arm/mach-tegra/board-whistler.h arch/arm/mach-tegra/clock.c arch/arm/mach-tegra/clock.h arch/arm/mach-tegra/common.c arch/arm/mach-tegra/cpu-tegra.c arch/arm/mach-tegra/devices.c arch/arm/mach-tegra/devices.h arch/arm/mach-tegra/dma.c arch/arm/mach-tegra/fuse.c arch/arm/mach-tegra/fuse.h arch/arm/mach-tegra/headsmp.S arch/arm/mach-tegra/include/mach/clk.h arch/arm/mach-tegra/include/mach/iomap.h arch/arm/mach-tegra/include/mach/system.h arch/arm/mach-tegra/irq.c arch/arm/mach-tegra/spi_tegra_slave.c arch/arm/mach-tegra/suspend.c arch/arm/mach-tegra/tegra2_dvfs.c arch/arm/mach-tegra/tegra2_emc.c arch/arm/mach-tegra/tegra2_emc.h arch/arm/tools/mach-types arch/x86/kvm/svm.c drivers/cpufreq/cpufreq_interactive.c drivers/crypto/tegra-aes.c drivers/gpio/cs5535-gpio.c drivers/hwmon/nct1008.c drivers/misc/Makefile drivers/net/wireless/p54/p54usb.c drivers/regulator/max8907c-regulator.c drivers/rtc/rtc-tegra.c drivers/usb/gadget/fsl_udc_core.c drivers/usb/host/ehci-tegra.c drivers/usb/host/xhci-mem.c drivers/usb/otg/tegra-otg.c drivers/usb/serial/ftdi_sio.c drivers/video/tegra/dc/dc.c drivers/video/tegra/dc/hdmi.c drivers/video/tegra/dc/hdmi.h drivers/video/tegra/host/dev.c drivers/video/tegra/host/nvhost_channel.c drivers/video/tegra/host/nvhost_intr.c include/linux/nct1008.h net/econet/af_econet.c sound/soc/tegra/Kconfig sound/soc/tegra/tegra_i2s.c sound/soc/tegra/tegra_pcm.c sound/soc/tegra/tegra_soc.c sound/soc/tegra/tegra_soc.h Original-Change-Id: I5b39fd8ea2284828e9cb3b5ce4330728e20b1662 Reviewed-on: http://git-master/r/15736 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I71ecd7c4426e7e82500f12d57b85a6bcc417065c Rebase-Id: Rc18bd03bdd6ef4cf0a5ae6f7dc863729deb2eb27
2011-11-30arm: tegra3: Fix chip unique id generationScott Williams
Original-Change-Id: I1bb441213edfd6440e890e0eb77c07577168d2a9 Reviewed-on: http://git-master/r/14854 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Id4470677f046ef4f3ff9f592cb5d7aafee460e07 Rebase-Id: R93290bbeec5c12c8fe9acf301d66c22191f5821e
2011-11-30ARM: tegra: Add speedo-based process identificationJin Qian
Reviewed-on: http://git-master/r/13396 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> (cherry picked from commit 59d05a32b0c86672259dbb0f8eefce6d663d6bfc) Conflicts: arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/fuse.c Original-Change-Id: I29c5243bedc97d7722c80b38e76934c77c3ccb47 Reviewed-on: http://git-master/r/13711 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ibfbd398e6a0c4948e336ecedd4c39495ff7d22c4 Rebase-Id: Rc1749a55a20feebfa6efcfe90449db85ecae5eab
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: Add speedo-based process identificationAlex Frid
Original-Change-Id: If6cd2914551331bd49b128ad3143a0d7adf0f120 Reviewed-on: http://git-master/r/13396 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Re61c7e38519e6fde84f95f1c7ecb883c92b2d0db
2011-11-30[ARM] tegra: add utility function to read spare fuse bitsGary King
spare fuse bits 18 and 19 are used to distinguish A03p Tegra 2 chips from A03 chips. this is needed on some platforms to determine whether or not LP0 suspend should be enabled. Original-Change-Id: I03a964eac3783535357faecee8cd35e65350b356 Reviewed-on: http://git-master/r/12078 Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd59fb4d4002b05d88529c44bb7a8d5c5b6bff79b
2011-11-30ARM: tegra: fuse: Fix bug in get_spare_fuseColin Cross
get_spare_fuse was calling tegra_apb_readl and passing an offset, but tegra_apb_readl requires a physical address. Fix it by calling tegra_fuse_readl instead, which takes an offset. Fixes a crash booting on A03 parts, where get_spare_fuse is used to determine the difference between A03 and A03 prime. Change-Id: Ie386dc099e1c14eeb36262bfcc882e29a40a8da6 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30[ARM] tegra: use APB DMA for accessing APB devicesJon Mayo
Change-Id: I165411a14342666cbac02fb8cb171580ab0826aa Reviewed-on: http://git-master/r/14464 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Signed-off-by: Jon Mayo <jmayo@nvidia.com>
2011-11-30[ARM] tegra: fuse: Add function to get Tegra revisionColin Cross
Change-Id: I11783f5784454fec143393336195db40c9aa3160 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: tegra: fuse: Separate fuse dma initializationColin Cross
There is a dependency loop between fuses, clocks, and APBDMA. If dma is enabled, fuse reads must go through APBDMA to avoid corruption due to a hw bug. APBDMA requires a clock to be enabled. Clocks must read a fuse to determine allowable cpu frequencies. Separate out the fuse DMA initialization, and allow the fuse read and write functions to be called without using DMA before the DMA initialization has been completed. Access to the fuses before APBDMA is initialized won't hit the hardware bug because nothing else can be using DMA. Change-Id: Ib5cb0f346488f2869e8314c5f3b24fd86873f4c3 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30[ARM] tegra: fuse read/write apis for fuse burningVarun Wadekar
expose fuse register read and write apis for fuse burning Change-Id: Id6785f5506fe9293ddb5072240f49470ca5fcd08 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2011-11-30[ARM] tegra: use dma to read/write fuse registersVarun Wadekar
tegra2 hangs if fuse registers are accessed during an apb dma operation. war is to use apb dma to read/write fuse registers instead. Change-Id: I4d99a1ad56115c0d73e9cd0679cf38f70f922f3d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2010-10-21[ARM] tegra: Add support for reading fusesColin Cross
The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency. Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-13 13:08:58 +0000