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path: root/arch/arm/mach-tegra/pm.h
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2014-09-16arm: tegra: Ram repair for slow clusterBibek Basu
Do ram repair for slow cluster also during boot Bug 1528461 Change-Id: I71ed7891aaff48f0b87438ad029b22ced9be0f04 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/494787 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2014-04-23platform: tegra: move LP0 entry function to driverPrashant Gaikwad
Change-Id: Ife6926d0c00d7e046b2579795f50ef96d633fc8f Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/395845 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-03-25ARM: tegra: pmc: deleting pmc.h from mach-tegra/Sumit Singh
Moving the content of pmc.h to linux/tegra-pmc.h and deleting it. Bug 1440573 Change-Id: I54014c58765b99dd99e6aaae22bad8cb9010e79c Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/377592 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-03-14ARM: tegra: remove CONFIG_USE_SECURE_KERNEL usageVarun Wadekar
Remove the config variable usage from the kernel and make the secure firmware check dynamic. This make LP1 resume tricky since we need to execute out of TZRAM till SDRAM is out of self-refresh. To fix this, store secure firmware presence bit in TZRAM during boot. Bug 1475528 Change-Id: Ic18766bbee14626e8cf092363d57f4d98b44b6df Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/377616
2014-03-14arm: tegra: use PSCI interfacesVarun Wadekar
ARM defines PSCI interfaces to be used for power states. We have been using the actual semantics for quite some time now and so can remove our implementation of the SMC issuing code and use the generic interfaces present in <arm/arm64>/kernel/psci.c. Bug 1475528 Change-Id: Ieba8a0a54f5ee731626e7d92a767ef044e88f12d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/378354
2014-02-09Revert "ARM: tegra: trustzone: Single kernel to work in both secure and ↵Varun Wadekar
non-secure mode." This reverts commit 7f93a0dddf39f372c064f772f9af6903e91aaacf as the t132ref builds break with the following errors - <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:45: undefined reference to `is_secure_mode' <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:57: undefined reference to `is_secure_mode' <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:58: undefined reference to `tegra_generic_smc' Change-Id: I4e44c2ffba4e1c013213e543b67f2d49a928b764 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/365347
2014-02-09ARM: tegra: trustzone: Single kernel to work in both secure and non-secure mode.Nitin Sehgal
- Remove CONFIG_TEGRA_USE_SECURE_KERNEL config option - Use DBGDSCR.NS bit to dynamically get secure/non-secure mode - Replace ifdefs with dynamic code. - Keep CONFIG_TRUSTED_LITTLE_KERNEL to enable secure os bug 1411345 Change-Id: I75ddfed7a35fcb30e2772bb43057ae022bcf09b3 Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com> Reviewed-on: http://git-master/r/353155 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2014-01-21ARM: tegra: fix build for platform with one clusterBo Yan
Change-Id: I81f5645ed89973c9dcbb2be61b7443d33bf9f472
2014-01-21ARM: tegra: port inline assemblies for ARM64Peng Du
Port the inline assemblies w.r.t ARMv8 ISA and #ifdef the code with CONFIG_ARM64. Change-Id: I430b441cc23c88ef947ddb7c5aa1836d06dbabf9 Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/196609 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2013-11-04arm: tegra: add function to enter LP0 from cpuidlePrashant Gaikwad
Bug 1254633 Change-Id: I8c69d238877615a594bed6542462873f897e0ad4 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/309496 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-16arm: tegra: update power state residencyPrashant Gaikwad
Update minimum residency expected for different power states as derived from analysis done in bug 1347388 Bug 1347388 Change-Id: Ifd3d1e68d58a3c0bf5015b33be5ed8c926dd1e91 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/299462 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14ARM: tegra: power: Enable cluster switch instrumentationAlex Frid
Enabled cluster switch instrumentation by default. Change-Id: Id55dc7f4a0d16946f80d359c92ce9f03ec1bf967 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262860 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: PMC DT supportBitan Biswas
PMC DT support changes are as follows: - Downstream code needs local changes in addition to upstream PMC DT support change to compile fine. Common clock framework (CCF) is not enabled downstream today as a result we cannot switch to upstream version of the function set_power_timers today. - All PMC platform data from board files is not available in DT bindings upstream. Using the board passed values in such cases to ensure that functionality is intact. - Further, if DT attribute values do not match board platform data settings the board setting is used for the time being. bug 1173104 Change-Id: Ife63ab84178c5aa4371bfee188ce919a99f651fc Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/263727
2013-09-14ARM: tegra: power: Support CPU rail early startupAlex Frid
Added an option for cluster switch procedure to turn CPU rail ON via direct access to PMC registers before disabling interrupts, and then continue scheduler execution while the rail is ramping up. RAM repair is executed in s/w as well after rail ramp is done. Only non-CPU partition is power-gated/un-gated by flow controller in the atomic section. However, rail ramp in this case is serialized with CPU save context. Hence the trade-off: early startup option reduces interrupt disabled time during cluster switch, but increases overall cluster switch time. Bug 1351735 Change-Id: I5ff9afb2aa6b27b9aa4b2318ee2740dee4908e2f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262864 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: power: Add cluster switch time statsAlex Frid
Expanded cluster switch instrumentation with simple timing statistic: running window average, exponential average, maximum switch time - aggregated separately for LP/G and G/LP cluster switch. Added the respective debugfs node. Moved cluster switch start/end timing samples to exactly match interrupt-disabled section of the switch. Replaced cluster instrumentation error message with debug print. The INSTRUMENT_CLUSTER_SWITCH compile option is still disabled, so by default all changes in this commit are not compiled in. Change-Id: If7b9c7b1469f6839e20b7c8db3aa9cf2c0592f2d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262859 Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra14: clock: Update EMC suspend configurationAlex Frid
- Set EMC suspend rate to minimum requested by base-band controller - Specify LP1BB voltage level based on EMC suspend rate (will actually be set by LP1BB entry code) Bug 1300939 Change-Id: Ida480539b5a71e13bfd8d00bb19724f4f85927e6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/240305 (cherry picked from commit 4777a040200d582b318ccb247299ddcd4675ac5d) Reviewed-on: http://git-master/r/262031 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra: power: Update DFLL bypass start/suspend/resumeAlex Frid
- Initialized DFLL before legacy dvfs if DFLL bypass is enabled (reversed common initialization order: first legacy dvfs - then DFLL, since DFLL bypass device is used as regulator by legacy dvfs) - Isolated DFLL output from voltage supply on entry to any state with CPU cluster powered down (suspend, cluster idle), and resumed normal operation on exit. This is necessary to avoid unpredictable effect of DFLL output on CPU voltage during power transitions. Bug 1310396 Change-Id: Ie42b92633367337ebc08200ab425baaf9043d133 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/257346 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14arm: tegra14: bbc: update core suspend about EMC rateVinayak Pane
Inform LP1BB entry part about the current BBC emc floor and the corresponding voltage required. These EMC parameters can be used by LP1 entry low power routine to set optimal values before entering in LP1BB hw state. The EMC parameter should also be used by lp1bb exit routine to set the required EMC frequency and voltage to minimize suspend-resume latency. Bug 1270116 Bug 1301005 Change-Id: I1a979ae92fd4d579cd5ecc293f5c40203b440e4d Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/238239 (cherry picked from commit 6b083a4101c7d30dd14b391b2381ed91b938306f) Reviewed-on: http://git-master/r/254495 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14ARM: tegra: USB1 VBUS and ID ANY wake level supportBitan Biswas
This change enables wakeup from USB cable connect and disconnect for both device(VBUS) and host(ID) cables. - board platform data used to enable the implementation - chip specific wakeups source file added with new API needed to detect VBUS and ID cable connect state - chip specific API exposed to return the USB1_VBUS and USB1_ID wake indices Moved dummy implementation of USB wake support APIs from chip-specific source into common file bug 1286802 bug 1314875 Change-Id: I59cfca82a907d33190a5bc92f33de5986fada43f Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/231918 (cherry picked from commit 75e8f1f218422013055c4fbcf96ceab059c933a7) Reviewed-on: http://git-master/r/241033 (cherry picked from commit 3f65b627372c37b4726084bec1129b9b2dabfe4f) Change-Id: Iae4db0cec2dbee6feef229b308b2b86340affd17 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/242383 (cherry picked from commit ba1bb5314fc5d877ab3bcd4e4530501e4f604dd4) Reviewed-on: http://git-master/r/243438 (cherry picked from commit 7beaa748094e754c0bf7bd5f946c9a314949d2b9) Reviewed-on: http://git-master/r/247106 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra: Add LP1 temp-based wakeup paramsDaniel Solomon
Add parameters to nct1008_pdata: - suspend_ext_limit_hi/_lo: limits of allowed temperature during suspend, outside of which an interrupt is triggered - suspend_with_wakeup: function pointer to check for desired NCT suspend type. For Tegra, this function returns true if suspend mode is LP1. Currently this functionality is only added to Pluto. Bug 1261915 Change-Id: I190721a42ee1e06961368f5c6f7274aa182fd49d Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/216366 (cherry picked from commit 8edbfe81583505ff51687573088615e69d469585) Reviewed-on: http://git-master/r/226449 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra: power: Add LP1 cold low voltage parameterDaniel Solomon
Currently, if CONFIG_TEGRA_LP1_LOW_COREVOLTAGE is enabled, we decrease core voltage to a level specified via lp1_core_volt_low in each platform's board file. Add another level, lp1_core_volt_low_cold, which will be used if there's a low temperature core voltage floor set during LP1 entry. Only one voltage floor exists for T30 and T114, so only one additional low voltage entry has been added. Bug 1261915 Change-Id: I614a4176b0bf68d6607a104a980d38589ebd3046 Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/216364 (cherry picked from commit b12e9b71552b89664dd8bdfc26e5e33cc9b45056) Reviewed-on: http://git-master/r/226437 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14arm: tegra: LP1 Low Core Voltage Support for T114Karthik Ramakrishnan
The feature was added for T30 and the config name referred to the lowest Core voltage for Enterprise(CONFIG_TEGRA_LP1_950). Changed the Kconfig to include T114 support and renamed the feature name to refer to the lowest Core voltage possible for the particular platform and not just 950mV. The initial change for this feature is in http://git-master/r/124135 Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> Signed-off-by: Hunk Lin <hulin@nvidia.com> (cherry picked from commit c94f740ede4809a897e18253a9c7fdfb8666970e) Reviewed-on: http://git-master/r/194260 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: Tegra: Add CONFIG_TEGRA_USE_SECURE_KERNELJames Zhao
This new config would only be enabled when we enable a secure os implementation. This config would be generic and we can reuse it if/when we change the secure os vendor. Change-Id: I94a0a365d4dc834fafa1137a0c0d9adf1b394c51 Signed-off-by: James Zhao <jamesz@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/211756 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Johnson <cwj@nvidia.com>
2013-09-14ARM: tegra11: pm: disable overriding pinmuxHarry Hong
By POR, sys_clk_req pad is enabled to override pinmux setting. this pin can be set to gpio. to avoid overriding for gpio usage, adding sysclkreq_gpio flag. Overriding pinmux will not works if this flag is set to true. bug 1236315 Change-Id: If6f30a8bfbfc272a4e303d26e2d9553e2b353bd7 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/202855 (cherry picked from commit f96759a36d68ad17a2ac9f066f36c0b2ed10026a) Reviewed-on: http://git-master/r/214386 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: Tegra: Add idle state for MC clockPrashant Gaikwad
This state puts DRAM in self-refresh. It is attached to MC clock domain, disabled initiallly and will get enabled automatically when MC clock domain is turned off. /sys/module/cpuidle_t11x/parameters/stop_mc_clk_in_idle can be used to control this state. Bug 1010971 Change-Id: Ia7d70ba1e5a4cdd8ac9cc722de20ed0cd4dabf1a Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/197386 Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14ARM: tegra14x: Add routines to maintain powermasksPrashant Malani
The decision to enter LP1BB might occur well into iRAM code. These functions will help to save and restore cpu_power_mask in case we decide to enter LP1BB in iRAM. Bug 1236920 Change-Id: Ic1e38281bdc508014d4edb3e9645c7ba89a2b4c1 Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/203166 (cherry picked from commit 8fc48afefb64fecb99db1d2cab1ac57d0af19bb2) Reviewed-on: http://git-master/r/204858 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-09-14ARM: tegra11x: Support min residency per platformBo Yan
Though there is no compelling reason to have different residency requirement of Fmin@Vmin and non-CPU power gating for each platform, still makes it possible to define these thresholds per platform. If they are not defined, the default value are taken. Change-Id: I663afb869338bd2e4078b15253c8f8e29c3d6b3c Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198846 (cherry picked from commit 841fb812bfc793c3028b72cbfa05ce26a21226c4) Reviewed-on: http://git-master/r/200860 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra11x: Define ncpu residency for 2 clustersBo Yan
There is no compelling reason to define minimum residency of non CPU power gating for each different platform. Non CPU power gating has far less dependency on platform in terms of latency when compared against rail gating. So move this parameter to CPU specific idle driver code. Define minimum residency of non CPU power gating for both slow and fast cluster. The entry criteria is different for two clusters, so different value are required. Change-Id: I3f734d056f6de6a804ca4c14e037a98bc07c646d Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/197537 Reviewed-on: http://git-master/r/200856 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra: add "memory" to clobber listPeter De Schrijver
The inline asm needs "memory" in its clobber list to prevent gcc from caching the mcr read too agressively. Bug 1207116 Change-Id: Ia93e8115b9bd8bf0539e7b7d55ffeda2efc0e7e6 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/200751 Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-09-14fixup pm.h move iomap.hDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: Fix cluster switch issue for T14XSeshendra Gadagottu
Getting cluster ID by reading MPIDR register is not working for T14x. For this issue, HW bug 1212957 is submitted. SW will use FLOWCONTROLLER_CLUSTER_CONTROL register to know the active clusterID. Change-Id: Ib1c02e27b39fba10d4d8027f6a90bae7c3024d31 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/188498 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: Get cluster ID by reading MPIDRBo Yan
This is to avoid MMIO access, thus save a few processor cycles. Change-Id: Ib4a2aaf8e991885baab51cd74a37387e91cfb5a8 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/171656 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14ARM: tegra11: power: Update core EDP on CPU cluster switchAlex Frid
Update core EDP limits when CPU cluster is switched between fast (G-mode) CPU, and slow (LP-mode) CPU. Bug 1165638 Change-Id: I956eb5ab2d8fbe873f998cca1e22984413cf5743 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/165617 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14arm: tegra: API for cluster switchingNitin Agrawal
API for doing cluster switching so that we can do cluster switching within the kernel from another process explictly. Bug 1058804 Reviewed-on: http://git-master/r/141961 (cherry picked from commit 96e05643a4b1ea2c566ab5cf07642645f4f935bb) Signed-off-by: Nitin Agrawal <nitina@nvidia.com> Change-Id: Ic4821fbd507327d7c951ab74ae7b1febc6f5bbe6 Reviewed-on: http://git-master/r/161869 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Nagaraj Kolur <nkolur@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra11x: cpuidle: Remove LP2 referencesBo Yan
This change completely removes references to lp2 in cpuidle-t11x.c, some related changes also affect cpuidle-t2.c, cpuidle-t3.c, and a few other files. bug 1034196 Change-Id: Ic2387bf614b39bd08ed4b2fc6e996f6fbf8306c0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/160017 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2013-09-14ARM: tegra11x: make SMP disabled compilesJong Kim
Make kernel compiles for disabled CONFIG_SMP. bug 1057875 Change-Id: Ie7161a86279d31245290f4e74027c1cc5e646790 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/160361 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Allen Martin <amartin@nvidia.com> Rebase-Id: R4ea53210dffe973551e939137c9f33fce96db316
2013-09-14ARM: tegra11x: CPUID virtualization supportBo Yan
This is the first patch to support CPUID virtualization. The goal is to treat all CPUs as equal in software. In current implementation, CPU0 is the anchor CPU, which must be the first one brought up, and the last one taken down. This patch removes that restriction. the cluster switch still has to start from CPU0 with this patch. This can not coexist with secure OS Reviewed-on: http://git-master/r/144610 (cherry picked from commit d32fba4be39e3f9a95ef5ab44d0c64dc6d2808a3) Change-Id: Ib7fcaae751d17fee839a4f228f5ef5c3ee2390c2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/159486 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R09e29d45acf92b3ad2d909d5438c3375aa85e7dd
2013-09-14ARM: tegra11x: residency time for different LP2 modeBo Yan
Select CPU partition power gating only, non-CPU power gating, or rail gating based on the required minimum residency and requested sleep length. The minimum residency for non-cpu power gating and rail-gating are arbitrarily set in this change, they have to be characterized. The minimum residency for non-cpu power gating shall always be less than the minimu residency for rail gating. Also fix a bug that prevents rail-gating Change-Id: Icc646061f0fb47662fa74e77c6ae6b5d5da1444a Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/146640 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rd2f8f5583057310c04bf0ea1d1bd8cdbbd15a9a6
2013-09-14ARM: tegra11x: CPU start up fixBo Yan
The first time when a CPU powers up in kernel, it has to be done by directly toggling PMC register. Subsequent CPU power up sequence is controlled by flow controller. This is done after LP0 exit as well. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/143296 Change-Id: If32712706d827e4d0337d75163449cfa0a3a50f8 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146484 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R8909dae486432fd628e8d89735634eee26063f4e
2013-09-14Revert "arm: tegra: optimize L2 enable/disable paths for secureos"Deepak Nibade
With this revert, Dalmore enters LP0 state in Main Otherwise NULL exception is encountered (variable l2x0_base) Revert is required till we get proper secureos code and we ensure that T114 does not enter l2x0 code This reverts commit 7274dfdea8e1512b863438d4f34074a67b5b4a97. Change-Id: Ib3ff4f1664fdc1693c2768eb3ecc0205a456c982 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/145288 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R147929cee9916146be1ce2a0f22895afd5d3622f
2013-09-14arm: tegra: optimize L2 enable/disable paths for secureosVarun Wadekar
For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Reviewed-on: http://git-master/r/119786 Original-author: Chris Johnson <cwj@nvidia.com> Change-Id: Iebcf1042ce2b58513e40e9d49f87ecec9dfdd301 Signed-off-by: Chris Johnson <cwj@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/130061 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R4dde3b2e285d5917bdba15a318ac18702eb59c90
2013-09-14arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: Re0625362698d402125337251c6b8337c2b2eb52d
2013-09-14Revert "arm: tegra: optimize L2 enable/disable paths for secureos"Varun Wadekar
This reverts commit 7ac85a9d58b51352605c845a0066c949c0c85f72. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R5fe5ed9d55ec2405b1e869d1e10342702fe1b95b
2013-09-14arm: tegra: optimize L2 enable/disable paths for secureosHyung Taek Ryoo
For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Bug 939415 Signed-off-by: Chris Johnson<cwj@nvidia.com> Change-Id: I756d2ceda83d5d8d6bc5670218e9d874d5e5f62a Reviewed-on: http://git-master/r/119786 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R3ef57b700f11d16ca5821194ab8144fd97a9fb47
2013-09-14ARM: tegra: reset io dpd modeBitan Biswas
Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R2a63cb307f02dc2870e73c6a9fcc73e8c76dca32
2013-09-14ARM: tegra: New macro name for LP2 timer configBo Yan
The config macro TEGRA_LP2_ARM_TWD was defined when only Cortex-A9 was used in Tegra SoC, but the feature enabled by this configuration option is not just for Cortex-A9. In fact, any CPU with private timer can make use of this feature. Therefore, change macro name to a more generic one "TEGRA_LP2_CPU_TIMER" so it can be used with new CPU architecture (CortexA15) Change-Id: I6903dba056c554c72bb8d1416df90145a4043295 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/118099 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Rebase-Id: R0da9d17d0281e91f5908099579b8eaaf4b01a024
2013-09-14arm: tegra: sd: enable sd dpdWen Yi
This is a WAR solution that allows for the turning on SD DPD feature. The original issue is that enabling SD DPD immediately after device comes out of LP0 causes ULPI disconnect. The root cause of that is not known. The WAR is to delay the enabling of SD DPD for 100ms after device comes out of LP0. Bug 929628 Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4 Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9) Reviewed-on: http://git-master/r/113392 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rd4728fda7b23fa349f48b19c054ed412bf10e089
2013-09-14ARM: tegra: Clean up flow controller CSR macrosBo Yan
Group flow controller macros for CSR register in one place in sleep.h Also strip "CPU" out of macro names because the corresponding COP CSR register has only one field INTR_FLAG which is at bit 15, same as CPU CSR, so there is no confusion here. Change-Id: Ib3dea0bd3e9051d1e7b9048abc4afde5ddc8bab5 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/103478 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Rebase-Id: R63c198f17e573818b8d44482c46cb61516bf1267
2013-09-14ARM: tegra11: CPU rail power up sequenceBo Yan
It is necessary to disable RAM repair bypass when CPU rail is powered up. This needs to be done even in case of HW controlled CPU rail power-on. This change also enables cluster switch to use "power_gate" flag defined in sysfs to control the power gating mode. For LP0 entry case, rail-gating is set to default. Set default power gating mode for cluster switch to rail gating. For chips that doesn't support symmetric power gating, "0" is the default value which will trigger rail-gating. Change-Id: Ia7ccb023118bbfba4fa53dc263bdfda59e29f089 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/101045 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R50b64bfc236a664028edc822219af0d30d1af043
2013-09-14ARM: tegra: power: Use Tegra3 LP2 timer functions for Tegra11xScott Williams
Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/50395 (cherry picked from commit efb2c5d7c6d873002f2f156a4c622b6e0a3aed36) Change-Id: I23baa13790ca9cb1b445bd4e4972dd5ab9f14903 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/77456 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mark Stadler <mastadler@nvidia.com> Tested-by: Mark Stadler <mastadler@nvidia.com> Rebase-Id: R129f1e31d9f61caf36723806c2147d76eb40c0d1
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-03 20:45:11 +0000