summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/sleep-t2.S
AgeCommit message (Collapse)Author
2012-11-27tegra: fix file names and paths in commentsMarcel Ziswiler
Several file names and paths showed copy/paste or otherwise issues.
2012-04-19Revert "ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPEND"Sang-Hun Lee
This reverts commit e6d0e0ceec7cd1a7b8085eb31d2e70bc4d15684f. Bug 967887 Change-Id: I60927a93ebdf6ba4da14311f8ffcc1edf4f56391 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96788 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: tegra: rethink the cpu suspend-resume code path"Sang-Hun Lee
This reverts commit f31ca2d9e0580b58dc51fde31fc8ace190dd253b. Bug 967887 Change-Id: I3fe975f7a6939cace5e208947bcb82e09008c0ac Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96787 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: tegra20: pm: flush L1 data before exit coherency"Sang-Hun Lee
This reverts commit 209209a303742d6312f66896b4351dd97e48e24c. Bug 967887 Change-Id: I2464db28b5a4970d6e60ef79c89c2107c64cb6d3 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96786 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-05ARM: tegra20: pm: flush L1 data before exit coherencyPrashant Gaikwad
Bug 934368 Change-Id: I960d8ae5c6390e719b8ee6c9cbc067cf8d28122d Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/92543 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-04-05ARM: tegra: rethink the cpu suspend-resume code pathVarun Wadekar
The current kernel methodology expects that tegra_cpu_suspend is actually the last function in the entire suspend sequence. In order to achieve this, the code needs to be remodelled a bit so that we actually execute native cpu_suspend at the end of the suspend sequence. This allows us to leverage all the cpu_suspend code developed by ARM in the upstream kernels. Bug 934368 Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/84481 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-05ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPENDVarun Wadekar
Bug 934368 Change-Id: Ic9d75cbb0c324b1858b2e476e33dd4f96349bce3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/86351 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-01-06ARM: tegra: power: L2 cache sync only for CPU0 LP2Prashant Gaikwad
Bug 922010 Change-Id: I19724ae5d8421b2fccfc604ecb0a867d20fddf75 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/72986 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-12-15arm: tegra: Invalidate TLB/BTAC afer enabling coherencyPrashant Gaikwad
Change-Id: Idaf841e245f3bccaae77375bb839e8c00bbc7542 Reviewed-on: http://git-master/r/67592 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-12-08arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-30ARM: tegra: power: Correct PL310 virt addr calculationPuneet Saxena
PL310 virtual address was calculated using PPSB virtual/phy address. It should be done using CPU virtual/phy address. This causes TEGRA_PL310_VIRT value to get overlapped with virtual kerenl memory map's Vmalloc region on whistler. Bug 881831 Bug 867094 Change-Id: Ifaeeb9291553af59453f0041ad7cb1fe9d27979b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/62097 Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Rebase-Id: Ra5a6165c8a02f0ac130bbaac4a477b901ceea62f
2011-11-30arm: tegra: pm: issue a pl310 cache sync for tegra2Mayuresh Kulkarni
this needs to be done when the lp2 is aborted before the stipulated programmed time to wake-up for bug 867094 Change-Id: I02102ed8afa69d782de5950118352e80edc79df4 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/52581 Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R5938771982b7cceb9ea23ee73852ca8b9b3490ae
2011-11-30ARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cacheJin Qian
Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef Reviewed-on: http://git-master/r/49053 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f
2011-11-30ARM: tegra2: power: Fix reset race condition between the CPUsScott Williams
During LP2 for CPU idle on Tegra2, there could be a race condition between the CPUs. CPU1 cannot autonomously shut itself down (put itself into reset). CPU1 must be reset by CPU0 but only when it has no outstanding memory or I/O transactions going on (i.e., it is in the WFI state). CPU1 indicates its readiness to be reset by setting status in a PMC scratch register. If CPU1 wakes up and CPU0 sees CPU1's ready to be reset status before CPU1 can clear it CPU1 could be reset at inappropriate times resulting in loss of cache coherency and ultimately a kernel panic. Eliminate the race condition by ensuring that: - CPU1's reset ready status is cleared as early as possible before CPU1 rejoins the coherent world. - Use writel when updating the IRAM LP2 status flags to ensure the IRAM and coherent memory views of the flags are consistent. - If there is not enough time remaining for CPU1 to be in LP2 for the minimum residency time, clear CPU1's reset status flag before entering WFI so that CPU0 will not wait for CPU1 to be ready to reset (since it won't be if there is insufficient time). Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848
2011-11-30ARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2Scott Williams
Don't try to flush the L1 D-cache for an aborted LP2 on the secondary CPU if the L2 cache is enabled. The L1 cache will have already been flushed and disabled by the suspend-side code. Change-Id: If6fc7bd0f7d630e6cdcda6824411503f346c5405 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc50e525a320986432d2b125f82f846f94f605cc3
2011-11-30ARM: tegra: power: Save CPU context to non-cacheable stackScott Williams
The standard cpu_suspend does not work if there is an exernal L2 cache in the system individual CPUs are suspending without shutting down the whole CPU complex. As a workaround for this problem, we must save the CPU context to a non-cacheable region of memory. Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930
2011-11-30ARM: tegra: power: Add stack frame debug checksScott Williams
Tag the stack frame created by the CPU register context push macro with a magic number and validate that magic number in the register context pop macro to ensure that the stack remains balanced and uncorrupted. Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60
2011-11-30ARM: tegra: power: Define push/pop context register macrosScott Williams
Define macros to ensure that the behavior of push/pop of the context regsiter set is consistent across all callers. Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4
2011-11-30ARM: tegra: power: Use uniform save/restore register setScott Williams
Modify the register usage of tegra_cpu_save so that the same set of registers is saved to and restored from the stack. Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59
2011-11-30ARM: tegra: power: Consolidate CPU context save and SMP exitScott Williams
Every call to tegra_cpu_save is always followed by a call to tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save by folding the CPU context save functionality of cpu_suspend and the coherency exit functionality into a single function called tegra_cpu_suspend. Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8
2011-11-30ARM: tegra: Use common coherency exit function for Tegra2Scott Williams
Change-Id: Ibbc9c2a38fb654e24b1edb4ee7bbcaf285bf0f7d Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R9ff092cf658b71d8f79ef3901bd5067d18548e69
2011-11-30ARM: tegra: power: Clean up stack pointer handlingScott Williams
Clean up some rather fragile manipulation of the stack pointer in the CPU suspend code. It's all unnecssary except in one case where Tegra2 can abort a suspend because of activity on the other CPU. Change-Id: Ic872364c5abd58f704b2afeeae4d8722f127d3bb Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5873dd120df2e98cc5bfcc74f86ebea6cc10f9b2
2011-11-30ARM: tegra: power: Split CPU context save and coherency exitScott Williams
Separate the CPU context save and CPU coherency exit into separate functions. Change-Id: I7c5376677e293342b02b5bebdef6be2610522936 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d
2011-11-30ARM: tegra: Rename tegra<n>_sleep_resetScott Williams
Rename tegra<n>_sleep_reset to tegra<n>_hotplug_shutdown since that is more descriptive of their actual function. Change-Id: I411e2474bd35a799d5367a182809d17933238612 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R72bf50004ab3fcdde5485b84b7ba008247d1bf4c
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra2: Fix CONFIG_HOTPLUG_CPU dependenciesScott Williams
Change-Id: I54fab1134f2c51337da6f7b2ccc5ab304b600dea Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R45b2521f5d574774f1db13f6ef9ade5c116da9b4
2011-11-30ARM: tegra: Rename flow control registersScott Williams
Change-Id: I2647718dc9c9420e57b24a810738c33ef05bcf61 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6d5c6a52a2b0fd1dafd021d4a187528aeca26516
2011-11-30ARM: tegra: Always compile sleep.SScott Williams
Decouple LP3 (WFI) mode and CPU hotplug shutdown from CONFIG_PM_SLEEP. Change-Id: Ie959fa5e044ab4a7f84772d3b743ce2680465acc Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R8f01e646e7bf65350db44557de87c4c2a33d8059
2011-11-30ARM: tegra: sleep: Remove hard-coded register offsetScott Williams
Change-Id: I0fb4dc6ff2158d2d9661e3a231e02fc3ae0cc86e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra4a5d9780d6329b2d029e3391c5d5145940c29c7
2011-11-30ARM: tegra: Fail when tegra2_cpu_reset is called by CPU 0Scott Williams
CPU 0 must be the last CPU to shutdown since it's the only one that can perform CPU power gating or rail gating. Therefore, CPU 0 can reset CPU 1, but the reverse is not allowed. Change-Id: I61296ee49d219a67c1fb864badc1170cd4684f8e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R722033713d671fe702d9a7c0813993f9c7e6bd01
2011-11-30ARM: tegra2: Don't use tegra_cpu_save to exit coherency on resetScott Williams
Change tegra2_sleep_reset not to depend on tegra_cpu_save to exit coherency. Now tegra2_sleep_reset no longer depends on CONFIG_PM_SLEEP Change-Id: I478e723e826fd3ddbd6a6e8bceaedf795bd2ee26 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2138dcf60971f7a9ad78e6a39fc2206c99faf7b5
2011-11-30ARM: tegra: Split sleep.S for Tegra2Scott Williams
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-10 20:55:48 +0000