summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/sleep.h
AgeCommit message (Collapse)Author
2011-11-30ARM: tegra2: power: Fix reset race condition between the CPUsScott Williams
During LP2 for CPU idle on Tegra2, there could be a race condition between the CPUs. CPU1 cannot autonomously shut itself down (put itself into reset). CPU1 must be reset by CPU0 but only when it has no outstanding memory or I/O transactions going on (i.e., it is in the WFI state). CPU1 indicates its readiness to be reset by setting status in a PMC scratch register. If CPU1 wakes up and CPU0 sees CPU1's ready to be reset status before CPU1 can clear it CPU1 could be reset at inappropriate times resulting in loss of cache coherency and ultimately a kernel panic. Eliminate the race condition by ensuring that: - CPU1's reset ready status is cleared as early as possible before CPU1 rejoins the coherent world. - Use writel when updating the IRAM LP2 status flags to ensure the IRAM and coherent memory views of the flags are consistent. - If there is not enough time remaining for CPU1 to be in LP2 for the minimum residency time, clear CPU1's reset status flag before entering WFI so that CPU0 will not wait for CPU1 to be ready to reset (since it won't be if there is insufficient time). Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848
2011-11-30ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmuScott Williams
The common ARM CPU state suspend/resume code does not work with and external L2 cache controller (like a PL310) enabled. This change fixes corruption of the current PMD by the MMU resume code. cpu_resume_mmu modifies the currently active page tables to add a flat (VA==PA) section mapping of cpu_resume_turn_mmu_on to handle MMU off-to-on transition. It turns off the L1 data cache but it knows nothing of the L2 cache. Since page table walks are L2 cacheable, other CPUs in the system can pick up the corrupted PMD which will eventually result in a kernel panic. The workaround for this is to modify push_ctx_regs to save the current TTB0 and CONTEXID registers in the CPU register context and switch to the private tegra_pgd before saving the rest of the CPU context. The tegra_pgd already has a flat mapping for the code in question, so it can't be damaged by the actions of cpu_resume_mmu. Likewise, pop_ctx_regs is modified to restore the actual TTB0 and CONTEXTID registers when restoring the CPU registers. Change-Id: Ided2b31cbea0b0abb934e64cf056e85e1a3f06ae Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R3f6ca9c63752430395fdf8375b82794abc9776af
2011-11-30ARM: tegra: power: Conditionalize diagnostic register save/restoreScott Williams
Change-Id: I540d7272d585331da0241e7878dbb35557f0bb99 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R59fe634cc803ba2c9bb7916046aff5f92120f5c3
2011-11-30ARM: tegra: power: Save CPU context to non-cacheable stackScott Williams
The standard cpu_suspend does not work if there is an exernal L2 cache in the system individual CPUs are suspending without shutting down the whole CPU complex. As a workaround for this problem, we must save the CPU context to a non-cacheable region of memory. Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930
2011-11-30ARM: tegra: power: Add stack frame debug checksScott Williams
Tag the stack frame created by the CPU register context push macro with a magic number and validate that magic number in the register context pop macro to ensure that the stack remains balanced and uncorrupted. Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60
2011-11-30ARM: tegra: power: Define push/pop context register macrosScott Williams
Define macros to ensure that the behavior of push/pop of the context regsiter set is consistent across all callers. Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4
2011-11-30ARM: tegra: power: Clear cache/TLB forwarding when exiting SMPScott Williams
When exiting SMP coherency, clear cache and TLB operation forwarding. Change-Id: Id91331b60eb40e47591fb0282820e31b14e027d5 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R4d7697d029fa1b9d30ff612fad940f1c65b3b376
2011-11-30ARM: tegra: power: Add SMP coherency exit macroScott Williams
Define the SMP coherency exit code as a macro to allow it to be inlined in assembly code that needs to control its register usage. Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a
2011-11-30ARM: tegra: power: Add LP2 in idle support for secondary CPUsScott Williams
Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: Add Tegra 3 CPU hotplug supportScott Williams
Change-Id: Ie43f4efdf884a916c6bc9737157091c35dc44501 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1f023651504a7d336f7e98921f6372bee0aa1341
2011-11-30ARM: tegra: power: Consolidate power management flagsScott Williams
Consolidate all of the power management control flags in one header and adjust the values of the software flags so that they do not conflict with the values of the hardware flags. Change-Id: I7971d274946d84dcc50bd9d9e0190091ebbefa2e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R29d2420a74f977c16f73b1abd9ca7470695a53f4
2011-11-30ARM: tegra: Rename tegra<n>_sleep_resetScott Williams
Rename tegra<n>_sleep_reset to tegra<n>_hotplug_shutdown since that is more descriptive of their actual function. Change-Id: I411e2474bd35a799d5367a182809d17933238612 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R72bf50004ab3fcdde5485b84b7ba008247d1bf4c
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: Trivial changesScott Williams
Change-Id: Id45f6be8336370bf011484bea0a90e7e9f49f026 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R06af455b61cb70a1a7dc18b38ad3f816d4ccba63
2011-11-30ARM: tegra: Consolidate flow control registersScott Williams
Change-Id: I07ffcffafcf47fd7539b22d4829712e041293bf3 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R34a7800e24254d54b499411652d59421be703619
2011-11-30ARM: tegra: Rename flow control registersScott Williams
Change-Id: I2647718dc9c9420e57b24a810738c33ef05bcf61 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6d5c6a52a2b0fd1dafd021d4a187528aeca26516
2011-11-30ARM: tegra: Split sleep.S for Tegra2Scott Williams
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
2011-11-30ARM: tegra: Add cpuidle.hScott Williams
Change-Id: I75ec091f9dcd0fa3fa56b1542f58a02006c1a314 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ree5fce2632aff6dc59879817ad7ad3f2b1538244
2011-11-30ARM: tegra: Finish power.h -> sleep.h renameScott Williams
Change-Id: I7e7698ee3a0b51e5d7ea21212806701b34e39064 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R324cb2c52cc2967be1189ef64ee6ac1bee8f60d0
2011-11-30ARM: tegra: power: Restore LP2 in idle protectionsScott Williams
Restore the code that was dropped in the port to Linux 2.6.39 that protects against using LP2 mode for idle when the platform suspend mode has disallowed the use of LP2 mode. Also cleans up some warning messages. Change-Id: I357210b8a272c10bf7c1e773342dc864bbddb74e Reviewed-on: http://git-master/r/40463 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6a60e3f0f2ebf06ec9701475af41679c24ef80ab
2011-11-30ARM: tegra: Add suspend supportColin Cross
Tegra supports three low power modes that involve powering down the CPU. LP2 powers down both CPU cores and the GICs, but leaves the core peripherals, including the memory controller and the legacy interrupt controller, enabled. The legacy interrupt controller is used as the wakeup source, and any interrupt can wake the device. LP2 can be used in idle. LP1 is the same as LP2, but in addition turns off the memory controller and puts the DDR memory in self-refresh. Any interrupt can wake the device. LP1 could be used in idle if no peripherals are doing DMA. LP0 turns off everything in the SoC except the RTC and a power management controller, both of which run off a 32 kHz clock. The power management controller has 32 wake sources, all other interrupts can not be used to wake from LP0. These low power modes power-gate the main CPU complex, requiring a full processor state save and restore from a reset vector. Platform-specific data (power good times, PMU capabilities, etc.) must be specified when registering the suspend operations to ensure that platform power sequencing restrictions are maintained. In both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely perform this transition, the final shutdown procedure responsible for * turning off the MMU and L1 data cache * putting memory into self-refresh * setting the DDR pads to the lowest power state * and turning off PLLs is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the start of the suspend process. In LP1 mode (like LP2), the CPU is reset and executes the code specified at the EVP reset vector. Since SDRAM is in self-refresh, this code must also be located in IRAM, and it must re-enable DRAM before restoring the full context. In this implementation, it enables the CPU on PLLP, enables PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset vector to restore the rest of the system (MMU, PLLX, coresite, etc.). The LP2 reset vector is expected to be found in PMC_SCRATCH1, and is initialized during system-bootup. In LP0 mode, the core voltage domain is also shutoff. As a result, all of the volatile state in the core voltage domain (e.g., pinmux registers, clock registers, etc.) must be saved to memory so that it can be restored after the system resumes. A limited set of wakeups are available from LP0, and the correct levels for the wakeups must be programmed into the PMC wakepad configuration register prior to system shutdown. On resume, the system resets into the boot ROM, and the boot ROM restores SDRAM and other system state using values saved during kernel initialization in the PMC scratch registers. Resuming from LP0 requires the boot ROM to supply a signed recovery codeblob to the kernel; the kernel expects that the length and address of this blob is supplied with the lp0_vec= command line argument; if not present, suspend- to-LP0 will be disabled For simplicity, the outer cache is shutdown for both LP0 and LP1; it is possible to optimize the LP1 routine to bypass outer cache shutdown and restart. Includes fixes from: Scott Williams <scwilliams@nvidia.com> Aleksandr Frid <afrid@nvidia.com> Vik Kasivajhula <tkasivajhula@nvidia.com> Bharat Nihalani <Kbnihalani@nvidia.com> James Wylder <james.wylder@motorola.com> Allen Martin <amartin@nvidia.com> Change-Id: I9e4e61c2fbb8c7bb5a29b1832ea38e7ea0524c52 Original-author: Gary King <gking@nvidia.com> Signed-off-by: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 14:35:16 +0000