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2017-09-20tegra11_soctherm.c: fix compilation with gcc 7Max Krummenacher
With gcc 7 the following compile time error occurs: | arch/arm/mach-tegra/tegra11_soctherm.c:2978:40: error: the omitted middle operand in ?: will always be 'true', suggest explicit middle operand [-Werror=parentheses] | s->sensor_enable = s->sensor_enable ?: therm->zone_enable; | ^ Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2014-08-18arm: tegra: soctherm: revert reprogram suppressionDiwakar Tundlam
Suppressing reprogramming HW registers saves very little but can potentially result in suppressing all HW interrupts from soctherm. Bug 1536511 Change-Id: I57a78f7955089c60dde89e81ed8d88d9f408f364 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/453269 (cherry picked from commit d4428beada43ba8849eb98ec1e42e13e60fe5c4b) Reviewed-on: http://git-master/r/456766 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-06-19arm: tegra: soctherm: fix pskip bypass programDiwakar Tundlam
Fix PSKIP configuration in soctherm for T132 chipset. Bypass ramp rate only in soctherm, but program the similar registers in ccroc the same as before as in soctherm for correct throttling behavior. Also added a clear comment noting the restriction of mapping throttling_depth string and actual throttle depth configuration in T13x due to indirect vector-based throttle selection. Change-Id: I86635101fc61229e54b22db67f134917e6a7e0aa Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/423359 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com>
2014-06-13arm: tegra: soctherm: fix throt level debugDiwakar Tundlam
This change fixes the show-regs output for OC5 throttle which broke when "refactor throt level & vect" change was reverted. Bug 200006274 Bug 200009441 Change-Id: I5a0843098baa7a6d041ceac86102d25d98dbae99 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/421891 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-06-13thermal: remove all unsigned type use for temperatureDiwakar Tundlam
Bug 1516918 Change-Id: I5615b0657d255d9134415d92d372771baa4271e1 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/420818 GVS: Gerrit_Virtual_Submit Reviewed-by: Josh Kuo <joshk@nvidia.com> Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>
2014-06-05Revert "arm: tegra: soctherm: refactor throt level & vect."Diwakar Tundlam
Bug 200009441 This reverts commit 392b7dbbf3d76f2db05eea05bcf8e1bd9610220b. Change-Id: I6e58562942b391796b8fa337074c3806921f4572 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/419238 Reviewed-by: Tony Ly <tly@nvidia.com> Tested-by: Tony Ly <tly@nvidia.com>
2014-06-05arm: tegra: soctherm: Update temp threshold with critical trip tempRoger Ma
Takes critical trip temp into hardware while updating temperature UP/DN thresholds to ensure that SW shutsown is working at critical trip temp with UART log of thermal shutdown even. Bug 1492653 Change-Id: I10094c3d5ee32171197f792880b85bcdd519e7eb Signed-off-by: Roger Ma <roma@nvidia.com> (cherry picked from commit 5eaccbbc5c44b5e4c61e28de256e1e9be7e53b3b) Reviewed-on: http://git-master/r/418481 Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-06-02arm: tegra: soctherm: split suspend and resume nbDiwakar Tundlam
Split soctherm suspend and resume notifier callbacks to allow different priority settings so that soctherm-suspend is called after dvfs-resume and soctherm-resume is called before dvfs-resume. Change-Id: I269a7851f4131f1b900c6a813a203a6d49c50c6a Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/416815 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2014-05-29arm: tegra: soctherm: refactor throt level & vect.Diwakar Tundlam
CPU HW throttling configuration is done in two stages. First stage in soctherm register space has a vector and the second stage in CCROC register space has the depths for each of these vectors. Although there are only 3 vectors, no-vector is also a valid configuration. Changed code to allow for NONE vector and use that for OC5. Also modified debug show command to display throttle depth and vector information as per new format. Bug 200006274 Change-Id: Ie56a99a4eeff44c033ed69beadbee1987a86c903 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/414262 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com>
2014-05-13arm: tegra: soctherm: cap hotspot offset on switchDiwakar Tundlam
If CPU-zone temp reads a lot higher than PLL-zone in a transient scenario, we would program a huge hotspot offset value which would cause spuriously high temperatures when we actually switch to PLL-TSOSC. In the issue described in the bug, this seems to cause a spurious shutdown. We fix this by capping the dynamic hotspot offset to the maximum defined by specification. Also use signed vars to work with -ve temps. Bug 1511045 Change-Id: Ia5803103e951105382c937de8c75f82e4f166b16 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/407794 Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com>
2014-05-13arm: tegra: thermal: new ATE rev and marginsDiwakar Tundlam
Added check for new ATE rev (0.9+). Added WAR for ATE revs 0.9-0.11 - continue to use PLL-TSOSC for thermals. Updated thermal thresholds and CPU and GPU EDP margins per thermal margins spreadsheet. Bug 1429685 Bug 1510809 Bug 1511626 Change-Id: I78528be0ed6b01625dd464054fbbf39c810c8873 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/407793 Reviewed-by: Automatic_Commit_Validation_User
2014-05-08sysedp: tn8: enable SW feedback for battery OC throttlingTimo Alho
* Enable battery OC hardware throttling on E1971 platform * Enable SW feedback loop on battery OC throttling on all TN8 platforms Bug 1511092 Change-Id: Iedf95e6b139661d5577519728a0fa781b525a341 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/406349 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-05-07arm: tegra: thermal: clean up fuse check apisDiwakar Tundlam
Allow fuse check api to be called only to check the fuse revision. Bug 1429685 Change-Id: I0370f237c4562814af0f41a162bccff2b3db5371 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/405474 Reviewed-on: http://git-master/r/405990 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-02arm: tegra: soctherm: add gap b/w HW & SW shutdownDiwakar Tundlam
Normally, HW shutdown threshold is programmed to be the same as the SW thermal critical temperature limit. Since HW detects this earlier, shutdown is always done by HW, and leaves no visible traces that could help debugging cases of suspected thermal shutdowns. Raise the HW shutdown threshold to be 1C higher than the SW thermal critical threshold so SW gets an opportunity to force thermal shutdown while putting out a console log message. Bug 1497873 Change-Id: I87d610c00523fa251b7a467017fa5dae37e716d4 Reviewed-on: http://git-master/r/403950 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/404069 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-04-23arm: tegra: thermal: clean up the GPU thermal pulse skipper status read pathPaul Walmsley
Clean up the GPU thermal throttling pulse skipper status read path. Add some temporary functions to indicate what features are present on what chips -- these need to be removed and replaced with some DT mechanism during the platform_driver conversion. I suspect this implementation still isn't ideal. Seems to me that we should register two separate cooling devices, one for the CPU and the other for the GPU. If SOC_THERM doesn't control CPU or GPU throttling on a given chip, then it shouldn't register the software cooling device. Instead, the driver for the IP block that handles the cooling device should do it. That should clean this code up somewhat. Bug 1201644 Bug 1380438 Bug 1482040 Change-Id: I48240ea0624842a389af74bd7f7fdc71c5f2eae8 Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Reviewed-on: http://git-master/r/397740 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-23arm: tegra: soctherm: T13x fuse correction updateDiwakar Tundlam
Added check for fuse revisions in T13x and pick the new fuse corrections table for CP revs 0.9 or higher. Bug 1429685 Change-Id: Ib0bfec7e122c22e67ef07b16a0ff7d9642c43644 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/397819 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-04-23arm: tegra: soctherm: simplify fuse correctionDiwakar Tundlam
With more chips needing fuse corrections, the old code became unwieldy due to repeated identical calculations with slightly different coefficients. Instead unify all coefficients in a structure and use it in on calculation stage. The structure setup is done depending on chip. Bug 1429685 Change-Id: I6d098fb1519d725dcfd892d440ce655618d6c525 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/397800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-04-23arm: tegra: thermal: clean up the CPU thermal pulse skipper status read pathPaul Walmsley
Clean up the CPU thermal throttling pulse skipper status read path. Add some temporary functions to indicate what features are present on what chips -- these need to be removed and replaced with some DT mechanism during the platform_driver conversion. I suspect this implementation still isn't ideal. Seems to me that we should register two separate cooling devices, one for the CPU and the other for the GPU. If SOC_THERM doesn't control CPU or GPU throttling on a given chip, then it shouldn't register the software cooling device. Instead, the driver for the IP block that handles the cooling device should do it. That should clean this code up somewhat. Bug 1201644 Bug 1380438 Bug 1482040 Change-Id: I31d913cd4d959bd4a924726fa802578970d61616 Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Reviewed-on: http://git-master/r/397452 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-23arm: tegra: thermal: remove throtctl_readl() and throtctl_writel()Paul Walmsley
In preparation for removing non-SOC_THERM IP block accesses from the driver, remove the functions throtctl_readl() and throtctl_writel(), which access registers in different IP blocks, depending on the chip in use. Instead, move the IS_T13X test into the caller, and call either clk_reset13_{read,write}l() or soctherm_{read,write}l(), as appropriate. Bug 1201644 Bug 1380438 Bug 1482040 Change-Id: I5011c814eca0920330989c1ea64cc27876d750b3 Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/395531 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-23arm: tegra13: soctherm: restore orig thresholdDiwakar Tundlam
For certain older revs of ATE, we will use use PLL-TSOSC (instead of the CPU-TSOSCs) on T132 devices to drive throttling (HW and SW) and shutdown to avoid random shutdown issues seen on some platforms. Revert T132-specific hacks in soctherm driver to prepare for the change, which is done in per-platform board-files. Bug 1468124 Change-Id: Iac8152045915ac59db45c9b30103dbbb13a784b2 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/395413
2014-04-23arm: tegra: thermal: split CPU throttle control codePaul Walmsley
For clarity, split the CPU thermal throttling pulse skipper control code, throttlectl_cpu(), into two variants. The first variant is for SoCs with CPU throttling control in the SOC_THERM block, such as T114, T148, and T124. These are programmed by setting pulse skipper M/N ratio values directly in SOC_THERM registers. The abbreviation used in the function names is "mn". The second variant is for SoCs with CPU throttling control in the CPU subsystem, such as T132. For these chips, the M/N ratio values are written to CPU subsystem registers, but the selection of which of these ratio tuples to use for a certain SoC throttling level (low, medium, heavy) is handled via SOC_THERM register writes. The abbreviation used in the function names is "level". While here, fix some minor documentation issues, and remove the pulse-skipper sequencer control code from the "level" variant, since we're not using it there. This version incorporates some comments on the function names from Matt Longnecker <mlongnecker@nvidia.com> Bug 1201644 Bug 1380438 Bug 1482040 Change-Id: Ibcfc370ee3fd83553b778f89bc419910f98b1269 Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Matt Longnecker <mlongnecker@nvidia.com> Reviewed-on: http://git-master/r/395530 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-23drivers: tegra: pmc: change name of struct tegra_tsensor_pmu_dataPaul Walmsley
At Aleks' request, change the name of struct tegra_tsensor_pmu_data, to clarify what it is and what it does. This structure has nothing to do with PMIC temperature sensors. Instead it's used to configure the boot ROM appropriately to tell the PMIC how to power off the SoC after SOC_THERM's critical thermal trip point has been reached ("thermtrip"). The name will now be 'struct tegra_thermtrip_pmic_data'. Change-Id: I40e5aeeb74267993272e33c92300d3506a15a4a8 Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Reviewed-on: http://git-master/r/396170 Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-23arm: tegra: soctherm: correct tsample_ate valueDiwakar Tundlam
For T124, the tsample rate was changed to 479 in ATE which means the SW should use the value 480, not 481. Same applies to T132. Bug 1291108 Bug 1429685 Change-Id: Ie6579aa849f58d54a6a5cff5c175d107b6ef1e65 Reviewed-on: http://git-master/r/397472 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/399255 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-04-11arm: tegra13: soctherm: loop over OC stats tooDiwakar Tundlam
Fixed loop condition so OC stats are not skipped. Bug 1497662 Change-Id: I59aa0dee4151faed07ef78c8cf4f1878dca09b83 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-07arm: tegra13: soctherm: temporary adjust throttleDiwakar Tundlam
Temporarily adjust thermal throttling parameters for T132 devices to avoid random shutdown issues seen on some platforms. Bug 1468124 Change-Id: Id7939110deae7f3076914a8a76049ca98fc843e4 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/392519
2014-04-04arm: tegra: soctherm: move PMC register accesses into PMC driverPaul Walmsley
The PMC IP block is not part of the SOC_THERM IP block, but the SOC_THERM code contains direct register reads and writes to the PMC IP block. Move these accesses into something PMC-specific: in this case, drivers/platform/tegra/pmc.c. While here, remove the usage of the REG_SET/GET* macros, since upstream Linux practice is to use the actual bit-manipulation operations, rather than these macros. This is part of the process of modifying the tegra11_soctherm.c code to convert it into a low-level device driver for the arsoc_therm IP block. We also relocate struct tegra_tsensor_pmu_data to a PMC-specific header file, since it is PMC-specific, and convert any header references to the old location to point to the new location. Thanks to Matt Longnecker for comments on the first version of this patch. Bug 1201644 Bug 1380438 Bug 1482001 Change-Id: Iea630ac9d9b3dfaab03edf44e2a2725174c7a3d8 Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-on: http://git-master/r/392198 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-04-04arm: tegra: soctherm: fuse correction for T13xDiwakar Tundlam
Start with some preliminary values to improve accuracy instead of using T124 correction parameters, which is just wrong. Bug 1429685 Change-Id: I4eaef6ca0b2549c03047575b6deff7735828d491 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/392452 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: John Hsu <johnh@nvidia.com>
2014-04-03arm: tegra13: CPU HW thermal throttling setupDiwakar Tundlam
Implement support for soctherm HW throttling per T132 throttlectl spec. CPU freq throttling is done via PSKIP configuration in CCROC NV_THERM. Bug 1312883 Bug 1479594 Change-Id: Ic76f4e3bcf2ba0ce803e58bf1b19c8e41ecdc716 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/385912 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2014-03-28arm: tegra: thermal: use correct zone pointerDiwakar Tundlam
The global index of thermal zones from thermal framework will be different from the 0-based soctherm driver's own index. Use the global index to notify framework, not the local index. Local index is used to program the HW, and is derived from the stored devdata. This fixes hw programming of thresholds in the wrong zone when written from the trip_point_x_temp sysfs node. This doesn't directly affect the bug mentioned below, but fixes a problem that occurs when trying to repro it. Bug 1482109 Change-Id: Ib03b719a51d296d3b77e99c53bcb68742576e3bb Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/387984 Reviewed-by: Automatic_Commit_Validation_User
2014-03-26arm: tegra: soctherm: check and write registersDiwakar Tundlam
There's an intentional side-effect of writing trip temperature thresholds in HW; It resets the up/down state machine that track hysteresis and can cause unnecessary thermal events (interrupts). Avoid unnecessary events by checking if the trip config register is being configured to the same settings. Although it doesn't fix the below bugs, it reduces unnecessary extra work that makes these problems worse. Bug 1463497 Bug 1478989 Change-Id: Idf07b49ca8d7da892b52ed796044c2f433e2a192 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/384656 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-03-25arm: tegra: soctherm: rename global arrayDiwakar Tundlam
Renamed global array of thermal zones to avoid masking formal argument of same type in API functions. The argument to set_trip_temp() was masked in the previous commit causing set_trip_temp via sysfs nodes to crash. Bug 1478989 Change-Id: I5dcc7b25e3fe8d66340a24088704e452ce0781da Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/385902 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-03-24arm: tegra: soctherm: fix pointer misuse in zoneidDiwakar Tundlam
Storing the integer local thermal array index in tz->devdata pointer is a misuse of pointers and gives rise to compilation warnings in 64bit builds. Fix this by storing the pointer to the local therm structure and retrieving it in the called routines. Since we can no longer have a thermal zone for each tsensor, we don't support it anymore. When handling soctherm HW interrupt, we know the exact trip_point triggered. There's no need to update the entire zone. Hence we switch to using the thermal_notify_framework API that takes the specific trip_point. Bug 1478989 Change-Id: I2211114602d54a4b0ca9d9780ce9a0b68e1ccecc Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/385817
2014-03-21arm: tegra: soctherm: check HW max and min tempDiwakar Tundlam
Soctherm trip points are set in HW registers that take temperature in the range -127C to +127C. This causes the bug# noted below. Fix by checking temp before changing HW register. If threshold temp is over the range HW can support, we set it to the max. Also added a change to show the TSOSC STOP bit in debug output. Bug 1480200 Change-Id: I3c69ca1978ad17ec19af3e896d7e537fb5986ea5 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/382727 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com>
2014-03-19arm: tegra: soctherm: align usage of PMC_SENSOR_CTRL.BLOCK_SCRATCH_WRITE ↵Paul Walmsley
with the spec The SOC_THERM code attempts to write a '1' to PMC_SENSOR_CTRL.BLOCK_SCRATCH_WRITE to attempt to allow it to write to PMC scratch registers. However, a value of '1' indicates that scratch register writes should be *blocked*, not allowed. If this write were allowed to succeed - which it is not by the IP block - it would mean that the subsequent writes in the SOC_THERM code to program the PMIC shutdown commands into the PMC scratch registers are ignored. This would prevent the boot ROM thermtrip code from instructing the PMIC to shut down after a thermtrip reset initiated by SOC_THERM. Align the code with the PMC specification by explicitly clearing this bit. This patch currently has no practical impact since the boot ROM code currently clears this bit on at least some Tegra SoCs. However, by the specification, the kernel should take care to clear it to ensure that it can write to the PMC scratch registers. Of course, the SOC_THERM code should not be directly accessing PMC registers, since they are in a different IP block. Thanks to Aleks Frid for some discussion on this patch. Bug 1482109 Change-Id: I16d78e37143f6d63f2e772718bd8d7ff9a2d9f09 Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/382272 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-03-19ARM: tegra13x: move cold/vmin trips to socthermDiwakar Tundlam
Move vmin trip points that boost voltage below cold-temp to soctherm thermal zones on t132 norrin and bowmore (ffd and ers) boards. To support both legacy DVFS and CL-DVFS with vmin/cold trips, we register two cdevs with the same type, bound to the same trip_point and the DVFS back-end knows which one is active to take action. Changed soctherm driver to allow binding multiple cdevs to the same trip_point so the above mechanism works. Bug 1479500 Change-Id: Ibe54a71c6518a0500fec3fc31c95d3d27797e079 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/383354
2014-02-13arm: tegra: soctherm: fix warnings from static analysis toolsPaul Walmsley
Fix several issues noted by 'checkpatch.pl --strict', sparse, smatch, and cppcheck. The objective here is to help conform the coding style to the expectations of the upstream Linux kernel. These changes were implemented by Christina Guertin <cguertin@nvidia.com>, Alexander Karp <akarp@nvidia.com>, Wesley Nitinthorn <wnitinthorn@nvidia.com>, and Kexin Shi <kexins@nvidia.com>. Bug 1201644 Bug 1420828 Signed-off-by: Christina Guertin <cguertin@nvidia.com> Signed-off-by: Alexander Karp <akarp@nvidia.com> Signed-off-by: Wesley Nitinthorn <wnitinthorn@nvidia.com> Signed-off-by: Kexin Shi <kexins@nvidia.com> Cc: Diwakar Tundlam <dtundlam@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Change-Id: I70207f35f36974e46e17a96593469c2d97d934ad Reviewed-on: http://git-master/r/365879 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-02-12arm: tegra: soctherm: fix PDIV corruptionDiwakar Tundlam
In the change to adjust on vdd_core vmin, a wrong array index check in the 'for' loop caused PDIV register to be overwritten with incorrect values whenever the adjust routine was called. This caused negative temperatures to show in PLL-therm zone. This also impacts CPU and GPU temperatures when the rail is below the minimum. Bug 1363113 Bug 1457777 Change-Id: I67aece5b19821345dcb46e933fabbfe29e98e2cd Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/366841 Reviewed-by: Automatic_Commit_Validation_User
2014-02-04arm: tegra: soctherm: adjust on vdd_core vminDiwakar Tundlam
Adjust soctherm GPU and MEM zone configuration when vdd_core crosses boundary between high/low voltage ranges. (old ref bug 832603). Uses dvfs rail notification API. Bug 1363113 Change-Id: Ib7d4093df6513c2d8a2a76929ef24b983304d70f Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/361147
2014-02-03arm: tegra12: soctherm: fix throttling depth configTimo Alho
This patch allows configuring throttling parameters in a way that any of following register settings can be set to zero: * dividend * divisor * duration * step Change-Id: I77ee5e09a8d0f2b7a47fee33515b431c9b58dae1 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/361072 (cherry picked from commit 41bdc27fa72b6773e6dace0eaf0118c11823ac73) Reviewed-on: http://git-master/r/361952 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
2014-01-30arm: tegra12: soctherm: change oc1 interrupt print messageTimo Alho
TN8/P1761 enables OC1 throttling with interrupts enabled. Therefore change pr_warn() message of OC1 interrupt to pr_debug() message. Also return successfully from interrupt handler. Bug 1444676 Change-Id: Ic210162259df5880e0e537fdebfcc2bb9a799bd5 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/360426 (cherry picked from commit d7ed0dd7b83bf507589c7622129dbbac118b931e) Reviewed-on: http://git-master/r/359945 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2014-01-30arm: tegra: soctherm: add interrupt threshold and filteringTimo Alho
This patch makes OC_ALARM_*_CNT_THRESHOLD and OC_ALARM_*_FILTER registers configurable from soc_therm platform data. Also fix naming of ALARM_THRESHOLD_PERIOD to ALARM_THROTTLE_PERIOD as per register description. Bug 1444676 Change-Id: I2901e5cd0ccd893aabbf622169e20b90b5977ff7 Signed-off-by: Timo Alho <talho@nvidia.com> (cherry picked from commit 81e6acf47d4493eea8f615f89a1cc23279037603) Reviewed-on: http://git-master/r/359396 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2014-01-27arm: tegra: soctherm: Added kernel-doc to functionsChristina Guertin
SOC_THERM lacked proper documentation, therefore I added kernel-doc-nano-style documentation to some of the functions. The function soctherm_fuse_read_tsensor() was documented by Alex Karp and Christina Guertin. The function soctherm_init_platform_data() was documented by Kexin Shi and Christina Guertin. The function soctherm_debug_init() was documented by Alex Karp, Wesley Nitinthorn, Christina Guertin and Kexin Shi. Change-Id: I836f838dc7657d4322f3a63d796905b127cf9389 Signed-off-by: Christina Guertin <cguertin@nvidia.com> Reviewed-on: http://git-master/r/356754 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-27arm: tegra: soctherm: Added kernel-doc to functions for SOC_THERM driverWesley Nitinthorn
Added kernel-doc-nano-style documentation to several functions in tegra11_soctherm.c to make it easier for others to understand what the code does. regs_show()'s documentation was a collaboration between Alex Karp and Wesley Nitinthorn soctherm_throttle_program()'s documentation was a collaboration between Wesley Nitinthorn and Kexin Shi The rest of the documentation in this patch was written by Wesley Nitinthorn Change-Id: Idd1d3f4456a54ac02e95778d4d93b4c493a11ce4 Signed-off-by: Wesley Nitinthorn <wnitinthorn@nvidia.com> Signed-off-by: Kexin Shi <kexins@nvidia.com> Signed-off-by: Alex Karp <akarp@nvidia.com> Reviewed-on: http://git-master/r/356668 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-27arm: tegra: soctherm: add kerneldoc to functionsAlex Karp
Added kerneldoc-nano-style documentation to several functions in this file to make it easier for others to understand what this code does. comments about soctherm_fuse_read_tsensor() were a collaboration between Alex Karp and Chrissy Guertin. comments about regs_show() were a collaboration between Alex Karp and Wesley Nitinthorn. comments about soctherm_debug_init() were a collaboration amongst Alex Karp, Wesley Nitinthorn, Chrissy Guertin and Kexin Shi. All of the other comments in this patch were written by Alex Karp. Change-Id: I586d987d964f55a489588bad62dda5c071f624ea Signed-off-by: Alex Karp <akarp@nvidia.com> Signed-off-by: Wesley Nitinthorn <akarp@nvidia.com> Reviewed-on: http://git-master/r/357802 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-27arm: tegra: soctherm: added kerneldoc to several functionsKexin Shi
Added kerneldoc-nano-style documentation to several functions in this file to make it easier for others to understand what this code does. soctherm_init_platform_data() was a collabration between Kexin Shi and Christina Guertin. All of the other functions documented in this patch were written by Kexin Shi. Change-Id: Ieeb9e858f523719cc76986e4925309207d8f5676 Signed-off-by: Kexin Shi <kexins@nvidia.com> Reviewed-on: http://git-master/r/357874 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-23arm: thermal: soctherm: fix debugfs outputDiwakar Tundlam
Fixed debugfs nodes cputemp, gputemp, etc. to correctly return the temperature by converting raw register value. Bug 1176075 Change-Id: Iddbf3836729f5ebd60c9aa3c34ea87b2530d2246 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/358339 Reviewed-by: Automatic_Commit_Validation_User
2014-01-22ARM: tegra132: add soc_therm support for T132Peng Du
Change-Id: Iff0b9067e7df5279cf28ad88cb8994f29737cbcf Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/350710 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-07arm: tegra12: soctherm: fix soc_therm_oc nameTimo Alho
Change-Id: Ie7de2e8c32f2dd08337836ab58f77e078026c4a6 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/348412 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2013-12-12arm: tegra12: Fix light thermal HW throttlingDiwakar Tundlam
Fix light thermal HW throttling cdev registration and its cur_status Bug 1342361 Change-Id: Ie1ac458539d1525772089724caaad58eae85eca9 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/344514 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-12-10arm: tegra12: soctherm: GPU HW throttling WARDiwakar Tundlam
Allow enabling HW GPU throttling for thermal and OC alarms. Implemented WAR discussed in bug. Also modified debug output to show depth as percent as well. Bug 1415030 Change-Id: I3c1e401e820713d7f7290f089c42e71531700d28 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/338122
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 01:19:35 +0000