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2014-07-08ARM: tegra: dvfs: Update DFLL tune settings to P4v17Alex Frid
Added DFLL tune settings for new speedo ranges below 2180, and 2180... 2336. Bug 1442659 Change-Id: I8259d2e3de3ed5ca9b5a622700755711d82511f0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/429137 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
2014-07-08ARM: tegra: dvfs: Update CPU DVFS table to P4v17Alex Frid
Bug 1442659 Change-Id: Ie0f64869aa79cfd57ab31ca4096800bfb4e797a4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/429136 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
2014-06-26ARM: T132: update SoC therm caps, vmax trips tableIshwarya Balaji Gururajan
update SoC therm caps table and vmax trips table bug 1442659 Change-Id: I26cc83fd9f6fe2a2f806eed254e2d70ce00ff254 Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/427836 Reviewed-by: Harshada Kale <hkale@nvidia.com> Tested-by: Harshada Kale <hkale@nvidia.com>
2014-06-26ARM: tegra13: dvfs: Add GPU SiMon offsetsAlex Frid
Added GPU Vmin -20mV offset for high SiMon grade on Tegra13 platforms. Constructed the respective GPU DVFS table with offsets applied, and SiMon notifier to switch between tables w/wo offset. Since no SiMon grading is available only original DVFS table with no offset is used for now. Bug 1511506 Change-Id: I959ed2142e478b9693a5bc425ef2165b43210bab Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/425035 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-06-26ARM: tegra13: dvfs: Specify DFLL tuning SiMon maskAlex Frid
Specified DFLL tuning mask to toggle settings based on SiMon grade. Changed defaults used before SiMon grade is determined after boot to slower settings. Bug 1511506 Change-Id: Ibcf25c418fe0fa10af0778599a701f11a9f90719 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/424908 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-06-26ARM: tegra13: dvfs: Add CPU SiMon offsetsAlex Frid
Added CPU Vmin -20mV offset for high SiMon grade on Tegra13 platforms. Since no SiMon grading is available this offset is not actually applied. Bug 1511506 Change-Id: Ia7fa83db6a6ee003c0e1211c8a7fb9ac89630487 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/424907 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-06-11ARM: T132: Clocks: Update temperature dependent vmin for cpuBibek Basu
Update temperature dependent vmin for A01 cpu table version p4v4 Bug 1458402 Change-Id: I4a2200eda67278b6d2e3f2696f25c4779169e162 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/401361 (cherry picked from commit a25df4eef43bb682d70b2897ce8e2a6f5bdd9b61) Reviewed-on: http://git-master/r/421552 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-06-09ARM: T132: update SoC dvfs table for DSI, eDPIshwarya Balaji Gururajan
Update freq for DSI to 402M and sor to 162M at 800mV. Update SoC dvfs revision to p4v1l. Bug 1442659 Change-Id: I2f488d5d5bd2c0be577d4947f9f36d0c4a810596 Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/415053 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-06-09ARM: tegra: dvfs: Update DFLL tune parametersAlex Frid
- Changed Tune1 parameter according to recent characterization results - Made Tune0 selection forward looking: applied current settings to possible future speedo ids (if any is introduced). - Updated CPU DVFS version to p4v12. Bug 1442659 Change-Id: I3430fc43a3ff045fd6fbcbfddbe5feda4671a727 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/419772 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-30ARM: T132: Update SoC dvfs table for clocksIshwarya Balaji Gururajan
update sbus, host1x, mselect and sor0 clocks in SoC dvfs table to version p4v10 Bug 1442659 Change-Id: Ifa0127c9750d89a88af3e41a94d67bebf528286b Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/413420 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-05-29ARM: T132: Update SoC dvfs table for c2/c3 busIshwarya Balaji Gururajan
updat SoC dvfs table for c2/c3 bus and their clients Bug 1442659 Change-Id: I6897a82acc4cdbf26324e6e4fd3819b61b5c1a0e Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/413458 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-05-29ARM: T132: Update SoC dvfs tables for I/OIshwarya Balaji Gururajan
update SoC dvfs tables for I/O peripherals Bug 1442659 Change-Id: I9f96b131aa13b033b5db1941b7ffe04b0a5e9096 Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/413411 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-05-28ARM: T132: Update GPU DVFS tablesIshwarya Balaji Gururajan
update max freq to 918MHz and speedo_id to 2 for sku_fuse 0x83 Bug 1442659 Change-Id: Ie7c94baeb5769c8a271f94ba2442fd00183aad99 Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/410384 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-05-16ARM: T132: Update GPU DVFS tableIshwarya Balaji Gururajan
Update max freq to 852Mhz for speedo_id 1 Bug 1442659 Change-Id: Ie4a08691963996e6ed7d988948cc9bd2d85614a0 Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/409702 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-16ARM: tegra13: dvfs: Update CPU DVFS table to P4v8Alex Frid
Bug 1492902 Bug 1442659 Change-Id: Id9e6114fa05e38d21f59fd34e1804abdb456f193 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/402658 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-16ARM: tegra13: dvfs: Add CPU Vmin dataAlex Frid
Added CVB coefficients to account CPU Vmin dependency on speedo and temperature. Implemented CVB equations to calculate Vmin thermal profile. Bug 1492902 Bug 1442659 Change-Id: Ib039df6807880d1714550bd6b770d2c4e46e8ac0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/402657 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-16ARM: tegra13: dvfs: Set CPU DFLL tuning parametersAlex Frid
On Tegra13 A02 silicon set CPU DFLL tuning parameters as a function of chip speed. Bug 1492902 Bug 1442659 Change-Id: I03a5a419c60ffa86a360c58222b93279f25e3145 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/402656 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-06ARM: T132: DVFS: Remove cpu/soc voltage dependency beyond A02Krishna Sitaraman
Keep the voltage dependency for A01 and A02 and remove for later revisions. Change-Id: If354f1bf2ddb5cca8d8db2b7d9a72ebe9f2f6d6b Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Hridya <hvalsaraju@nvidia.com> Reviewed-on: http://git-master/r/401094 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-04-23ARM: t132: DVFS: update gpu DVFS tables to version p4v4Ishwarya Balaji Gururajan
update gpu dvfs tables to version p4v4 Bug 1442659 Change-Id: Ibbb10fc17ea5a3663759df85d9e657b29b1587dc Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/397260 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
2014-04-23ARM: T132: DVFS: Add sor0 clock to dvfs tableKrishna Sitaraman
soc dvfs version p4v7 Bug 1497005 Bug 1442659 Change-Id: I357db8a0c0417214a1a749cb1160ef5154a0933c Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/396661 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-28ARM: T132: DVFS: Soc dvfs table udpate version p4v4Krishna Sitaraman
Bug 1442659 Change-Id: I79941c7ca11344ec924663f5f1d24e08c44afb02 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/383443 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-03-28ARM: T132: DVFS: Update cpu dvfs table version p4v6Krishna Sitaraman
Bug 1442659 Change-Id: I4d04b30bb278468abadeddf605798e2cd7fb29a1 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/382228 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-03-13ARM:tegra:dvfs: update max pll_m rateRay Poudrier
Update max pll_m rate to 1200MHz to support 1200MHz emc freq for loki Bug 1452529 Change-Id: I8fcfe4ffd9bb423d78888911882ce474a4d9988d Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> (cherry picked from commit b8a928a34bc216e7fac36c983c13df2507ce3d6a) Reviewed-on: http://git-master/r/370215 Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com> Reviewed-on: http://git-master/r/379628 Reviewed-by: David Dastous St Hilaire <ddastoussthi@nvidia.com> Tested-by: David Dastous St Hilaire <ddastoussthi@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Tao Xie <txie@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-03-10ARM: tegra13: dvfs: Account for thermal floor slackAlex Frid
When calculating VDD_CORE floor imposed by VDD_CPU took into account that in dfll-mode VDD_CPU rail will be at/above current thermal floor however low is voltage specified in DVFS table for target frequency. Set margin above thermal floor to 30mV. Lower dependency constraint at VDD_CPU level 900mV from 870mV to 830mV (this limit was statically set higher than necessary because 900mV is a cold floor, and thermal floor slack was not accounted in resolution algorithm until this commit). Bug 1461646 Change-Id: I11e00e7077496150e86f5ef56efede40febba1e9 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/379284 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-07ARM: T132: Thermal: Enable Vmin boost based on temperatureKrishna Sitaraman
Change-Id: I9ad911ea2fc438b6863e785bd9a390f2ea639c79 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/373097 Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-07ARM: T132: Clocks: Update temperature dependent vmin for cpuKrishna Sitaraman
Update temperature dependent vmin for cpu table version p4v4 Change-Id: If20feaf65847e9682f9d92f6ad2100afd7d541a3 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/377956 Reviewed-by: Chao Xu <cxu@nvidia.com> Tested-by: Chao Xu <cxu@nvidia.com>
2014-03-06ARM: T132: DVFS: Soc dvfs table updateKrishna Sitaraman
First soc dvfs post silicon table update. Version p4_v3 Change-Id: I2850ad3806cf89eb1357946b42280de0e7f8918c Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/375067 Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-04ARM: T132: dvfs: Update cldvfs table v4Krishna Sitaraman
Add PLLX based table for A01 and CLDVFS based table for A02 Change-Id: Ibbec5b5d0dc9b43f6e4447791675a7226c732419 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/375803 Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-04ARM: tegra13: dvfs: Add VDD_CORE dependency on VDD_CPUAlex Frid
Bug 1461646 Change-Id: I84e9d3f5a2cc17451f32c682a1fcd10680a7c838 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/369112 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-03ARM: T132: GPU DVFS table updateKrishna Sitaraman
Adding first post silicion gpu dvfs table (version p4_v3) Bug 1442659 Change-Id: I3bf09c4134a3bb3afe5de4a49c3ecf11993025b5 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/375029 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-02-21arm: tegra13: add A02 CPU DVFS tableAdeel Raza
Add the A02 CPU DVFS table. Right now the A01 and A02 CPU DVFS tables are identical except for the speedo_id. In the future the A02 CPU DVFS table will be updated. Bug 1455768 Change-Id: Ia7461e5aa09501413ef9cc0b8c979d5a6b78d472 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/369014 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-02-10ARM: T132: Clock: Set minimum vdd_core to 1.0vKrishna Sitaraman
Update sbus to operate at 1.0V or higher forcing vdd_core to operate atleast at 1.0v Change-Id: I0dd488fbe9f5683e79d0f16ff56a41221758c24c Reviewed-on: http://git-master/r/356803 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361715 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Shashank Garg <sgarg@nvidia.com>
2014-02-10ARM: T132: DVFS: Add 1st post silicon cpu dvfs tableKrishna Sitaraman
Update cpu cl-dvfs parameters with first post silicon dvfs table Change-Id: I9cfc7afb4933d837e109d35d1569c7277c0e4235 Reviewed-on: http://git-master/r/355734 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361712 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Shashank Garg <sgarg@nvidia.com>
2014-02-08ARM: T132: Clocks: Limit gpu to 804Mhz and vmin at 850mVKrishna Sitaraman
As per recommendation from silicon validation team Change-Id: I5f9ed90db05b7056cc5a3c9dc73df9ac00f4ed8c Reviewed-on: http://git-master/r/360031 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361709 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com>
2014-02-03Tegra: ARM: T132: Clock: Allow higher emc frequenciesKrishna Sitaraman
Change-Id: I959bbed9d926f7b5861610f1df1e5d3a53f2511f Reviewed-on: http://git-master/r/355245 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361684 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
2014-02-03ARM: Tegra132: DVFS: Add version names for initial dvfs tablesKrishna Sitaraman
Change-Id: Ic91fcb02474b4bfb28bcf943d5a2726cbdd760c7 Reviewed-on: http://git-master/r/355258 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361682 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
2014-01-22T132: DVFS: Update PLLX safe tableKrishna Sitaraman
Increase voltage for all PLLX entries by 100mV to fix boot issue on slow and fast boards. Change-Id: I35e3770eb5a6799f668a83247256072386da8c98 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/353432 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-01-21Tegra13: DVFS: Update parameters to prepare for cldvfsKrishna Sitaraman
Change-Id: I228ba5cc4f67c5ad4dac6b3810da454296930b6d Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/350004 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: DVFS: Add safe table for gpuKrishna Sitaraman
gpu safe table has 50mV margin over T124 production SW setting. Frequency limit was removed. Bug 1394146 Bug 1426244 Change-Id: Id0eae3bd99efe38cc2a417217c45c6138e9e1795 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/347665 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: DVFS: Add safe dvfs table for cpuKrishna Sitaraman
Adding safe cvb table for cpu with 20% margin. Remove any limits on max cpu voltage. Bug 1394146 Change-Id: Ic293bd51d08a502999b2f9eec51c67b19fff3f47 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/347173 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra12: DVFS: Adding dvfs and speedo files for T132Krishna Sitaraman
Creating dvfs and speedo files separately for T132 and reducing the max gpu speed to 252Mhz Bug 1426244 Change-Id: Ie274b134d7704ff02560cb1658d4d1814a8487be Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/346662 Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 05:35:41 +0000