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2016-06-29tegra: fix dvfs gcc 5.2 build errorMarcel Ziswiler
This fixes the following GCC 5.2 built time error: arch/arm/mach-tegra/tegra_cl_dvfs.c: In function 'monitor_get': arch/arm/mach-tegra/tegra_cl_dvfs.c:372:8: error: 'v' may be used uninitialized in this function [-Werror=maybe-uninitialized] *data &= CL_DVFS_MONITOR_DATA_MASK; ^ arch/arm/mach-tegra/tegra_cl_dvfs.c:2949:6: note: 'v' was declared here u32 v, s; ^ arch/arm/mach-tegra/tegra_cl_dvfs.c: In function 'cl_dvfs_calibrate': arch/arm/mach-tegra/tegra_cl_dvfs.c:372:8: error: 'data' may be used uninitialized in this function [-Werror=maybe-uninitialized] *data &= CL_DVFS_MONITOR_DATA_MASK; ^ arch/arm/mach-tegra/tegra_cl_dvfs.c:902:11: note: 'data' was declared here u32 val, data; ^ Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2014-06-26ARM: tegra: dvfs: Add SiMon grading to DFLL tuningAlex Frid
Added dependency of DFLL tuning settings on SiMon grading as follows: - Selected set of tuning bits specified by platform specific SiMon mask is toggled when SiMon grade is changing from zero to non-zero (high) grade, or vice versa. - The same toggle mask is applied to settings in low and high voltage tuning ranges. - SiMon mask can be applied only while DFLL is tuned for low voltage range Bug 1511506 Change-Id: I10cb69ea30c7773042c640d41e0dc0c99038ab7d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/424906 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-06-09ARM: tegra: dvfs: Increase DFLL force guard-bandAlex Frid
Increased DFLL force voltage request guard-band below maximum voltage from 1 LUT step to 2 LUT steps per characterization results. Bug 1442659 Change-Id: Ie34d19174372bc85aa3c44391542406bc6a564de Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/419773 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-16ARM: tegra: dvfs: Defer calibration on force valueAlex Frid
Deferred DFLL calibration if last sent voltage is at the initially forced request output level. It is needed to avoid false interpretation of high voltage when power management micro-controller re-sends DFLL request underneath CLDVFS driver running on CPU. Bug 1492902 Change-Id: I0757469ff432818d1aadb616accba01136345257 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/402659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-10ARM: tegra: dvfs: Use hrtimer for DFLL tuningAlex Frid
Used high resolution timer for DFLL tuning. Since Tegra13 is running with HZ = 100, regular timer resolution 10ms is too coarse for 1-2ms tuning delay. Change-Id: I10adf8518973256bb1c1e6129af60893c02ceabf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/393776 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-09ARM: tegra: dvfs: Calibrate DFLL tuning thresholdAlex Frid
Currently switch from low to high voltage tuning ranges is based on fixed characterized V/F curve: high range tuning settings are used if predicted voltage for DFLL target rate is above high range floor plus fixed margin. If margin is too low this result in CL-DVFS saturation at floor voltage with actual frequency above the target. If margin is too high the low tuning range is over-extended with DFLL running at unnecessary high voltages. Tuning range selection algorithm introduced by this commit: high range tuning settings are selected if predicted voltage for DFLL target rate is above high range floor level (no margin). Actual DFLL rate at high range floor is calibrated using existing DVCO minimum rate calibration procedure. Fixed margin is used only for initial approximation of floor rate before calibration starts. All target rates between fixed estimated floor and calibrated high range minimum rate are achieved using output skipper at floor voltage. Thus, necessary accuracy of output rate is assured with high range tuning settings and low output voltage. Bug 1492902 Change-Id: I7ac27f62423e67a3f09213033c32aaad7871da2b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/393224 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-09ARM: tegra: dvfs: Tune DFLL low at coldAlex Frid
Added an option to tune DFLL low in the entire voltage range while temperature is below minimum trip-point; still different tuning setting are used in low and high voltage ranges while temperature is above cold trip-point. For now, this option is disabled on all Tegra platforms. Bug 1492902 Change-Id: Ibf080279b034522add8eed4da15617b59ac1a59a Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/391123 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-08ARM: tegra: dvfs: Update DFLL calibrationAlex Frid
- Added DVCO minimum rate and output skipper update to DFLL calibration timer callback (rather than updating skipper exclusively on new rate request, or temperature change). - Re-started calibration timer whenever rate request is crossing down DVCO minimum rate level - Made sure calibration timer delay never falls below specified interval - Increased calibration down range (necessary if characterized DVCO minimum rate is overestimated - may now be the case on Tegra13 parts) - Added calibrated rate before clipping to range boundaries to debug print. Bug 1492902 Change-Id: I095b04f1f18511652a19c776fa003474c8c1109c Signed-off-by: Alex Frid <afrid@nvidia.com>
2014-04-03ARM: tegra: dvfs: Compare set and required DFLL VminAlex Frid
Added CL-DVFS driver interface to compare set and required DFLL Vmin. Commonly while operating in closed loop these two levels are equal. However, when DFLL is disabled or in transition to/from disabled state temperature or SiMon grade changes are not immediately delivered to PMIC, and the levels may be different. Bug 1343366 Change-Id: I7ecd782b37ddb5e3ca7a0f0dfa658ebb526e9fc6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/391050 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-31ARM: tegra: dvfs: Swap CL-DVFS barrier and read fenceAlex Frid
To assure completion of the previous writes through Tegra interconnect CL-DVFS driver used memory write barrier followed by read fence. Removed the preceding memory barrier, since it has no additional to read fence effect (given Tegra IO mapping as device). Added barrier after read fence. The latter is needed to avoid partial overlap of read operation and propagation delay after read (if any). Such overlap is possible because architectural timer used as delay counter is not MMIO register. Bug 1484343 Change-Id: Ic0bcbeb980e5b728e5b1ee949f1aacfe94309931 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/390284 Reviewed-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2014-03-28ARM: tegra: dvfs: Fix compiler cast warningAlex Frid
Fixed compiler cast warning in DFLL SiMon callback. Change-Id: Ie764fbbed03535ac5291e444807145792361d85f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/388161 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-28ARM: tegra: dvfs: Add delay after DFLL enableAlex Frid
Added 1us propagation delay after DFLL is enabled in open loop mode as a double-precaution on top of already inserted memory barrier and read fence. Change-Id: Iab6a61833b5ef087c8f4da57b8d78d6a571dbb9e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/389581 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-20ARM: tegra: dvfs: Add DFLL output clamping interfaceAlex Frid
Added DFLL output voltage clamping interface: set maximum and minimum voltage limits the same to the lowest safe (at current temperature and tuning range) level. In this state target clock rate is ignored, DFLL output rate is determined by the clamped limit. Interface has clamp control parameter, and can be used to release clamping as well. In any case clamping is released when switching out of closed loop mode. This interface is intended to be used during SiMon grading only. Bug 1343366 Change-Id: Id004f520bdfc85376e3ff00e83041a3be7d79ee4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/383658 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-19ARM: tegra: dvfs: Re-factor DFLL output force controlAlex Frid
Implemented output force register access functions, and re-factored clients, respectively. Updated debugfs force output control: enabled I2C PMIC control, fixed order (swapped) of locking DFLL register access and enabling access clock. Change-Id: I33d656dfb384e97f55b46a0404578e6b0bc9b873 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/383657 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-10ARM: tegra: dvfs: Check DFLL unlock voltage outputAlex Frid
When switching to open loop mode added check to confirm that last DFLL voltage request delivered to PMIC is above current Vmin limit. Provided 2 grace sample periods for delivery after Vmin update with temperature, and before the open loop switch if check has failed. Scenario addressed by this commit: Vmin thermal floor update followed by unlocking DFLL before new transaction to PMIC has a chance to start. Change-Id: I9c708a7566a0e94f981abe7859d1e0164602ffba Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/376249 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-04Revert "ARM: T132: dvfs: Update dfll request ratio for 1st post silicon table"Krishna Sitaraman
This reverts commit 3ed1b1fe808141a2ab08af77a2381d294ff53b1b. Bug 1440923 Change-Id: Ibd92221abdcc60bbacba9639e3f8e232d7dff49f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/375802 Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-03ARM: tegra: dvfs: Update DFLL Fmax@Vmin calibrationAlex Frid
- Completely skipped calibration if calibration delay is zero (used to only stop calibration timer in this case, but still calibrated on request) - When storing calibration results checked Vmin consistency. In theory high tuning low limit may push calibrated rate higher current thermal floor; in this case default characterized Fmax@Vmin is always used as a base for the calibration (instead of previous calibration result). Change-Id: I2419e0d5b278e97108d94db34014652aad7f8f74 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/376248 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-24ARM: tegra: dvfs: Add 1st CL-DVFS out disable fenceAlex Frid
Added read fence after CL-DVFS output is disabled first time during initialization. This is necessary to avoid spurious I2C transaction when updating output limits on tegra SoC that has I2C output enable control register and output limits register separated in different apertures. Bug 144152 Change-Id: Ifd5931bf79689f88389bbff3d7bd27f522c98b5c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/373338 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-21ARM: tegra: dvfs: Add CL-DVFS driver compatibilityAlex Frid
Added CL-DVFS driver compatibility with Tegra132 SoC. Expanded debug prints, since Tegra132 has separate MMIO ranges for loop control and I2C registers. Bug 1442709 Change-Id: I7c87271fb632162cbb9833b535699efc719709d2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/372771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-20ARM: tegra: dvfs: Use safe DFLL caps below minimaxAlex Frid
If some other rail depends on DFLL rail, set maximum output cap to match voltage from safe dvfs table used by s/w DVFS on other rails to resolve dependencies Otherwise, with no dependencies leave a room for regulation up to minimax level. In any case keep maximum cap at/above forced limit if PMIC undershoot guard-band is specified. The guard-band must be within rail dependency slack. Bug 1461646 Change-Id: I6f511b1502c96d5796cfb72fda0b343bcf1b4ff5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/369765 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-18ARM: tegra: dvfs: Add access to DFLL thermal floorsAlex Frid
Since SiMon grading offsets applied to CPU Vmin only if DFLL is used as a clock source, thermal floors in DFLL and PLL modes can now be different. Although CL-DVFS driver maintains its own copy of thermal floors properly updated with SiMon offsets, this updated floors are not accessible by legacy DVFS mechanisms that are still engaged in DFLL mode: rail stats gathering, DVFS debugfs tree, and safe voltage setting before cluster switch (using PLL mode floors is still safe in this case, but unnecessary push voltage higher). Hence, this commit exposed DFLL thermal floors to legacy DVFS. Bug 1343366 Change-Id: Ibd0bcd577f72f6022a4a83faf1894bec2361c151 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/368124 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-09ARM: T132: dvfs: Update dfll request ratio for 1st post silicon tableKrishna Sitaraman
DFLL VCO will run at twice the requested frequency and clk divider will be set to 2 to match the requested value. This change to be removed after proper DFLL settings are available for T132. Bug 1440923 Change-Id: I89c49d11677831677a385a0c4ef2d9bee4761693 Reviewed-on: http://git-master/r/354033 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361711 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com>
2014-02-07ARM: tegra: dvfs: Allow no-tracking DFLL limit readAlex Frid
Check start tracking argument NULL-pointer in DFLL limit read interfaces, and just return limit value if the caller does not intend to track. Change-Id: I95fa2e23151666b73ae584458ac983645657e711 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/364700 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-07ARM: tegra: dvfs: Apply guard-band to tuning thresholdAlex Frid
Applied PMIC undershoot guard-band to tuning threshold. Although tuning start hysteresis already effectively provides such guard band the values of these two parameters are driven by different h/w: power tree for undershoot guard band and SoC characterization for tuning start hysteresis. Hence, this commit. Bug 1285525 Change-Id: I3c5a9fda8aa1499b249a3384e29003edfcbcb00c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/356918 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-03ARM: tegra: Move PWM PMIC binding into DFLL sub-nodeAlex Frid
Updated definition of DFLL DT binding: moved PWM PMIC integration to DFLL device sub-node (from root node). Modified DT parsing in CL-DVFS driver accordingly. Bug 1442709 Change-Id: I1d3919589ae95c7f3c86c435716577d433c73e4d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/362657 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30ARM: tegra: dvfs: Add PWM DFLL device tree supportAlex Frid
Parsed DT data for DFLL PMIC with PWM interface. This is in addition to already implemented DT parsing for DFLL PMIC with I2C interface. Full DFLL DT binding is defined in Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt Bug 1442709 Change-Id: Id6e2a5cce9b8dea158a2a6f811b5c065ddee0e1d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/361881 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30ARM: tegra: dvfs: Track CL-DVFS limits changeAlex Frid
Added to CL-DVFS data voltage limits (Vmin, Vmax) and the respective sequential counters to track run time limit updates. Implemented limit writers in CL-DVFS driver to record the limits in mV (in addition to already existing recording in CL-DVFS output steps). Provided limit reader interfaces with update/retry checking. Bug 1343366 Change-Id: Ia42b0a0142f5ae44ebb83cd15e47408e5fd3f564 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/349282 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30ARM: tegra: clock: Update DFLL private data accessAlex Frid
- Added Tegra private interface to get CL-DVFS data from DFLL clock source (set interface already exists) - Checked DFLL flag in both set/get interfaces - Added tegra_dfll prefix to the names of both interfaces Bug 1343366 Change-Id: If08b4a58f2f494e985a6c08ac9ffb338d20feb02 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/361296 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-29ARM: tegra12: Move DFLL bypass device registrationAlex Frid
Moved registration of DFLL bypass device from CL-DVFS driver probe to board regulator init. Thus the initialization/probe order of DFLL bypass device and driver, CL-DVFS driver and legacy DVFS is now the same as if all devices are defined in device tree (although DT is not used, yet). With changed order, set initial voltage for DFLL bypass regulator constraints to boot (rather than nominal) level. Bug 1442709 Change-Id: I96e8b38c1f3969e7e46913ef659fe49bb81892c4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/358586 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-23ARM: tegra: dvfs: Parse DFLL device tree dataAlex Frid
Added parsing of DFLL device tree data in tegra CL-DVFS driver probe. Implementation is backward compatible with the specification of DFLL platform data in board files - if the latter is present, DT data is ignored. Only PMIC with I2C interface can be integrated with DFLL data in DT. For PMIC with PWM interface integration data must still be specified as static platform data in the respective board file. Bug 1442709 Change-Id: Ie481c0f766b13308449199168e3567711a8834f3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/357461 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2014-01-17ARM: tegra: dvfs: Re-factor DFLL output limits controlAlex Frid
Consolidated DFLL output limits control into one function called from both open and closed loop configuration. Bug 1343366 Change-Id: I2a91265485ca6e306043c5d7668239f23186da0b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/356855 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-17ARM: tegra: dvfs: Set DFLL clock data in common codeAlex Frid
Set CL-DVFS data for DFLL target clock by CL-DVFS driver probe code (instead of per-chip DFLL clock initialization). Change-Id: I742093570245f6ef97dfdc908c538de6ff4c338e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/356964 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-17ARM: tegra: dvfs: Build DFLL voltage selection mapAlex Frid
Added an option to build DFLL voltage selection map dynamically, if static map is not provided in platform data. Two building algorithms: - Use regulator interface to match regulator selector to voltage level, and linear conversion of selector to register values. Applied when vdd supply with I2C interface and internal voltage selection register is connected. - Directly map PWM duty cycle to voltage level linearly, and record number of high PWM steps as register setting. Applied when vdd supply driven by DFLL PWM data output is connected. Conversion coefficients are added to DFLL platform data, and in both cases above can be specified instead of static voltage map. Change-Id: I1c41e7d13df564affb5cb02441d57a90128c14a4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/356954 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-07ARM: tegra: dvfs: Fix DFLL I2C mode calibrationAlex Frid
Properly extracted last I2C sent value during DFLL minimum rate calibration in I2C mode. Change-Id: I38dcf32d42a8e550bec4df88722672f4c2cc97af Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/352456 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-13ARM: tegra: dvfs: Exempt top floor from SiMon offsetAlex Frid
Made sure that SiMon offset for VDD_CPU rail is not applied to maximum thermal floor (lowest temperature entry in thermal floor profile). Bug 1343366 Change-Id: Ide935b1402d4e55350db9b182b20a58858e9c78b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/344511 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-13ARM: tegra: dvfs: Handle SiMon CPU notificationAlex Frid
Registered DFLL call-back with SiMOn notification chain. When SiMOn grade for DFLL rail (VDD_CPU) is changed, applied the respective offset to the DFLL thermal floor profile. Bug 1343366 Change-Id: I5ee2c94473a6ec165d7ec9d4238c3327f67abcfb Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/340230 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-11ARM: tegra: dvfs: Fix DFLL voltage mappingAlex Frid
Fixed DFLL voltages mapping when maximum voltage is reached by the frequency below the top one: map all the rest frequencies to maximum DFLL output. Bug 1422196 Change-Id: I58394fe54cd6b3196c8adfac911a812b1c4cca1e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/343868 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-09ARM: tegra: dvfs: Update DFLL profile debugfs nodeAlex Frid
Updated temperature trip-point output format to indicate range the respective profile limit is applied in: floors below trip-point, caps -- above. Fixed typo in thermal floors header line. Change-Id: I299d48cafadddb2fc90fb32ecbcbf9f499b3c16c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339681 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-04ARM: tegra: dvfs: Support non-sync DFLL monitorAlex Frid
Added platform flag to indicate DFLL monitor h/w that do not allow synchronization because DATA_NEW status bit can not be used. For any monitor read just skipped synchronization, and rely only on already implemented check for consistency of consecutive reads. In addition, replaced wait for data in calibration procedure with explicit delay to make sure data has been monitored at least one full sample period. Bug 1401470 Change-Id: Ia3b21ff3db8c46f1fc3167634e337888201eb4e2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/337555 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-04ARM: tegra: dvfs: Work-around DFLL monitor fluctuationsAlex Frid
Reading DFLL frequency and voltage monitor at the same time data is updated by h/w may return intermediate values. Hence, any usage of monitored data (DFLL minimum rate calibration, reading of last voltage output in DFLL bypass mode, debugfs interfaces) must be synchronized with monitor DATA_NEW status. Still monitor outliers are possible, and their effect should be mitigated as well. To address monitor output fluctuations this commit: - added synchronization with DATA_NEW for all monitor read cases (so far, only calibration procedure was synchronized) - added a simple check-filter for consistency of consecutive reads - limited calibration step upward to half of reference frequency (partially reverted commit 39256aec5020e07263f4fc1fe673ed88dae026e9 that introduced jump up to the measured rate in a single calibration sample). Bug 1401470 Change-Id: I8ef89adc3ba5de36d38bdffaa7b39503def8d8b5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/337527 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-15ARM: tegra: power: Fix DFLL bypass ops return typeAlex Frid
Fixed DFLL bypass get_voltage_sel() interface return type (changed < unsigned int > to < int > - matching regulator core prototype). Change-Id: I836aa6ca17784307b76b61c4d40347152a78af9b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/331301 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-11-15ARM: tegra: dvfs: Update DFLL debugfs profile nodesAlex Frid
- added DFLL tuning profile to debugfs - added min rates information to thermal floor profile Change-Id: I35db05de780b73a691ebfd61937c8d894799b84c Signed-off-by: Alex Frid <afrid@nvidia.com>
2013-11-07ARM: tegra: dvfs: Split CL-DVFS registers accessorsAlex Frid
In some h/w configurations CL-DVFS module registers have two different address bases: one for I2C control/status registers, and one for all other registers. Separated registers accessors accordingly. Change-Id: I4e72e0a643b1870a77564511763dad9d8bd52804 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/325933 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-04ARM: tegra: dvfs: Allow GPIO # 0 for DFLL PWM controlAlex Frid
Zero is a valid GPIO number. No need to bail out when GPIO # 0 is specified as DFLL PWM buffer control. Also no need to request GPIO for direct one-wire PWM configuration. Respectively updated CL-DVFS initialization. Change-Id: I663101d04e41311989340e635144e3fde872721a Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/325937 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-04ARM: tegra: dvfs: Fix DFLL undershoot guard-bandAlex Frid
Fixed output voltage mapping for DFLL undershoot guard-band calculation in PWM mode. Change-Id: If397c476adf41167e4c61aa97c618eba1fed57b3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/325936 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-30ARM: tegra: dvfs: Show DFLL thermal profiles in debugfsAlex Frid
Change-Id: Id955390bec1a4edd2f166c29776e964c5e04dcbf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/304159 GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-16ARM: tegra: dvfs: Don't enbale DFLL bypass on LP clusterAlex Frid
Since Cl-DVFS PWM logic is on G CPU power rail, keep DFLL bypass output in PWM mode disabled when running on LP CPU cluster. Change-Id: If2325fb824bc8f812e43e479abf43658d5550b70 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/299263 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-14ARM: tegra: dvfs: Explicitly enumerate CL-DVFS PWM busesAlex Frid
Defined explicit enumeration for supported Cl-DVFS PWM configurations: - 1-wire bus with external buffer between CL-DVFS data output and PMIC input - 1-wire bus with direct connection from CL-DVFS data output and PMIC input - 2-wire bus with direct connection from CL-DVFS data/clock outputs and PMIC inputs Re-factored PWM control code to use this explicit definitions instead of inferring bus configuration from gpio and/or pingroup specification in platform data. Populate bus enumerations entries in platform data on platforms that use Cl-DVFS PWM interface (ardbeg and loki Tegra12 platforms). Bug 1349163 Change-Id: I1af3a7c2ee189f891b7639d4cbed9f057355b9cf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/298708 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-26ARM: tegra: dvfs: Limit CL-DVFS calibration rangeAlex Frid
Made sure CL-DVFS calibration range does not exceed maximum cpu frequency. Change-Id: Idad9bc1dba0a269fc25ec4179b1eea7915680a75 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/257756 (cherry picked from commit 4ffce3a53ab46894a1cbb156d7ca2d0558c2ca85) Reviewed-on: http://git-master/r/274915 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-26ARM: tegra: dvfs: Prevent CL-DVFS map allocation overflowAlex Frid
Instead of generating BUG() when number of CL-DVFS output map entries exceeds look up table size, store maximum voltage mapping, and abort allocation when last available slot is reached. Change-Id: Ibff18a82e4efa3729f3e0641473acb826429a8e5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/248945 (cherry picked from commit 38c68198819c6fb1d2c9cff3d2e498b5f9a25e23) Reviewed-on: http://git-master/r/254680 (cherry picked from commit e2af4d6762b2cfe2353ee9f1394442245e99b769) Reviewed-on: http://git-master/r/274914 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-29 06:26:04 +0000