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path: root/arch/arm/mach-tegra/tegra_simon.c
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2014-05-20ARM: tegra: power: Track grading interval with timerAlex Frid
Added kernel timer to track grading interval. Check timer expiration flag in grading callback instead of reading and checking time directly. It reduced some CPU cycles within each callback invocation. Bug 1343366 Change-Id: I6ba901e34b737cae760ead944ee344722d2eb47c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/400717 (cherry picked from commit 228c7221be7d39724f739b3dc563ce4c9722dc99) Reviewed-on: http://git-master/r/407058 (cherry picked from commit f5ce03476dcc33950082a9a88be27d793a629a04) Reviewed-on: http://git-master/r/410539 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-05-06ARM: tegra: power: Remove fake SiMon graders on Tegra13Alex Frid
Change-Id: I52f134c896bab6a91556e2c2078e82ff4cab6d45 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/398600 (cherry picked from commit e2243720d0f3754a4ef772bec0ff3e9fcec62972) Reviewed-on: http://git-master/r/403800 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-28ARM: tegra: power: Fix SiMon variable name spellingAlex Frid
Bug 1343366 Change-Id: Ieedc742803f15947e1ab1f2d06436e0cb53b0440 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/388163 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-27ARM: tegra: power: Add SiMon grading WDTAlex Frid
Added SiMon grading watch-dog timer for each domain. It is running while domain grade is above zero. If WDT expires domain grade is reset to default zero. Since it is possible to modify grade concurrently by grading and WDT callbacks, added domain grade lock to serialize grade updates in both callbacks as well as in debugfs grade write operation. Bug 1343366 Change-Id: Id907878c478b5ac581905a04a600c37505721dae Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/387442 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-25ARM: tegra: power: Set CPU SiMon grading rate to 850MHzAlex Frid
Bug 1343366 Change-Id: I6ab3e31ec13097862cf29654d0bfe27cfc25c326 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/384702 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-25ARM: tegra: power: Clamp DFLL voltage for SiMon gradingAlex Frid
Clamped DFLL voltage limits at minimum during CPU SiMon grading, so that voltage would not fluctuate during grading for sure (with previous approach - grade after frequency request is low enough to saturate DFLL at minimum - there was still a possibility for fluctuation). Bug 1343366 Change-Id: I390f67e3b1bb38e648965f4dc8159a57270eebcd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/384700 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-20ARM: tegra: power: Restart SiMon grading from debugfsAlex Frid
Restarted SiMon grading every time grade is changed via debugfs. Bug 1343366 Change-Id: Ic466dee600fb4270fb969dc50f49c96b7ac3b1ae Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/384124 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-20ARM: tegra: power: Add SiMon min grading temperatureAlex Frid
Added minimum grading temperature to SiMon grader description. Updated grading callbacks accordingly. Set minimum temperature to 20C for now. Renamed grading rate and voltage limits, to make it clear that these are maximum limits (unlike temperature minimum limit). Bug 1343366 Change-Id: Ifbd65b0f4bfda1a046351252ae2904f2e2922a04 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/384123 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-17ARM: tegra: power: Allow SiMon high grade onceAlex Frid
Updated SiMon grading policy so that lowering high (non-zero) grade back to zero automatically stops grading completely. Bug 1343366 Change-Id: I1d94b071eba7bfdd4371958d018a702bf58b8cb5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/382336 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-17ARM: tegra: power: Add SiMon voltage settle delayAlex Frid
Added voltage settling time to SiMon grader description, and delay grading respectively. Bug 1343366 Change-Id: I0eb476cea75a51d015f9dd0c3686e2f52f31a8cb Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/382334 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-17ARM: tegra: power: Add SiMon grader descriptionAlex Frid
- Combined platform/chip specific SiMon grader data into tegra_simon_grader_desc structure - Defined tegra_simon_add_grader() interface for grader driver to pass grader description to SiMon core - Renamed ..._grade_update functions to ..._grade_notify to properly reflect the actual operation - Modified SiMon domain debugfs to send debug grade notification even when no grader description is added - On Tegra12 added fake GPU and CPU graders that always report safe low grade Bug 1343366 Change-Id: I51a9bea159a7931d35e7b57b867132b1d6fb289e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/382292 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-14ARM: tegra: power: Bypass thermal zone lock in SiMonAlex Frid
Bypass thermal zone lock when calling get temperature interface from SiMon callback to avoid ABBA dead-lock (thermal zone lock also covers cooling device update that locks CPU/GPU clock rate interfaces that are calling SiMon grading callbacks). Bug 1343366 Change-Id: I319d26dde1a79752f43f217b40279231152646c9 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/367477 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-03ARM: tegra: power: Simplify SiMon GPU grading initAlex Frid
Simplified initial GPU SiMon grader registration with vdd_gpu regulator by using DVFS rail interface (instead of creating/destroying temporary regulator consumer). Bug 1343366 Change-Id: I9e0c50c697856eefbde08bf5c2f07b37477f8c31 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/360765 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30ARM: tegra: power: Limit SiMon support to Tegra12Alex Frid
Limited SiMon grading support to Tegra12 platforms, for now. Bug 1343366 Change-Id: I78b3a6084a14e3f6a57bdb78cbfe47d7e5b8c271 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/355379 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30ARM: tegra: power: Add SiMon CPU grading call-backAlex Frid
Added SiMon CPU grading callback to CPU rate post-change notification chain. This guarantees constant frequency during grading. Grading is executed when running on G-CPU, with DFLL as clock source, at rate low enough for DFLL to saturate at minimum voltage at any temperature. It is still possible that DFLL Vmin changes during grading because of temperature fluctuation. In that case grading results are discarded. First grading after boot can be executed anytime the conditions above are met, next grading is always separated by the grading interval from the last successful grading. Bug 1343366 Change-Id: Id1caa346c957afb95d2006132fff9ad7bbf54586 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/349283 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-06ARM: tegra: power: Add SiMon GPU grading call-backAlex Frid
Added SiMon GPU grading callback to vdd_gpu post-change notification chain. This guarantees constant voltage during grading. First grading after boot can be executed anytime when GPU voltage is below specified threshold, next grading is always separated by the grading interval from the last successful grading. Current setting for threshold (0.85V) and interval (about 8 weeks) are placeholders and subject to change. Bug 1343366 Change-Id: Id774ee1f3f60071d1ad732901cdd80dd6604dae8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/347825 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-06ARM: tegra: power: Define SiMon grading deviceAlex Frid
Defined tegra SiMon grading device data structure. Moved SiMon domain grade notification to work function. Re-factored SiMon debugfs entries, accordingly. Bug 1343366 Change-Id: Id12f4b7252051701081a9f2a0b1f638c178f4a71 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/347824 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-10ARM: tegra: power: Add initial SiMon supportAlex Frid
Defined tegra Silicon Monitor (SiMon) domains: CPU, GPU, core. Added SiMon domain grade notification chain, and debugfs entries. Bug 1343366 Change-Id: Ieff7ca57af48e5a5a2224fd6800bcccabf8eef5e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/338521 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 01:45:39 +0000